NXP Semiconductors K32W032S1M2_cm4 2024.06.02 K32W032S1M2CAx_cm4,K32W032S1M2VPJ_cm4 CM4 r0p1 little true true 3 false 8 32 ADC0 ADC ADC0 0x0 0x0 0x304 registers n ADC0 52 CFG ADC Configuration Register 0x20 32 read-write n 0x0 0x0 ADCKEN ADC asynchronous clock enable 31 1 read-write ADCKEN_0 ADC internal clock is disabled 0 ADCKEN_1 ADC internal clock is enabled 0x1 CALOFS Configure for offset calibration function 15 1 read-write CALOFS_0 Calibration function disabled 0 CALOFS_1 Configure for offset calibration function 0x1 PUDLY Power Up Delay 16 8 read-write PWREN ADC Analog Pre-Enable 28 1 read-write PWREN_0 ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. 0 PWREN_1 ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any detected trigger does not begin ADC operation until the power up delay time has passed. 0x1 PWRSEL Power Configuration Select 4 2 read-write PWRSEL_0 Level 1 (Lowest power setting) 0 PWRSEL_1 Level 2 0x1 PWRSEL_2 Level 3 0x2 PWRSEL_3 Level 4 (Highest power setting) 0x3 REFSEL Voltage Reference Selection 6 2 read-write REFSEL_0 (Default) Option 1 setting. 0 REFSEL_1 Option 2 setting. 0x1 REFSEL_2 Option 3 setting. 0x2 TPRICTRL ADC trigger priority control 0 1 read-write TPRICTRL_0 If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. 0 TPRICTRL_1 If a higher priority trigger is received during command processing, the current conversion is completed (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true conversion. 0x1 VREF1RNG Enable support for low voltage reference on Option 1 Reference 29 1 read-write VREF1RNG_0 Configuration required when Voltage Reference Option 1 input is in high voltage range 0 VREF1RNG_1 Configuration required when Voltage Reference Option 1 input is in low voltage range 0x1 CMDH1 ADC Command High Buffer Register 0x104 32 read-write n 0x0 0x0 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 CMPEN Compare Function Enable 0 2 read-write CMPEN_0 Compare disabled. 0 CMPEN_2 Compare enabled. Store on true. 0x2 CMPEN_3 Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. 0x3 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF STS Sample Time Select 8 3 read-write STS_0 no description available 0 STS_1 no description available 0x1 STS_2 no description available 0x2 STS_3 no description available 0x3 STS_4 no description available 0x4 STS_5 no description available 0x5 STS_6 no description available 0x6 STS_7 no description available 0x7 CMDH10 ADC Command High Buffer Register 0x14C 32 read-write n 0x0 0x0 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF STS Sample Time Select 8 3 read-write STS_0 no description available 0 STS_1 no description available 0x1 STS_2 no description available 0x2 STS_3 no description available 0x3 STS_4 no description available 0x4 STS_5 no description available 0x5 STS_6 no description available 0x6 STS_7 no description available 0x7 CMDH11 ADC Command High Buffer Register 0x154 32 read-write n 0x0 0x0 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF STS Sample Time Select 8 3 read-write STS_0 no description available 0 STS_1 no description available 0x1 STS_2 no description available 0x2 STS_3 no description available 0x3 STS_4 no description available 0x4 STS_5 no description available 0x5 STS_6 no description available 0x6 STS_7 no description available 0x7 CMDH12 ADC Command High Buffer Register 0x15C 32 read-write n 0x0 0x0 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF STS Sample Time Select 8 3 read-write STS_0 no description available 0 STS_1 no description available 0x1 STS_2 no description available 0x2 STS_3 no description available 0x3 STS_4 no description available 0x4 STS_5 no description available 0x5 STS_6 no description available 0x6 STS_7 no description available 0x7 CMDH13 ADC Command High Buffer Register 0x164 32 read-write n 0x0 0x0 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF STS Sample Time Select 8 3 read-write STS_0 no description available 0 STS_1 no description available 0x1 STS_2 no description available 0x2 STS_3 no description available 0x3 STS_4 no description available 0x4 STS_5 no description available 0x5 STS_6 no description available 0x6 STS_7 no description available 0x7 CMDH14 ADC Command High Buffer Register 0x16C 32 read-write n 0x0 0x0 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF STS Sample Time Select 8 3 read-write STS_0 no description available 0 STS_1 no description available 0x1 STS_2 no description available 0x2 STS_3 no description available 0x3 STS_4 no description available 0x4 STS_5 no description available 0x5 STS_6 no description available 0x6 STS_7 no description available 0x7 CMDH15 ADC Command High Buffer Register 0x174 32 read-write n 0x0 0x0 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF STS Sample Time Select 8 3 read-write STS_0 no description available 0 STS_1 no description available 0x1 STS_2 no description available 0x2 STS_3 no description available 0x3 STS_4 no description available 0x4 STS_5 no description available 0x5 STS_6 no description available 0x6 STS_7 no description available 0x7 CMDH2 ADC Command High Buffer Register 0x10C 32 read-write n 0x0 0x0 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 CMPEN Compare Function Enable 0 2 read-write CMPEN_0 Compare disabled. 0 CMPEN_2 Compare enabled. Store on true. 0x2 CMPEN_3 Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. 0x3 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF STS Sample Time Select 8 3 read-write STS_0 no description available 0 STS_1 no description available 0x1 STS_2 no description available 0x2 STS_3 no description available 0x3 STS_4 no description available 0x4 STS_5 no description available 0x5 STS_6 no description available 0x6 STS_7 no description available 0x7 CMDH3 ADC Command High Buffer Register 0x114 32 read-write n 0x0 0x0 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 CMPEN Compare Function Enable 0 2 read-write CMPEN_0 Compare disabled. 0 CMPEN_2 Compare enabled. Store on true. 0x2 CMPEN_3 Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. 0x3 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF STS Sample Time Select 8 3 read-write STS_0 no description available 0 STS_1 no description available 0x1 STS_2 no description available 0x2 STS_3 no description available 0x3 STS_4 no description available 0x4 STS_5 no description available 0x5 STS_6 no description available 0x6 STS_7 no description available 0x7 CMDH4 ADC Command High Buffer Register 0x11C 32 read-write n 0x0 0x0 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 CMPEN Compare Function Enable 0 2 read-write CMPEN_0 Compare disabled. 0 CMPEN_2 Compare enabled. Store on true. 0x2 CMPEN_3 Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. 0x3 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF STS Sample Time Select 8 3 read-write STS_0 no description available 0 STS_1 no description available 0x1 STS_2 no description available 0x2 STS_3 no description available 0x3 STS_4 no description available 0x4 STS_5 no description available 0x5 STS_6 no description available 0x6 STS_7 no description available 0x7 CMDH5 ADC Command High Buffer Register 0x124 32 read-write n 0x0 0x0 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF STS Sample Time Select 8 3 read-write STS_0 no description available 0 STS_1 no description available 0x1 STS_2 no description available 0x2 STS_3 no description available 0x3 STS_4 no description available 0x4 STS_5 no description available 0x5 STS_6 no description available 0x6 STS_7 no description available 0x7 CMDH6 ADC Command High Buffer Register 0x12C 32 read-write n 0x0 0x0 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF STS Sample Time Select 8 3 read-write STS_0 no description available 0 STS_1 no description available 0x1 STS_2 no description available 0x2 STS_3 no description available 0x3 STS_4 no description available 0x4 STS_5 no description available 0x5 STS_6 no description available 0x6 STS_7 no description available 0x7 CMDH7 ADC Command High Buffer Register 0x134 32 read-write n 0x0 0x0 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF STS Sample Time Select 8 3 read-write STS_0 no description available 0 STS_1 no description available 0x1 STS_2 no description available 0x2 STS_3 no description available 0x3 STS_4 no description available 0x4 STS_5 no description available 0x5 STS_6 no description available 0x6 STS_7 no description available 0x7 CMDH8 ADC Command High Buffer Register 0x13C 32 read-write n 0x0 0x0 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF STS Sample Time Select 8 3 read-write STS_0 no description available 0 STS_1 no description available 0x1 STS_2 no description available 0x2 STS_3 no description available 0x3 STS_4 no description available 0x4 STS_5 no description available 0x5 STS_6 no description available 0x6 STS_7 no description available 0x7 CMDH9 ADC Command High Buffer Register 0x144 32 read-write n 0x0 0x0 AVGS Hardware Average Select 12 3 read-write AVGS_0 Single conversion. 0 AVGS_1 2 conversions averaged. 0x1 AVGS_2 4 conversions averaged. 0x2 AVGS_3 8 conversions averaged. 0x3 AVGS_4 16 conversions averaged. 0x4 AVGS_5 32 conversions averaged. 0x5 AVGS_6 64 conversions averaged. 0x6 AVGS_7 128 conversions averaged. 0x7 LOOP Loop Count Select 16 4 read-write LOOP_0 Looping not enabled. Command executes 1 time. 0 LOOP_1 Loop 1 time. Command executes 2 times. 0x1 LOOP_2 Loop 2 times. Command executes 3 times. 0x2 LOOP_3 Loop corresponding number of times. Command executes LOOP+1 times. 0x3 LOOP_4 Loop corresponding number of times. Command executes LOOP+1 times. 0x4 LOOP_5 Loop corresponding number of times. Command executes LOOP+1 times. 0x5 LOOP_6 Loop corresponding number of times. Command executes LOOP+1 times. 0x6 LOOP_7 Loop corresponding number of times. Command executes LOOP+1 times. 0x7 LOOP_8 Loop corresponding number of times. Command executes LOOP+1 times. 0x8 LOOP_9 Loop corresponding number of times. Command executes LOOP+1 times. 0x9 LOOP_15 Loop 15 times. Command executes 16 times. 0xF LWI Loop with Increment 7 1 read-write LWI_0 Auto channel increment disabled 0 LWI_1 Auto channel increment enabled 0x1 NEXT Next Command Select 24 4 read-write NEXT_0 No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. 0 NEXT_1 Select CMD1 command buffer register as next command. 0x1 NEXT_2 Select corresponding CMD command buffer register as next command 0x2 NEXT_3 Select corresponding CMD command buffer register as next command 0x3 NEXT_4 Select corresponding CMD command buffer register as next command 0x4 NEXT_5 Select corresponding CMD command buffer register as next command 0x5 NEXT_6 Select corresponding CMD command buffer register as next command 0x6 NEXT_7 Select corresponding CMD command buffer register as next command 0x7 NEXT_8 Select corresponding CMD command buffer register as next command 0x8 NEXT_9 Select corresponding CMD command buffer register as next command 0x9 NEXT_15 Select CMD15 command buffer register as next command. 0xF STS Sample Time Select 8 3 read-write STS_0 no description available 0 STS_1 no description available 0x1 STS_2 no description available 0x2 STS_3 no description available 0x3 STS_4 no description available 0x4 STS_5 no description available 0x5 STS_6 no description available 0x6 STS_7 no description available 0x7 CMDL1 ADC Command Low Buffer Register 0x100 32 read-write n 0x0 0x0 ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 The associated A-side channel is converted. 0 ABSEL_1 The associated B-side channel is converted. 0x1 ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B 0 ADCH_1 Select CH1A or CH1B 0x1 ADCH_30 Select CH30A or CH30B 0x1E ADCH_31 Select CH31A or CH31B 0x1F ADCH_2 Select CH2A or CH2B 0x2 ADCH_3 Select CH3A or CH3B 0x3 ADCH_4 Select corresponding channel CHnA or CHnB 0x4 ADCH_5 Select corresponding channel CHnA or CHnB 0x5 ADCH_6 Select corresponding channel CHnA or CHnB 0x6 ADCH_7 Select corresponding channel CHnA or CHnB 0x7 ADCH_8 Select corresponding channel CHnA or CHnB 0x8 ADCH_9 Select corresponding channel CHnA or CHnB 0x9 CMDL10 ADC Command Low Buffer Register 0x148 32 read-write n 0x0 0x0 ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 The associated A-side channel is converted. 0 ABSEL_1 The associated B-side channel is converted. 0x1 ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B 0 ADCH_1 Select CH1A or CH1B 0x1 ADCH_30 Select CH30A or CH30B 0x1E ADCH_31 Select CH31A or CH31B 0x1F ADCH_2 Select CH2A or CH2B 0x2 ADCH_3 Select CH3A or CH3B 0x3 ADCH_4 Select corresponding channel CHnA or CHnB 0x4 ADCH_5 Select corresponding channel CHnA or CHnB 0x5 ADCH_6 Select corresponding channel CHnA or CHnB 0x6 ADCH_7 Select corresponding channel CHnA or CHnB 0x7 ADCH_8 Select corresponding channel CHnA or CHnB 0x8 ADCH_9 Select corresponding channel CHnA or CHnB 0x9 CMDL11 ADC Command Low Buffer Register 0x150 32 read-write n 0x0 0x0 ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 The associated A-side channel is converted. 0 ABSEL_1 The associated B-side channel is converted. 0x1 ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B 0 ADCH_1 Select CH1A or CH1B 0x1 ADCH_30 Select CH30A or CH30B 0x1E ADCH_31 Select CH31A or CH31B 0x1F ADCH_2 Select CH2A or CH2B 0x2 ADCH_3 Select CH3A or CH3B 0x3 ADCH_4 Select corresponding channel CHnA or CHnB 0x4 ADCH_5 Select corresponding channel CHnA or CHnB 0x5 ADCH_6 Select corresponding channel CHnA or CHnB 0x6 ADCH_7 Select corresponding channel CHnA or CHnB 0x7 ADCH_8 Select corresponding channel CHnA or CHnB 0x8 ADCH_9 Select corresponding channel CHnA or CHnB 0x9 CMDL12 ADC Command Low Buffer Register 0x158 32 read-write n 0x0 0x0 ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 The associated A-side channel is converted. 0 ABSEL_1 The associated B-side channel is converted. 0x1 ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B 0 ADCH_1 Select CH1A or CH1B 0x1 ADCH_30 Select CH30A or CH30B 0x1E ADCH_31 Select CH31A or CH31B 0x1F ADCH_2 Select CH2A or CH2B 0x2 ADCH_3 Select CH3A or CH3B 0x3 ADCH_4 Select corresponding channel CHnA or CHnB 0x4 ADCH_5 Select corresponding channel CHnA or CHnB 0x5 ADCH_6 Select corresponding channel CHnA or CHnB 0x6 ADCH_7 Select corresponding channel CHnA or CHnB 0x7 ADCH_8 Select corresponding channel CHnA or CHnB 0x8 ADCH_9 Select corresponding channel CHnA or CHnB 0x9 CMDL13 ADC Command Low Buffer Register 0x160 32 read-write n 0x0 0x0 ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 The associated A-side channel is converted. 0 ABSEL_1 The associated B-side channel is converted. 0x1 ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B 0 ADCH_1 Select CH1A or CH1B 0x1 ADCH_30 Select CH30A or CH30B 0x1E ADCH_31 Select CH31A or CH31B 0x1F ADCH_2 Select CH2A or CH2B 0x2 ADCH_3 Select CH3A or CH3B 0x3 ADCH_4 Select corresponding channel CHnA or CHnB 0x4 ADCH_5 Select corresponding channel CHnA or CHnB 0x5 ADCH_6 Select corresponding channel CHnA or CHnB 0x6 ADCH_7 Select corresponding channel CHnA or CHnB 0x7 ADCH_8 Select corresponding channel CHnA or CHnB 0x8 ADCH_9 Select corresponding channel CHnA or CHnB 0x9 CMDL14 ADC Command Low Buffer Register 0x168 32 read-write n 0x0 0x0 ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 The associated A-side channel is converted. 0 ABSEL_1 The associated B-side channel is converted. 0x1 ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B 0 ADCH_1 Select CH1A or CH1B 0x1 ADCH_30 Select CH30A or CH30B 0x1E ADCH_31 Select CH31A or CH31B 0x1F ADCH_2 Select CH2A or CH2B 0x2 ADCH_3 Select CH3A or CH3B 0x3 ADCH_4 Select corresponding channel CHnA or CHnB 0x4 ADCH_5 Select corresponding channel CHnA or CHnB 0x5 ADCH_6 Select corresponding channel CHnA or CHnB 0x6 ADCH_7 Select corresponding channel CHnA or CHnB 0x7 ADCH_8 Select corresponding channel CHnA or CHnB 0x8 ADCH_9 Select corresponding channel CHnA or CHnB 0x9 CMDL15 ADC Command Low Buffer Register 0x170 32 read-write n 0x0 0x0 ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 The associated A-side channel is converted. 0 ABSEL_1 The associated B-side channel is converted. 0x1 ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B 0 ADCH_1 Select CH1A or CH1B 0x1 ADCH_30 Select CH30A or CH30B 0x1E ADCH_31 Select CH31A or CH31B 0x1F ADCH_2 Select CH2A or CH2B 0x2 ADCH_3 Select CH3A or CH3B 0x3 ADCH_4 Select corresponding channel CHnA or CHnB 0x4 ADCH_5 Select corresponding channel CHnA or CHnB 0x5 ADCH_6 Select corresponding channel CHnA or CHnB 0x6 ADCH_7 Select corresponding channel CHnA or CHnB 0x7 ADCH_8 Select corresponding channel CHnA or CHnB 0x8 ADCH_9 Select corresponding channel CHnA or CHnB 0x9 CMDL2 ADC Command Low Buffer Register 0x108 32 read-write n 0x0 0x0 ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 The associated A-side channel is converted. 0 ABSEL_1 The associated B-side channel is converted. 0x1 ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B 0 ADCH_1 Select CH1A or CH1B 0x1 ADCH_30 Select CH30A or CH30B 0x1E ADCH_31 Select CH31A or CH31B 0x1F ADCH_2 Select CH2A or CH2B 0x2 ADCH_3 Select CH3A or CH3B 0x3 ADCH_4 Select corresponding channel CHnA or CHnB 0x4 ADCH_5 Select corresponding channel CHnA or CHnB 0x5 ADCH_6 Select corresponding channel CHnA or CHnB 0x6 ADCH_7 Select corresponding channel CHnA or CHnB 0x7 ADCH_8 Select corresponding channel CHnA or CHnB 0x8 ADCH_9 Select corresponding channel CHnA or CHnB 0x9 CMDL3 ADC Command Low Buffer Register 0x110 32 read-write n 0x0 0x0 ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 The associated A-side channel is converted. 0 ABSEL_1 The associated B-side channel is converted. 0x1 ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B 0 ADCH_1 Select CH1A or CH1B 0x1 ADCH_30 Select CH30A or CH30B 0x1E ADCH_31 Select CH31A or CH31B 0x1F ADCH_2 Select CH2A or CH2B 0x2 ADCH_3 Select CH3A or CH3B 0x3 ADCH_4 Select corresponding channel CHnA or CHnB 0x4 ADCH_5 Select corresponding channel CHnA or CHnB 0x5 ADCH_6 Select corresponding channel CHnA or CHnB 0x6 ADCH_7 Select corresponding channel CHnA or CHnB 0x7 ADCH_8 Select corresponding channel CHnA or CHnB 0x8 ADCH_9 Select corresponding channel CHnA or CHnB 0x9 CMDL4 ADC Command Low Buffer Register 0x118 32 read-write n 0x0 0x0 ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 The associated A-side channel is converted. 0 ABSEL_1 The associated B-side channel is converted. 0x1 ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B 0 ADCH_1 Select CH1A or CH1B 0x1 ADCH_30 Select CH30A or CH30B 0x1E ADCH_31 Select CH31A or CH31B 0x1F ADCH_2 Select CH2A or CH2B 0x2 ADCH_3 Select CH3A or CH3B 0x3 ADCH_4 Select corresponding channel CHnA or CHnB 0x4 ADCH_5 Select corresponding channel CHnA or CHnB 0x5 ADCH_6 Select corresponding channel CHnA or CHnB 0x6 ADCH_7 Select corresponding channel CHnA or CHnB 0x7 ADCH_8 Select corresponding channel CHnA or CHnB 0x8 ADCH_9 Select corresponding channel CHnA or CHnB 0x9 CMDL5 ADC Command Low Buffer Register 0x120 32 read-write n 0x0 0x0 ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 The associated A-side channel is converted. 0 ABSEL_1 The associated B-side channel is converted. 0x1 ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B 0 ADCH_1 Select CH1A or CH1B 0x1 ADCH_30 Select CH30A or CH30B 0x1E ADCH_31 Select CH31A or CH31B 0x1F ADCH_2 Select CH2A or CH2B 0x2 ADCH_3 Select CH3A or CH3B 0x3 ADCH_4 Select corresponding channel CHnA or CHnB 0x4 ADCH_5 Select corresponding channel CHnA or CHnB 0x5 ADCH_6 Select corresponding channel CHnA or CHnB 0x6 ADCH_7 Select corresponding channel CHnA or CHnB 0x7 ADCH_8 Select corresponding channel CHnA or CHnB 0x8 ADCH_9 Select corresponding channel CHnA or CHnB 0x9 CMDL6 ADC Command Low Buffer Register 0x128 32 read-write n 0x0 0x0 ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 The associated A-side channel is converted. 0 ABSEL_1 The associated B-side channel is converted. 0x1 ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B 0 ADCH_1 Select CH1A or CH1B 0x1 ADCH_30 Select CH30A or CH30B 0x1E ADCH_31 Select CH31A or CH31B 0x1F ADCH_2 Select CH2A or CH2B 0x2 ADCH_3 Select CH3A or CH3B 0x3 ADCH_4 Select corresponding channel CHnA or CHnB 0x4 ADCH_5 Select corresponding channel CHnA or CHnB 0x5 ADCH_6 Select corresponding channel CHnA or CHnB 0x6 ADCH_7 Select corresponding channel CHnA or CHnB 0x7 ADCH_8 Select corresponding channel CHnA or CHnB 0x8 ADCH_9 Select corresponding channel CHnA or CHnB 0x9 CMDL7 ADC Command Low Buffer Register 0x130 32 read-write n 0x0 0x0 ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 The associated A-side channel is converted. 0 ABSEL_1 The associated B-side channel is converted. 0x1 ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B 0 ADCH_1 Select CH1A or CH1B 0x1 ADCH_30 Select CH30A or CH30B 0x1E ADCH_31 Select CH31A or CH31B 0x1F ADCH_2 Select CH2A or CH2B 0x2 ADCH_3 Select CH3A or CH3B 0x3 ADCH_4 Select corresponding channel CHnA or CHnB 0x4 ADCH_5 Select corresponding channel CHnA or CHnB 0x5 ADCH_6 Select corresponding channel CHnA or CHnB 0x6 ADCH_7 Select corresponding channel CHnA or CHnB 0x7 ADCH_8 Select corresponding channel CHnA or CHnB 0x8 ADCH_9 Select corresponding channel CHnA or CHnB 0x9 CMDL8 ADC Command Low Buffer Register 0x138 32 read-write n 0x0 0x0 ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 The associated A-side channel is converted. 0 ABSEL_1 The associated B-side channel is converted. 0x1 ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B 0 ADCH_1 Select CH1A or CH1B 0x1 ADCH_30 Select CH30A or CH30B 0x1E ADCH_31 Select CH31A or CH31B 0x1F ADCH_2 Select CH2A or CH2B 0x2 ADCH_3 Select CH3A or CH3B 0x3 ADCH_4 Select corresponding channel CHnA or CHnB 0x4 ADCH_5 Select corresponding channel CHnA or CHnB 0x5 ADCH_6 Select corresponding channel CHnA or CHnB 0x6 ADCH_7 Select corresponding channel CHnA or CHnB 0x7 ADCH_8 Select corresponding channel CHnA or CHnB 0x8 ADCH_9 Select corresponding channel CHnA or CHnB 0x9 CMDL9 ADC Command Low Buffer Register 0x140 32 read-write n 0x0 0x0 ABSEL A-side vs. B-side Select 5 1 read-write ABSEL_0 The associated A-side channel is converted. 0 ABSEL_1 The associated B-side channel is converted. 0x1 ADCH Input channel select 0 5 read-write ADCH_0 Select CH0A or CH0B 0 ADCH_1 Select CH1A or CH1B 0x1 ADCH_30 Select CH30A or CH30B 0x1E ADCH_31 Select CH31A or CH31B 0x1F ADCH_2 Select CH2A or CH2B 0x2 ADCH_3 Select CH3A or CH3B 0x3 ADCH_4 Select corresponding channel CHnA or CHnB 0x4 ADCH_5 Select corresponding channel CHnA or CHnB 0x5 ADCH_6 Select corresponding channel CHnA or CHnB 0x6 ADCH_7 Select corresponding channel CHnA or CHnB 0x7 ADCH_8 Select corresponding channel CHnA or CHnB 0x8 ADCH_9 Select corresponding channel CHnA or CHnB 0x9 CTRL ADC Control Register 0x10 32 read-write n 0x0 0x0 ADCEN ADC Enable 0 1 read-write ADCEN_0 ADC is disabled. 0 ADCEN_1 ADC is enabled. 0x1 DOZEN Doze Enable 2 1 read-write DOZEN_0 ADC is enabled in Doze mode. 0 DOZEN_1 ADC is disabled in Doze mode. 0x1 RST Software Reset 1 1 read-write RST_0 ADC logic is not reset. 0 RST_1 ADC logic is reset. 0x1 RSTFIFO Reset FIFO 8 1 write-only RSTFIFO_0 No effect. 0 RSTFIFO_1 FIFO is reset. 0x1 CV1 Compare Value Register 0x200 32 read-write n 0x0 0x0 CVH Compare Value High. 16 16 read-write CVL Compare Value Low. 0 16 read-write CV2 Compare Value Register 0x204 32 read-write n 0x0 0x0 CVH Compare Value High. 16 16 read-write CVL Compare Value Low. 0 16 read-write CV3 Compare Value Register 0x208 32 read-write n 0x0 0x0 CVH Compare Value High. 16 16 read-write CVL Compare Value Low. 0 16 read-write CV4 Compare Value Register 0x20C 32 read-write n 0x0 0x0 CVH Compare Value High. 16 16 read-write CVL Compare Value Low. 0 16 read-write DE DMA Enable Register 0x1C 32 read-write n 0x0 0x0 FWMDE FIFO Watermark DMA Enable 0 1 read-write FWMDE_0 DMA request disabled. 0 FWMDE_1 DMA request enabled. 0x1 FCTRL ADC FIFO Control Register 0x30 32 read-write n 0x0 0x0 FCOUNT Result FIFO counter 0 5 read-only FWMARK Watermark level selection 16 4 read-write IE Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 FOFIE Result FIFO Overflow Interrupt Enable 1 1 read-write FOFIE_0 FIFO overflow interrupts are not enabled. 0 FOFIE_1 FIFO overflow interrupts are enabled. 0x1 FWMIE FIFO Watermark Interrupt Enable 0 1 read-write FWMIE_0 FIFO watermark interrupts are not enabled. 0 FWMIE_1 FIFO watermark interrupts are enabled. 0x1 OFSTRIM ADC Offset Trim Register 0x40 32 read-write n 0x0 0x0 OFSTRIM Trim for offset 0 6 read-write PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 CMD_NUM Command Buffer Number 24 8 read-only CV_NUM Compare Value Number 16 8 read-only FIFOSIZE Result FIFO Depth 8 8 read-only FIFOSIZE_1 Result FIFO depth = 1 dataword. 0x1 FIFOSIZE_16 Result FIFO depth = 16 datawords. 0x10 FIFOSIZE_32 Result FIFO depth = 32 datawords. 0x20 FIFOSIZE_4 Result FIFO depth = 4 datawords. 0x4 FIFOSIZE_64 Result FIFO depth = 64 datawords. 0x40 FIFOSIZE_8 Result FIFO depth = 8 datawords. 0x8 TRIG_NUM Trigger Number 0 8 read-only PAUSE ADC Pause Register 0x24 32 read-write n 0x0 0x0 PAUSEDLY Pause Delay 0 9 read-write PAUSEEN PAUSE Option Enable 31 1 read-write PAUSEEN_0 Pause operation disabled 0 PAUSEEN_1 Pause operation enabled 0x1 RESFIFO ADC Data Result FIFO Register 0x300 32 read-only n 0x0 0x0 CMDSRC Command Buffer Source 24 4 read-only CMDSRC_0 Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. 0 CMDSRC_1 CMD1 buffer used as control settings for this conversion. 0x1 CMDSRC_2 Corresponding command buffer used as control settings for this conversion. 0x2 CMDSRC_3 Corresponding command buffer used as control settings for this conversion. 0x3 CMDSRC_4 Corresponding command buffer used as control settings for this conversion. 0x4 CMDSRC_5 Corresponding command buffer used as control settings for this conversion. 0x5 CMDSRC_6 Corresponding command buffer used as control settings for this conversion. 0x6 CMDSRC_7 Corresponding command buffer used as control settings for this conversion. 0x7 CMDSRC_8 Corresponding command buffer used as control settings for this conversion. 0x8 CMDSRC_9 Corresponding command buffer used as control settings for this conversion. 0x9 CMDSRC_15 CMD15 buffer used as control settings for this conversion. 0xF D Data result 0 16 read-only LOOPCNT Loop count value 20 4 read-only LOOPCNT_0 Result is from initial conversion in command. 0 LOOPCNT_1 Result is from second conversion in command. 0x1 LOOPCNT_2 no description available 0x2 LOOPCNT_3 no description available 0x3 LOOPCNT_4 no description available 0x4 LOOPCNT_5 no description available 0x5 LOOPCNT_6 no description available 0x6 LOOPCNT_7 no description available 0x7 LOOPCNT_8 no description available 0x8 LOOPCNT_9 no description available 0x9 LOOPCNT_15 no description available 0xF TSRC Trigger Source 16 2 read-only TSRC_0 Trigger source 0 initiated this conversion. 0 TSRC_1 Trigger source 1 initiated this conversion. 0x1 TSRC_2 Trigger source 2 initiated this conversion. 0x2 TSRC_3 Trigger source 3 initiated this conversion. 0x3 VALID FIFO entry is valid 31 1 read-only VALID_0 FIFO is empty. Discard any read from RESFIFO. 0 VALID_1 FIFO record read from RESFIFO is valid. 0x1 STAT ADC Status Register 0x14 32 read-write n 0x0 0x0 CMDACT Command Active 24 4 read-only CMDACT_0 No command is currently in progress. 0 CMDACT_1 Command 1 currently being executed. 0x1 CMDACT_2 Command 2 currently being executed. 0x2 CMDACT_3 Associated command number is currently being executed. 0x3 CMDACT_4 Associated command number is currently being executed. 0x4 CMDACT_5 Associated command number is currently being executed. 0x5 CMDACT_6 Associated command number is currently being executed. 0x6 CMDACT_7 Associated command number is currently being executed. 0x7 CMDACT_8 Associated command number is currently being executed. 0x8 CMDACT_9 Associated command number is currently being executed. 0x9 FOF Result FIFO Overflow Flag 1 1 read-write oneToClear FOF_0 No result FIFO overflow has occurred since the last time the flag was cleared. 0 FOF_1 At least one result FIFO overflow has occurred since the last time the flag was cleared. 0x1 RDY Result FIFO Ready Flag 0 1 read-only RDY_0 Result FIFO data level not above watermark level. 0 RDY_1 Result FIFO holding data above watermark level. 0x1 TRGACT Trigger Active 16 2 read-only TRGACT_0 Command (sequence) associated with Trigger 0 currently being executed. 0 TRGACT_1 Command (sequence) associated with Trigger 1 currently being executed. 0x1 TRGACT_2 Command (sequence) associated with Trigger 2 currently being executed. 0x2 TRGACT_3 Command (sequence) associated with Trigger 3 currently being executed. 0x3 SWTRIG Software Trigger Register 0x34 32 read-write n 0x0 0x0 SWT0 Software trigger 0 event 0 1 write-only SWT0_0 No trigger 0 event generated. 0 SWT0_1 Trigger 0 event generated. 0x1 SWT1 Software trigger 1 event 1 1 write-only SWT1_0 No trigger 1 event generated. 0 SWT1_1 Trigger 1 event generated. 0x1 SWT2 Software trigger 2 event 2 1 write-only SWT2_0 No trigger 2 event generated. 0 SWT2_1 Trigger 2 event generated. 0x1 SWT3 Software trigger 3 event 3 1 write-only SWT3_0 No trigger 3 event generated. 0 SWT3_1 Trigger 3 event generated. 0x1 TCTRL0 Trigger Control Register 0xC0 32 read-write n 0x0 0x0 HTEN Trigger enable 0 1 read-write HTEN_0 Hardware trigger source disabled 0 HTEN_1 Hardware trigger source enabled 0x1 TCMD Trigger command select 24 4 read-write TCMD_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 TCMD_1 CMD1 is executed 0x1 TCMD_2 Corresponding CMD is executed 0x2 TCMD_3 Corresponding CMD is executed 0x3 TCMD_4 Corresponding CMD is executed 0x4 TCMD_5 Corresponding CMD is executed 0x5 TCMD_6 Corresponding CMD is executed 0x6 TCMD_7 Corresponding CMD is executed 0x7 TCMD_8 Corresponding CMD is executed 0x8 TCMD_9 Corresponding CMD is executed 0x9 TCMD_15 CMD15 is executed 0xF TDLY Trigger delay select 16 4 read-write TPRI Trigger priority setting 8 2 read-write TPRI_0 Set to highest priority, Level 1 0 TPRI_1 Set to corresponding priority level 0x1 TPRI_2 Set to corresponding priority level 0x2 TPRI_3 Set to lowest priority, Level 4 0x3 TCTRL1 Trigger Control Register 0xC4 32 read-write n 0x0 0x0 HTEN Trigger enable 0 1 read-write HTEN_0 Hardware trigger source disabled 0 HTEN_1 Hardware trigger source enabled 0x1 TCMD Trigger command select 24 4 read-write TCMD_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 TCMD_1 CMD1 is executed 0x1 TCMD_2 Corresponding CMD is executed 0x2 TCMD_3 Corresponding CMD is executed 0x3 TCMD_4 Corresponding CMD is executed 0x4 TCMD_5 Corresponding CMD is executed 0x5 TCMD_6 Corresponding CMD is executed 0x6 TCMD_7 Corresponding CMD is executed 0x7 TCMD_8 Corresponding CMD is executed 0x8 TCMD_9 Corresponding CMD is executed 0x9 TCMD_15 CMD15 is executed 0xF TDLY Trigger delay select 16 4 read-write TPRI Trigger priority setting 8 2 read-write TPRI_0 Set to highest priority, Level 1 0 TPRI_1 Set to corresponding priority level 0x1 TPRI_2 Set to corresponding priority level 0x2 TPRI_3 Set to lowest priority, Level 4 0x3 TCTRL2 Trigger Control Register 0xC8 32 read-write n 0x0 0x0 HTEN Trigger enable 0 1 read-write HTEN_0 Hardware trigger source disabled 0 HTEN_1 Hardware trigger source enabled 0x1 TCMD Trigger command select 24 4 read-write TCMD_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 TCMD_1 CMD1 is executed 0x1 TCMD_2 Corresponding CMD is executed 0x2 TCMD_3 Corresponding CMD is executed 0x3 TCMD_4 Corresponding CMD is executed 0x4 TCMD_5 Corresponding CMD is executed 0x5 TCMD_6 Corresponding CMD is executed 0x6 TCMD_7 Corresponding CMD is executed 0x7 TCMD_8 Corresponding CMD is executed 0x8 TCMD_9 Corresponding CMD is executed 0x9 TCMD_15 CMD15 is executed 0xF TDLY Trigger delay select 16 4 read-write TPRI Trigger priority setting 8 2 read-write TPRI_0 Set to highest priority, Level 1 0 TPRI_1 Set to corresponding priority level 0x1 TPRI_2 Set to corresponding priority level 0x2 TPRI_3 Set to lowest priority, Level 4 0x3 TCTRL3 Trigger Control Register 0xCC 32 read-write n 0x0 0x0 HTEN Trigger enable 0 1 read-write HTEN_0 Hardware trigger source disabled 0 HTEN_1 Hardware trigger source enabled 0x1 TCMD Trigger command select 24 4 read-write TCMD_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 TCMD_1 CMD1 is executed 0x1 TCMD_2 Corresponding CMD is executed 0x2 TCMD_3 Corresponding CMD is executed 0x3 TCMD_4 Corresponding CMD is executed 0x4 TCMD_5 Corresponding CMD is executed 0x5 TCMD_6 Corresponding CMD is executed 0x6 TCMD_7 Corresponding CMD is executed 0x7 TCMD_8 Corresponding CMD is executed 0x8 TCMD_9 Corresponding CMD is executed 0x9 TCMD_15 CMD15 is executed 0xF TDLY Trigger delay select 16 4 read-write TPRI Trigger priority setting 8 2 read-write TPRI_0 Set to highest priority, Level 1 0 TPRI_1 Set to corresponding priority level 0x1 TPRI_2 Set to corresponding priority level 0x2 TPRI_3 Set to lowest priority, Level 4 0x3 TCTRL[0] Trigger Control Register 0x180 32 read-write n 0x0 0x0 HTEN Trigger enable 0 1 read-write HTEN_0 Hardware trigger source disabled 0 HTEN_1 Hardware trigger source enabled 0x1 TCMD Trigger command select 24 4 read-write TCMD_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 TCMD_1 CMD1 is executed 0x1 TCMD_2 Corresponding CMD is executed 0x2 TCMD_3 Corresponding CMD is executed 0x3 TCMD_4 Corresponding CMD is executed 0x4 TCMD_5 Corresponding CMD is executed 0x5 TCMD_6 Corresponding CMD is executed 0x6 TCMD_7 Corresponding CMD is executed 0x7 TCMD_8 Corresponding CMD is executed 0x8 TCMD_9 Corresponding CMD is executed 0x9 TCMD_15 CMD15 is executed 0xF TDLY Trigger delay select 16 4 read-write TPRI Trigger priority setting 8 2 read-write TPRI_0 Set to highest priority, Level 1 0 TPRI_1 Set to corresponding priority level 0x1 TPRI_2 Set to corresponding priority level 0x2 TPRI_3 Set to lowest priority, Level 4 0x3 TCTRL[1] Trigger Control Register 0x244 32 read-write n 0x0 0x0 HTEN Trigger enable 0 1 read-write HTEN_0 Hardware trigger source disabled 0 HTEN_1 Hardware trigger source enabled 0x1 TCMD Trigger command select 24 4 read-write TCMD_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 TCMD_1 CMD1 is executed 0x1 TCMD_2 Corresponding CMD is executed 0x2 TCMD_3 Corresponding CMD is executed 0x3 TCMD_4 Corresponding CMD is executed 0x4 TCMD_5 Corresponding CMD is executed 0x5 TCMD_6 Corresponding CMD is executed 0x6 TCMD_7 Corresponding CMD is executed 0x7 TCMD_8 Corresponding CMD is executed 0x8 TCMD_9 Corresponding CMD is executed 0x9 TCMD_15 CMD15 is executed 0xF TDLY Trigger delay select 16 4 read-write TPRI Trigger priority setting 8 2 read-write TPRI_0 Set to highest priority, Level 1 0 TPRI_1 Set to corresponding priority level 0x1 TPRI_2 Set to corresponding priority level 0x2 TPRI_3 Set to lowest priority, Level 4 0x3 TCTRL[2] Trigger Control Register 0x30C 32 read-write n 0x0 0x0 HTEN Trigger enable 0 1 read-write HTEN_0 Hardware trigger source disabled 0 HTEN_1 Hardware trigger source enabled 0x1 TCMD Trigger command select 24 4 read-write TCMD_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 TCMD_1 CMD1 is executed 0x1 TCMD_2 Corresponding CMD is executed 0x2 TCMD_3 Corresponding CMD is executed 0x3 TCMD_4 Corresponding CMD is executed 0x4 TCMD_5 Corresponding CMD is executed 0x5 TCMD_6 Corresponding CMD is executed 0x6 TCMD_7 Corresponding CMD is executed 0x7 TCMD_8 Corresponding CMD is executed 0x8 TCMD_9 Corresponding CMD is executed 0x9 TCMD_15 CMD15 is executed 0xF TDLY Trigger delay select 16 4 read-write TPRI Trigger priority setting 8 2 read-write TPRI_0 Set to highest priority, Level 1 0 TPRI_1 Set to corresponding priority level 0x1 TPRI_2 Set to corresponding priority level 0x2 TPRI_3 Set to lowest priority, Level 4 0x3 TCTRL[3] Trigger Control Register 0x3D8 32 read-write n 0x0 0x0 HTEN Trigger enable 0 1 read-write HTEN_0 Hardware trigger source disabled 0 HTEN_1 Hardware trigger source enabled 0x1 TCMD Trigger command select 24 4 read-write TCMD_0 Not a valid selection from the command buffer. Trigger event is ignored. 0 TCMD_1 CMD1 is executed 0x1 TCMD_2 Corresponding CMD is executed 0x2 TCMD_3 Corresponding CMD is executed 0x3 TCMD_4 Corresponding CMD is executed 0x4 TCMD_5 Corresponding CMD is executed 0x5 TCMD_6 Corresponding CMD is executed 0x6 TCMD_7 Corresponding CMD is executed 0x7 TCMD_8 Corresponding CMD is executed 0x8 TCMD_9 Corresponding CMD is executed 0x9 TCMD_15 CMD15 is executed 0xF TDLY Trigger delay select 16 4 read-write TPRI Trigger priority setting 8 2 read-write TPRI_0 Set to highest priority, Level 1 0 TPRI_1 Set to corresponding priority level 0x1 TPRI_2 Set to corresponding priority level 0x2 TPRI_3 Set to lowest priority, Level 4 0x3 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 CALOFSI Calibration Offset Function Implemented 10 1 read-only CALOFSI_0 Offset calibration and offset trimming not implemented. 0 CALOFSI_1 Offset calibration and offset trimming implemented. 0x1 CSW Channel Scale Width 4 3 read-only CSW_0 Channel scaling not supported. 0 CSW_1 Channel scaling supported. 1-bit CSCALE control field. 0x1 CSW_6 Channel scaling supported. 6-bit CSCALE control field. 0x6 DIFFEN Differential Supported 1 1 read-only DIFFEN_0 Differential operation not supported. 0 DIFFEN_1 Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented. 0x1 IADCKI Internal ADC Clock implemented 9 1 read-only IADCKI_0 Internal clock source not implemented. 0 IADCKI_1 Internal clock source (and CFG[ADCKEN]) implemented. 0x1 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only MVI Multi Vref Implemented 3 1 read-only MVI_0 Single voltage reference high (VREFH) input supported. 0 MVI_1 Multiple voltage reference high (VREFH) inputs supported. 0x1 RES Resolution 0 1 read-only RES_0 Up to 13-bit differential/12-bit single ended resolution supported. 0 RES_1 Up to 16-bit differential/15-bit single ended resolution supported. 0x1 VR1RNGI Voltage Reference 1 Range Control Bit Implemented 8 1 read-only VR1RNGI_0 Range control not required. CFG[VREF1RNG] is not implemented. 0 VR1RNGI_1 Range control required. CFG[VREF1RNG] is implemented. 0x1 AXBS0 AXBS AXBS 0x0 0x0 0xD04 registers n CRS0 Control Register 0x10 32 read-write n 0x0 0x0 ARB Arbitration Mode 8 2 read-write ARB_0 Fixed priority 0 ARB_1 Round-robin, or rotating, priority 0x1 HLP Halt Low Priority 30 1 read-write HLP_0 The low power mode request has the highest priority for arbitration on this slave port 0 HLP_1 The low power mode request has the lowest initial priority for arbitration on this slave port 0x1 PARK Park 0 3 read-write PARK_0 Park on master port M0 0 PARK_1 Park on master port M1 0x1 PARK_2 Park on master port M2 0x2 PARK_3 Park on master port M3 0x3 PARK_4 Park on master port M4 0x4 PARK_5 Park on master port M5 0x5 PARK_6 Park on master port M6 0x6 PARK_7 Park on master port M7 0x7 PCTL Parking Control 4 2 read-write PCTL_0 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field 0 PCTL_1 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port 0x1 PCTL_2 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state 0x2 RO Read Only 31 1 read-write RO_0 The slave port's registers are writeable 0 RO_1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. 0x1 CRS1 Control Register 0x110 32 read-write n 0x0 0x0 ARB Arbitration Mode 8 2 read-write ARB_0 Fixed priority 0 ARB_1 Round-robin, or rotating, priority 0x1 HLP Halt Low Priority 30 1 read-write HLP_0 The low power mode request has the highest priority for arbitration on this slave port 0 HLP_1 The low power mode request has the lowest initial priority for arbitration on this slave port 0x1 PARK Park 0 3 read-write PARK_0 Park on master port M0 0 PARK_1 Park on master port M1 0x1 PARK_2 Park on master port M2 0x2 PARK_3 Park on master port M3 0x3 PARK_4 Park on master port M4 0x4 PARK_5 Park on master port M5 0x5 PARK_6 Park on master port M6 0x6 PARK_7 Park on master port M7 0x7 PCTL Parking Control 4 2 read-write PCTL_0 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field 0 PCTL_1 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port 0x1 PCTL_2 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state 0x2 RO Read Only 31 1 read-write RO_0 The slave port's registers are writeable 0 RO_1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. 0x1 CRS2 Control Register 0x210 32 read-write n 0x0 0x0 ARB Arbitration Mode 8 2 read-write ARB_0 Fixed priority 0 ARB_1 Round-robin, or rotating, priority 0x1 HLP Halt Low Priority 30 1 read-write HLP_0 The low power mode request has the highest priority for arbitration on this slave port 0 HLP_1 The low power mode request has the lowest initial priority for arbitration on this slave port 0x1 PARK Park 0 3 read-write PARK_0 Park on master port M0 0 PARK_1 Park on master port M1 0x1 PARK_2 Park on master port M2 0x2 PARK_3 Park on master port M3 0x3 PARK_4 Park on master port M4 0x4 PARK_5 Park on master port M5 0x5 PARK_6 Park on master port M6 0x6 PARK_7 Park on master port M7 0x7 PCTL Parking Control 4 2 read-write PCTL_0 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field 0 PCTL_1 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port 0x1 PCTL_2 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state 0x2 RO Read Only 31 1 read-write RO_0 The slave port's registers are writeable 0 RO_1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. 0x1 CRS3 Control Register 0x310 32 read-write n 0x0 0x0 ARB Arbitration Mode 8 2 read-write ARB_0 Fixed priority 0 ARB_1 Round-robin, or rotating, priority 0x1 HLP Halt Low Priority 30 1 read-write HLP_0 The low power mode request has the highest priority for arbitration on this slave port 0 HLP_1 The low power mode request has the lowest initial priority for arbitration on this slave port 0x1 PARK Park 0 3 read-write PARK_0 Park on master port M0 0 PARK_1 Park on master port M1 0x1 PARK_2 Park on master port M2 0x2 PARK_3 Park on master port M3 0x3 PARK_4 Park on master port M4 0x4 PARK_5 Park on master port M5 0x5 PARK_6 Park on master port M6 0x6 PARK_7 Park on master port M7 0x7 PCTL Parking Control 4 2 read-write PCTL_0 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field 0 PCTL_1 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port 0x1 PCTL_2 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state 0x2 RO Read Only 31 1 read-write RO_0 The slave port's registers are writeable 0 RO_1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. 0x1 CRS4 Control Register 0x410 32 read-write n 0x0 0x0 ARB Arbitration Mode 8 2 read-write ARB_0 Fixed priority 0 ARB_1 Round-robin, or rotating, priority 0x1 HLP Halt Low Priority 30 1 read-write HLP_0 The low power mode request has the highest priority for arbitration on this slave port 0 HLP_1 The low power mode request has the lowest initial priority for arbitration on this slave port 0x1 PARK Park 0 3 read-write PARK_0 Park on master port M0 0 PARK_1 Park on master port M1 0x1 PARK_2 Park on master port M2 0x2 PARK_3 Park on master port M3 0x3 PARK_4 Park on master port M4 0x4 PARK_5 Park on master port M5 0x5 PARK_6 Park on master port M6 0x6 PARK_7 Park on master port M7 0x7 PCTL Parking Control 4 2 read-write PCTL_0 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field 0 PCTL_1 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port 0x1 PCTL_2 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state 0x2 RO Read Only 31 1 read-write RO_0 The slave port's registers are writeable 0 RO_1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. 0x1 MGPCR0 Master General Purpose Control Register 0x800 32 read-write n 0x0 0x0 AULB Arbitrates On Undefined Length Bursts 0 3 read-write AULB_0 No arbitration is allowed during an undefined length burst 0 AULB_1 Arbitration is allowed at any time during an undefined length burst 0x1 AULB_2 Arbitration is allowed after four beats of an undefined length burst 0x2 AULB_3 Arbitration is allowed after eight beats of an undefined length burst 0x3 AULB_4 Arbitration is allowed after 16 beats of an undefined length burst 0x4 MGPCR1 Master General Purpose Control Register 0x900 32 read-write n 0x0 0x0 AULB Arbitrates On Undefined Length Bursts 0 3 read-write AULB_0 No arbitration is allowed during an undefined length burst 0 AULB_1 Arbitration is allowed at any time during an undefined length burst 0x1 AULB_2 Arbitration is allowed after four beats of an undefined length burst 0x2 AULB_3 Arbitration is allowed after eight beats of an undefined length burst 0x3 AULB_4 Arbitration is allowed after 16 beats of an undefined length burst 0x4 MGPCR2 Master General Purpose Control Register 0xA00 32 read-write n 0x0 0x0 AULB Arbitrates On Undefined Length Bursts 0 3 read-write AULB_0 No arbitration is allowed during an undefined length burst 0 AULB_1 Arbitration is allowed at any time during an undefined length burst 0x1 AULB_2 Arbitration is allowed after four beats of an undefined length burst 0x2 AULB_3 Arbitration is allowed after eight beats of an undefined length burst 0x3 AULB_4 Arbitration is allowed after 16 beats of an undefined length burst 0x4 MGPCR3 Master General Purpose Control Register 0xB00 32 read-write n 0x0 0x0 AULB Arbitrates On Undefined Length Bursts 0 3 read-write AULB_0 No arbitration is allowed during an undefined length burst 0 AULB_1 Arbitration is allowed at any time during an undefined length burst 0x1 AULB_2 Arbitration is allowed after four beats of an undefined length burst 0x2 AULB_3 Arbitration is allowed after eight beats of an undefined length burst 0x3 AULB_4 Arbitration is allowed after 16 beats of an undefined length burst 0x4 MGPCR4 Master General Purpose Control Register 0xC00 32 read-write n 0x0 0x0 AULB Arbitrates On Undefined Length Bursts 0 3 read-write AULB_0 No arbitration is allowed during an undefined length burst 0 AULB_1 Arbitration is allowed at any time during an undefined length burst 0x1 AULB_2 Arbitration is allowed after four beats of an undefined length burst 0x2 AULB_3 Arbitration is allowed after eight beats of an undefined length burst 0x3 AULB_4 Arbitration is allowed after 16 beats of an undefined length burst 0x4 MGPCR5 Master General Purpose Control Register 0xD00 32 read-write n 0x0 0x0 AULB Arbitrates On Undefined Length Bursts 0 3 read-write AULB_0 No arbitration is allowed during an undefined length burst 0 AULB_1 Arbitration is allowed at any time during an undefined length burst 0x1 AULB_2 Arbitration is allowed after four beats of an undefined length burst 0x2 AULB_3 Arbitration is allowed after eight beats of an undefined length burst 0x3 AULB_4 Arbitration is allowed after 16 beats of an undefined length burst 0x4 PRS0 Priority Slave Registers 0x0 32 read-write n 0x0 0x0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write M0_0 This master has level 1, or highest, priority when accessing the slave port. 0 M0_1 This master has level 2 priority when accessing the slave port. 0x1 M0_2 This master has level 3 priority when accessing the slave port. 0x2 M0_3 This master has level 4 priority when accessing the slave port. 0x3 M0_4 This master has level 5 priority when accessing the slave port. 0x4 M0_5 This master has level 6 priority when accessing the slave port. 0x5 M0_6 This master has level 7 priority when accessing the slave port. 0x6 M0_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write M1_0 This master has level 1, or highest, priority when accessing the slave port. 0 M1_1 This master has level 2 priority when accessing the slave port. 0x1 M1_2 This master has level 3 priority when accessing the slave port. 0x2 M1_3 This master has level 4 priority when accessing the slave port. 0x3 M1_4 This master has level 5 priority when accessing the slave port. 0x4 M1_5 This master has level 6 priority when accessing the slave port. 0x5 M1_6 This master has level 7 priority when accessing the slave port. 0x6 M1_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write M2_0 This master has level 1, or highest, priority when accessing the slave port. 0 M2_1 This master has level 2 priority when accessing the slave port. 0x1 M2_2 This master has level 3 priority when accessing the slave port. 0x2 M2_3 This master has level 4 priority when accessing the slave port. 0x3 M2_4 This master has level 5 priority when accessing the slave port. 0x4 M2_5 This master has level 6 priority when accessing the slave port. 0x5 M2_6 This master has level 7 priority when accessing the slave port. 0x6 M2_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write M3_0 This master has level 1, or highest, priority when accessing the slave port. 0 M3_1 This master has level 2 priority when accessing the slave port. 0x1 M3_2 This master has level 3 priority when accessing the slave port. 0x2 M3_3 This master has level 4 priority when accessing the slave port. 0x3 M3_4 This master has level 5 priority when accessing the slave port. 0x4 M3_5 This master has level 6 priority when accessing the slave port. 0x5 M3_6 This master has level 7 priority when accessing the slave port. 0x6 M3_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M4 Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. 16 3 read-write M4_0 This master has level 1, or highest, priority when accessing the slave port. 0 M4_1 This master has level 2 priority when accessing the slave port. 0x1 M4_2 This master has level 3 priority when accessing the slave port. 0x2 M4_3 This master has level 4 priority when accessing the slave port. 0x3 M4_4 This master has level 5 priority when accessing the slave port. 0x4 M4_5 This master has level 6 priority when accessing the slave port. 0x5 M4_6 This master has level 7 priority when accessing the slave port. 0x6 M4_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M5 Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. 20 3 read-write M5_0 This master has level 1, or highest, priority when accessing the slave port. 0 M5_1 This master has level 2 priority when accessing the slave port. 0x1 M5_2 This master has level 3 priority when accessing the slave port. 0x2 M5_3 This master has level 4 priority when accessing the slave port. 0x3 M5_4 This master has level 5 priority when accessing the slave port. 0x4 M5_5 This master has level 6 priority when accessing the slave port. 0x5 M5_6 This master has level 7 priority when accessing the slave port. 0x6 M5_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 PRS1 Priority Slave Registers 0x100 32 read-write n 0x0 0x0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write M0_0 This master has level 1, or highest, priority when accessing the slave port. 0 M0_1 This master has level 2 priority when accessing the slave port. 0x1 M0_2 This master has level 3 priority when accessing the slave port. 0x2 M0_3 This master has level 4 priority when accessing the slave port. 0x3 M0_4 This master has level 5 priority when accessing the slave port. 0x4 M0_5 This master has level 6 priority when accessing the slave port. 0x5 M0_6 This master has level 7 priority when accessing the slave port. 0x6 M0_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write M1_0 This master has level 1, or highest, priority when accessing the slave port. 0 M1_1 This master has level 2 priority when accessing the slave port. 0x1 M1_2 This master has level 3 priority when accessing the slave port. 0x2 M1_3 This master has level 4 priority when accessing the slave port. 0x3 M1_4 This master has level 5 priority when accessing the slave port. 0x4 M1_5 This master has level 6 priority when accessing the slave port. 0x5 M1_6 This master has level 7 priority when accessing the slave port. 0x6 M1_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write M2_0 This master has level 1, or highest, priority when accessing the slave port. 0 M2_1 This master has level 2 priority when accessing the slave port. 0x1 M2_2 This master has level 3 priority when accessing the slave port. 0x2 M2_3 This master has level 4 priority when accessing the slave port. 0x3 M2_4 This master has level 5 priority when accessing the slave port. 0x4 M2_5 This master has level 6 priority when accessing the slave port. 0x5 M2_6 This master has level 7 priority when accessing the slave port. 0x6 M2_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write M3_0 This master has level 1, or highest, priority when accessing the slave port. 0 M3_1 This master has level 2 priority when accessing the slave port. 0x1 M3_2 This master has level 3 priority when accessing the slave port. 0x2 M3_3 This master has level 4 priority when accessing the slave port. 0x3 M3_4 This master has level 5 priority when accessing the slave port. 0x4 M3_5 This master has level 6 priority when accessing the slave port. 0x5 M3_6 This master has level 7 priority when accessing the slave port. 0x6 M3_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M4 Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. 16 3 read-write M4_0 This master has level 1, or highest, priority when accessing the slave port. 0 M4_1 This master has level 2 priority when accessing the slave port. 0x1 M4_2 This master has level 3 priority when accessing the slave port. 0x2 M4_3 This master has level 4 priority when accessing the slave port. 0x3 M4_4 This master has level 5 priority when accessing the slave port. 0x4 M4_5 This master has level 6 priority when accessing the slave port. 0x5 M4_6 This master has level 7 priority when accessing the slave port. 0x6 M4_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M5 Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. 20 3 read-write M5_0 This master has level 1, or highest, priority when accessing the slave port. 0 M5_1 This master has level 2 priority when accessing the slave port. 0x1 M5_2 This master has level 3 priority when accessing the slave port. 0x2 M5_3 This master has level 4 priority when accessing the slave port. 0x3 M5_4 This master has level 5 priority when accessing the slave port. 0x4 M5_5 This master has level 6 priority when accessing the slave port. 0x5 M5_6 This master has level 7 priority when accessing the slave port. 0x6 M5_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 PRS2 Priority Slave Registers 0x200 32 read-write n 0x0 0x0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write M0_0 This master has level 1, or highest, priority when accessing the slave port. 0 M0_1 This master has level 2 priority when accessing the slave port. 0x1 M0_2 This master has level 3 priority when accessing the slave port. 0x2 M0_3 This master has level 4 priority when accessing the slave port. 0x3 M0_4 This master has level 5 priority when accessing the slave port. 0x4 M0_5 This master has level 6 priority when accessing the slave port. 0x5 M0_6 This master has level 7 priority when accessing the slave port. 0x6 M0_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write M1_0 This master has level 1, or highest, priority when accessing the slave port. 0 M1_1 This master has level 2 priority when accessing the slave port. 0x1 M1_2 This master has level 3 priority when accessing the slave port. 0x2 M1_3 This master has level 4 priority when accessing the slave port. 0x3 M1_4 This master has level 5 priority when accessing the slave port. 0x4 M1_5 This master has level 6 priority when accessing the slave port. 0x5 M1_6 This master has level 7 priority when accessing the slave port. 0x6 M1_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write M2_0 This master has level 1, or highest, priority when accessing the slave port. 0 M2_1 This master has level 2 priority when accessing the slave port. 0x1 M2_2 This master has level 3 priority when accessing the slave port. 0x2 M2_3 This master has level 4 priority when accessing the slave port. 0x3 M2_4 This master has level 5 priority when accessing the slave port. 0x4 M2_5 This master has level 6 priority when accessing the slave port. 0x5 M2_6 This master has level 7 priority when accessing the slave port. 0x6 M2_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write M3_0 This master has level 1, or highest, priority when accessing the slave port. 0 M3_1 This master has level 2 priority when accessing the slave port. 0x1 M3_2 This master has level 3 priority when accessing the slave port. 0x2 M3_3 This master has level 4 priority when accessing the slave port. 0x3 M3_4 This master has level 5 priority when accessing the slave port. 0x4 M3_5 This master has level 6 priority when accessing the slave port. 0x5 M3_6 This master has level 7 priority when accessing the slave port. 0x6 M3_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M4 Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. 16 3 read-write M4_0 This master has level 1, or highest, priority when accessing the slave port. 0 M4_1 This master has level 2 priority when accessing the slave port. 0x1 M4_2 This master has level 3 priority when accessing the slave port. 0x2 M4_3 This master has level 4 priority when accessing the slave port. 0x3 M4_4 This master has level 5 priority when accessing the slave port. 0x4 M4_5 This master has level 6 priority when accessing the slave port. 0x5 M4_6 This master has level 7 priority when accessing the slave port. 0x6 M4_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M5 Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. 20 3 read-write M5_0 This master has level 1, or highest, priority when accessing the slave port. 0 M5_1 This master has level 2 priority when accessing the slave port. 0x1 M5_2 This master has level 3 priority when accessing the slave port. 0x2 M5_3 This master has level 4 priority when accessing the slave port. 0x3 M5_4 This master has level 5 priority when accessing the slave port. 0x4 M5_5 This master has level 6 priority when accessing the slave port. 0x5 M5_6 This master has level 7 priority when accessing the slave port. 0x6 M5_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 PRS3 Priority Slave Registers 0x300 32 read-write n 0x0 0x0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write M0_0 This master has level 1, or highest, priority when accessing the slave port. 0 M0_1 This master has level 2 priority when accessing the slave port. 0x1 M0_2 This master has level 3 priority when accessing the slave port. 0x2 M0_3 This master has level 4 priority when accessing the slave port. 0x3 M0_4 This master has level 5 priority when accessing the slave port. 0x4 M0_5 This master has level 6 priority when accessing the slave port. 0x5 M0_6 This master has level 7 priority when accessing the slave port. 0x6 M0_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write M1_0 This master has level 1, or highest, priority when accessing the slave port. 0 M1_1 This master has level 2 priority when accessing the slave port. 0x1 M1_2 This master has level 3 priority when accessing the slave port. 0x2 M1_3 This master has level 4 priority when accessing the slave port. 0x3 M1_4 This master has level 5 priority when accessing the slave port. 0x4 M1_5 This master has level 6 priority when accessing the slave port. 0x5 M1_6 This master has level 7 priority when accessing the slave port. 0x6 M1_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write M2_0 This master has level 1, or highest, priority when accessing the slave port. 0 M2_1 This master has level 2 priority when accessing the slave port. 0x1 M2_2 This master has level 3 priority when accessing the slave port. 0x2 M2_3 This master has level 4 priority when accessing the slave port. 0x3 M2_4 This master has level 5 priority when accessing the slave port. 0x4 M2_5 This master has level 6 priority when accessing the slave port. 0x5 M2_6 This master has level 7 priority when accessing the slave port. 0x6 M2_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write M3_0 This master has level 1, or highest, priority when accessing the slave port. 0 M3_1 This master has level 2 priority when accessing the slave port. 0x1 M3_2 This master has level 3 priority when accessing the slave port. 0x2 M3_3 This master has level 4 priority when accessing the slave port. 0x3 M3_4 This master has level 5 priority when accessing the slave port. 0x4 M3_5 This master has level 6 priority when accessing the slave port. 0x5 M3_6 This master has level 7 priority when accessing the slave port. 0x6 M3_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M4 Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. 16 3 read-write M4_0 This master has level 1, or highest, priority when accessing the slave port. 0 M4_1 This master has level 2 priority when accessing the slave port. 0x1 M4_2 This master has level 3 priority when accessing the slave port. 0x2 M4_3 This master has level 4 priority when accessing the slave port. 0x3 M4_4 This master has level 5 priority when accessing the slave port. 0x4 M4_5 This master has level 6 priority when accessing the slave port. 0x5 M4_6 This master has level 7 priority when accessing the slave port. 0x6 M4_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M5 Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. 20 3 read-write M5_0 This master has level 1, or highest, priority when accessing the slave port. 0 M5_1 This master has level 2 priority when accessing the slave port. 0x1 M5_2 This master has level 3 priority when accessing the slave port. 0x2 M5_3 This master has level 4 priority when accessing the slave port. 0x3 M5_4 This master has level 5 priority when accessing the slave port. 0x4 M5_5 This master has level 6 priority when accessing the slave port. 0x5 M5_6 This master has level 7 priority when accessing the slave port. 0x6 M5_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 PRS4 Priority Slave Registers 0x400 32 read-write n 0x0 0x0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write M0_0 This master has level 1, or highest, priority when accessing the slave port. 0 M0_1 This master has level 2 priority when accessing the slave port. 0x1 M0_2 This master has level 3 priority when accessing the slave port. 0x2 M0_3 This master has level 4 priority when accessing the slave port. 0x3 M0_4 This master has level 5 priority when accessing the slave port. 0x4 M0_5 This master has level 6 priority when accessing the slave port. 0x5 M0_6 This master has level 7 priority when accessing the slave port. 0x6 M0_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write M1_0 This master has level 1, or highest, priority when accessing the slave port. 0 M1_1 This master has level 2 priority when accessing the slave port. 0x1 M1_2 This master has level 3 priority when accessing the slave port. 0x2 M1_3 This master has level 4 priority when accessing the slave port. 0x3 M1_4 This master has level 5 priority when accessing the slave port. 0x4 M1_5 This master has level 6 priority when accessing the slave port. 0x5 M1_6 This master has level 7 priority when accessing the slave port. 0x6 M1_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write M2_0 This master has level 1, or highest, priority when accessing the slave port. 0 M2_1 This master has level 2 priority when accessing the slave port. 0x1 M2_2 This master has level 3 priority when accessing the slave port. 0x2 M2_3 This master has level 4 priority when accessing the slave port. 0x3 M2_4 This master has level 5 priority when accessing the slave port. 0x4 M2_5 This master has level 6 priority when accessing the slave port. 0x5 M2_6 This master has level 7 priority when accessing the slave port. 0x6 M2_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write M3_0 This master has level 1, or highest, priority when accessing the slave port. 0 M3_1 This master has level 2 priority when accessing the slave port. 0x1 M3_2 This master has level 3 priority when accessing the slave port. 0x2 M3_3 This master has level 4 priority when accessing the slave port. 0x3 M3_4 This master has level 5 priority when accessing the slave port. 0x4 M3_5 This master has level 6 priority when accessing the slave port. 0x5 M3_6 This master has level 7 priority when accessing the slave port. 0x6 M3_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M4 Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. 16 3 read-write M4_0 This master has level 1, or highest, priority when accessing the slave port. 0 M4_1 This master has level 2 priority when accessing the slave port. 0x1 M4_2 This master has level 3 priority when accessing the slave port. 0x2 M4_3 This master has level 4 priority when accessing the slave port. 0x3 M4_4 This master has level 5 priority when accessing the slave port. 0x4 M4_5 This master has level 6 priority when accessing the slave port. 0x5 M4_6 This master has level 7 priority when accessing the slave port. 0x6 M4_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 M5 Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. 20 3 read-write M5_0 This master has level 1, or highest, priority when accessing the slave port. 0 M5_1 This master has level 2 priority when accessing the slave port. 0x1 M5_2 This master has level 3 priority when accessing the slave port. 0x2 M5_3 This master has level 4 priority when accessing the slave port. 0x3 M5_4 This master has level 5 priority when accessing the slave port. 0x4 M5_5 This master has level 6 priority when accessing the slave port. 0x5 M5_6 This master has level 7 priority when accessing the slave port. 0x6 M5_7 This master has level 8, or lowest, priority when accessing the slave port. 0x7 CAU3 CAU3 CAU3 0x0 0x0 0x1000 registers n CAU3_Task_Complete 55 CAU3_Security_Violation 56 ARR Address Remap Register 0xFC 32 read-write n 0x0 0x0 ARRL Address Remap Register List 0 32 read-write CC_CF Condition Flag 0x208 32 read-only n 0x0 0x0 C Carry flag 0 1 read-only N Negative flag 3 1 read-only V Overflow flag 1 1 read-only Z Zero flag 2 1 read-only CC_CMD Start Command Register 0x204 32 read-write n 0x0 0x0 CMD Command 16 3 write-only CMD_0 Use CR[DTCCFG] for task completion configuration 0 CMD_1 Issue an interrupt request 0x1 CMD_2 Assert Event Completion Signal 0x2 CMD_4 Issue a DMA request 0x4 CC_PC Program Counter 0x200 32 read-write n 0x0 0x0 PC Program Counter 0 20 read-write CC_R0 CryptoCore General Purpose Registers 0x180 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R1 CryptoCore General Purpose Registers 0x184 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R10 CryptoCore General Purpose Registers 0x1A8 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R11 CryptoCore General Purpose Registers 0x1AC 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R12 CryptoCore General Purpose Registers 0x1B0 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R13 CryptoCore General Purpose Registers 0x1B4 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R14 CryptoCore General Purpose Registers 0x1B8 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R15 CryptoCore General Purpose Registers 0x1BC 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R16 CryptoCore General Purpose Registers 0x1C0 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R17 CryptoCore General Purpose Registers 0x1C4 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R18 CryptoCore General Purpose Registers 0x1C8 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R19 CryptoCore General Purpose Registers 0x1CC 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R2 CryptoCore General Purpose Registers 0x188 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R20 CryptoCore General Purpose Registers 0x1D0 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R21 CryptoCore General Purpose Registers 0x1D4 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R22 CryptoCore General Purpose Registers 0x1D8 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R23 CryptoCore General Purpose Registers 0x1DC 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R24 CryptoCore General Purpose Registers 0x1E0 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R25 CryptoCore General Purpose Registers 0x1E4 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R26 CryptoCore General Purpose Registers 0x1E8 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R27 CryptoCore General Purpose Registers 0x1EC 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R28 CryptoCore General Purpose Registers 0x1F0 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R29 CryptoCore General Purpose Registers 0x1F4 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R3 CryptoCore General Purpose Registers 0x18C 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R30 General Purpose R30 0x1F8 32 read-write n 0x0 0x0 SP Stack Pointer 0 32 read-write CC_R31 General Purpose R31 0x1FC 32 read-write n 0x0 0x0 LR Link 0 32 read-write CC_R4 CryptoCore General Purpose Registers 0x190 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R5 CryptoCore General Purpose Registers 0x194 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R6 CryptoCore General Purpose Registers 0x198 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R7 CryptoCore General Purpose Registers 0x19C 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R8 CryptoCore General Purpose Registers 0x1A0 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CC_R9 CryptoCore General Purpose Registers 0x1A4 32 read-write n 0x0 0x0 R CryptoCore general purpose register R 0 32 read-write CHA_VID CHA Revision ID 0x4F8 32 read-only n 0x0 0x0 PKHAREV PK Revision NUmber 16 4 read-only PKHAVID PK Version ID 20 4 read-only CKLFSR Clock Linear Feedback Shift Register 0x608 32 read-write n 0x0 0x0 LFSR Linear Feedback Shift Register 0 32 read-write COM Command Register 0x430 32 read-write n 0x0 0x0 ALL Reset All Internal Logic 0 1 write-only NO_RESET Do Not Reset 0 RESET_ALL Reset PKHA engine and registers 0x1 PK Reset PKHA 6 1 write-only NO_RESET Do Not Reset 0 RESET_PKHA Reset Public Key Hardware Accelerator 0x1 CR Control Register 0x10 32 read-write n 0x0 0x0 ASREIE AHB Slave Response Error Interrupt Enable 3 1 read-write ASREIE_0 AHB slave response error interruption is not enabled 0 ASREIE_1 AHB slave response error interruption is enabled 0x1 DAESI Disable AES Instructions 30 1 read-write DAESI_0 AES instructions are enabled 0 DAESI_1 AES instructions are disabled 0x1 DDESI Disable DES Instructions 29 1 read-write DDESI_0 DES instructions are enabled 0 DDESI_1 DES instructions are disabled 0x1 DIADIE DMEM Illegal Address Interrupt Enable 5 1 read-write DIADIE_0 DMEM illegal address interruption is not enabled 0 DIADIE_1 DMEM illegal address interruption is enabled 0x1 DSHFI Disable Secure Hash Function Instructions 28 1 read-write DSHFI_0 Secure Hash Functions are enabled 0 DSHFI_1 Secure Hash Functions are disabled 0x1 DTCCFG Default Task Completion Configuration 24 3 read-write DTCCFG_0 no explicit action 0 DTCCFG_1 Issue an Interrupt Request 0x1 DTCCFG_2 Assert Event Completion Signal 0x2 DTCCFG_4 Issue a DMA request 0x4 FSV Force Security Violation Test 16 1 read-write FSV_0 no violation is forced 0 FSV_1 force security violation 0x1 IIADIE IMEM Illegal Address Interrupt Enable 4 1 read-write IIADIE_0 IMEM illegal address interruption is not enabled 0 IIADIE_1 IMEM illegal address interruption is enabled 0x1 ILLIE Illegal Instruction Interrupt Enable 1 1 read-write ILLIE_0 Illegal instruction interrupt requests are disabled 0 ILLIE_1 illegal Instruction interrupt requests are enabled 0x1 MDIS Module Disable 31 1 read-write MDIS_0 CAU3 exits from low power mode 0 MDIS_1 CAU3 enters low power mode 0x1 MRST Module Reset 15 1 write-only MRST_0 no action 0 MRST_1 reset 0x1 RSTSM4 Reset Semaphore 12 2 read-write RSTSM4_0 Idle state 0 RSTSM4_1 Wait for second write 0x1 RSTSM4_2 Clears semaphore if previous state was 01 0x2 SVIE Security Violation Interrupt Enable 6 1 read-write SVIE_0 Security violation interruption is not enabled 0 SVIE_1 Security violation interruption is enabled 0x1 TCIE Task completion with no error interrupt enable 7 1 read-write TCIE_0 Disables task completion with no error to generate an interrupt request 0 TCIE_1 Enables task completion with no error to generate an interrupt request 0x1 TCSEIE Task completion with software error interrupt enable 0 1 read-write TCSEIE_0 Disables task completion with software error to generate an interrupt request 0 TCSEIE_1 Enables task completion with software error to generate an interrupt request 0x1 CTL Control Register 0x434 32 read-write n 0x0 0x0 IM Interrupt Mask 0 1 read-write INT_NOT_MASKED Interrupt not masked. 0 INT_MASKED Interrupt masked 0x1 PDE PKHA Register DMA Enable 4 1 read-write PDE_DISABLED DMA Request and Done signals disabled for the PKHA Registers. 0 PDE_ENABLED DMA Request and Done signals enabled for the PKHA Registers. 0x1 CW Clear Written Register 0x440 32 read-write n 0x0 0x0 CM Clear the Mode Register 0 1 write-only CPKA Clear the PKHA A Size Register 12 1 write-only CPKB Clear the PKHA B Size Register 13 1 write-only CPKE Clear the PKHA E Size Register 15 1 write-only CPKN Clear the PKHA N Size Register 14 1 write-only DBGCSR Debug Control/Status Register 0x20 32 read-write n 0x0 0x0 CHLTF CryptoCore is Halted Status Flag 31 1 read-only CHLTF_0 CryptoCore is not halted 0 CHLTF_1 CryptoCore is halted 0x1 CSTPF CryptoCore is Stopped Status Flag 30 1 read-only CSTPF_0 CryptoCore is not stopped 0 CSTPF_1 CryptoCore is stopped 0x1 DBGGO Debug Go 12 1 write-only DBGGO_0 No action 0 DBGGO_1 Resume program execution 0x1 DDBG Debug Disable 0 1 read-write DDBG_0 debug is enabled 0 DDBG_1 debug is disabled 0x1 DDBGMC Disable Debug Memory Commands 1 1 read-write DDBGMC_0 IPS access to IMEM and DMEM are enabled 0 DDBGMC_1 IPS access to IMEM and DMEM are disabled 0x1 FRCH Force Debug Halt 8 1 read-write FRCH_0 Halt state not forced 0 FRCH_1 Force halt state 0x1 HLTIF CryptoCore is Halted due to HALT Instruction 18 1 read-only HLTIF_0 CryptoCore is not in software breakpoint 0 HLTIF_1 CryptoCore is in software breakpoint 0x1 PBREN PC Breakpoint Register Enable 4 1 read-write PBREN_0 PC breakpoint register (DBGPBR) is disabled 0 PBREN_1 PC breakpoint register (DBGPBR) is enabled 0x1 PCBHF CryptoCore is Halted due to Hardware Breakpoint 16 1 read-only PCBHF_0 CryptoCore is not halted due to a hardware breakpoint 0 PCBHF_1 CryptoCore is halted due to a hardware breakpoint 0x1 SIM Single Instruction Mode 5 1 read-write SIM_0 Single instruction mode is disabled 0 SIM_1 Single instruction mode is enabled 0x1 SIMHF CryptoCore is Halted due to Single Instruction Step 17 1 read-only SIMHF_0 CryptoCore is not in a single step halt 0 SIMHF_1 CryptoCore is in a single step halt 0x1 DBGMADR Debug Memory Address Register 0x34 32 read-write n 0x0 0x0 DMADDR Debug Memory Address 2 30 read-write DBGMCMD Debug Memory Command Register 0x30 32 read-write n 0x0 0x0 BV Byte Reversal Control 28 1 read-write BV_0 DMEM bytes are not reversed 0 BV_1 DMEM bytes are reversed 0x1 DM Instruction/Data Memory Selection 24 1 read-write DM_0 IMEM is selected 0 DM_1 DMEM is selected 0x1 IA Increment Address 26 1 read-write IA_0 Address is not incremented 0 IA_1 Address is incremented after the access 0x1 Rb_1 Read always as 1 27 1 read-only R_0 Read always as 0 30 1 read-only R_1 Read always as 1 31 1 read-only DBGMDR Debug Memory Data Register 0x38 32 read-write n 0x0 0x0 DMDATA Debug Memory Data 0 32 read-write DBGPBR Debug PC Breakpoint Register 0x24 32 read-write n 0x0 0x0 PCBKPT PC Breakpoint 2 18 read-write ESTA Error Status Register 0x44C 32 read-only n 0x0 0x0 CL1 algorithms 8 4 read-only GEN_ERROR General Error 0 PKHA_ERROR Public Key 0x8 ERRID1 Error ID 1 0 4 read-only MODE_ERROR Mode Error 0x1 DATA_SIZE_ERROR PKHA N Register Size Error 0x2 KEY_SIZE_ERROR PKHA E Register Size Error 0x3 PKHA_A_SIZE_ERROR PKHA A Register Size Error 0x4 PKHA_B_SIZE_ERROR PKHA B Register Size Error 0x5 DATA_OUT_OF_SEQ_ERROR PKHA C input (as contained in the PKHA B0 quadrant) is Zero 0x6 PKHA_DIV_BY_0_ERROR PKHA Divide by Zero Error 0x7 PKHA_MOD_EVEN_ERROR PKHA Modulus Even Error 0x8 INVALID_ENGINE_SEL_ERROR Invalid Crypto Engine Selected 0xF GSR Global Status Register 0x604 32 read-only n 0x0 0x0 CDI CAU3 Done Interrupt occurred 10 1 read-only CDI_0 CAU3 Done Interrupt did not occur 0 CDI_1 CAU3 Done Interrupt occurred 0x1 CEI CAU3 Error Interrupt 14 1 read-only CEI_0 CAU3 Error Interrupt did not occur 0 CEI_1 CAU3 Error Interrupt occurred 0x1 PBSY PKHA Busy 31 1 read-only PBSY_0 PKHA not busy 0 PBSY_1 PKHA busy 0x1 PEI PKHA Done or Error Interrupt 15 1 read-only PEI_0 PKHA interrupt did not occur 0 PEI_1 PKHA interrupt had occurred 0x1 MCFG Memory Configuration 0x4 32 read-only n 0x0 0x0 DRAM_SZ Data RAM Size 8 4 read-only DRAM_SZ_0 No memory module 0 DRAM_SZ_4 2K bytes 0x4 DRAM_SZ_5 3K bytes 0x5 DRAM_SZ_6 4K bytes 0x6 DRAM_SZ_7 6K bytes 0x7 DRAM_SZ_8 8K bytes 0x8 DRAM_SZ_9 12K bytes 0x9 DRAM_SZ_10 16K bytes 0xA DRAM_SZ_11 24K bytes 0xB DRAM_SZ_12 32K bytes 0xC DRAM_SZ_13 48K bytes 0xD DRAM_SZ_14 64K bytes 0xE DRAM_SZ_15 96K bytes 0xF IRAM_SZ Instruction RAM Size 24 4 read-only IRAM_SZ_0 No memory module 0 IRAM_SZ_4 2K bytes 0x4 IRAM_SZ_5 3K bytes 0x5 IRAM_SZ_6 4K bytes 0x6 IRAM_SZ_7 6K bytes 0x7 IRAM_SZ_8 8K bytes 0x8 IRAM_SZ_9 12K bytes 0x9 IRAM_SZ_10 16K bytes 0xA IRAM_SZ_11 24K bytes 0xB IRAM_SZ_12 32K bytes 0xC IRAM_SZ_13 48K bytes 0xD IRAM_SZ_14 64K bytes 0xE IRAM_SZ_15 96K bytes 0xF IROM_SZ Instruction ROM Size 16 4 read-only IROM_SZ_0 No memory module 0 IROM_SZ_4 2K bytes 0x4 IROM_SZ_5 3K bytes 0x5 IROM_SZ_6 4K bytes 0x6 IROM_SZ_7 6K bytes 0x7 IROM_SZ_8 8K bytes 0x8 IROM_SZ_9 12K bytes 0x9 IROM_SZ_10 16K bytes 0xA IROM_SZ_11 24K bytes 0xB IROM_SZ_12 32K bytes 0xC IROM_SZ_13 48K bytes 0xD IROM_SZ_14 64K bytes 0xE IROM_SZ_15 96K bytes 0xF MDPK Mode Register (PublicKey) 0x400 32 read-write n 0x0 0x0 ALG Algorithm 20 4 read-write PKHA PKHA 0x8 PKHA_MODE_LS PKHA_MODE least significant 12 bits 0 12 read-write PKHA_MODE_MS PKHA_MODE most-significant 4 bits 16 4 read-write PCT Processor Core Type 0x0 32 read-only n 0x0 0x0 ID Module ID number 8 24 read-only ID_4931936 ID number for basic configuration 0x4B4160 ID_4931937 ID number for PKHA configuration 0x4B4161 X Major version number 4 4 read-only X_0 Major version number 0 Y Minor version number 0 4 read-only Y_0 Minor version number 0 PKA0_0 PKHA A0 Register 0x800 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_1 PKHA A0 Register 0x804 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_10 PKHA A0 Register 0x828 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_11 PKHA A0 Register 0x82C 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_12 PKHA A0 Register 0x830 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_13 PKHA A0 Register 0x834 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_14 PKHA A0 Register 0x838 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_15 PKHA A0 Register 0x83C 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_16 PKHA A0 Register 0x840 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_17 PKHA A0 Register 0x844 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_18 PKHA A0 Register 0x848 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_19 PKHA A0 Register 0x84C 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_2 PKHA A0 Register 0x808 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_20 PKHA A0 Register 0x850 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_21 PKHA A0 Register 0x854 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_22 PKHA A0 Register 0x858 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_23 PKHA A0 Register 0x85C 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_24 PKHA A0 Register 0x860 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_25 PKHA A0 Register 0x864 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_26 PKHA A0 Register 0x868 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_27 PKHA A0 Register 0x86C 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_28 PKHA A0 Register 0x870 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_29 PKHA A0 Register 0x874 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_3 PKHA A0 Register 0x80C 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_30 PKHA A0 Register 0x878 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_31 PKHA A0 Register 0x87C 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_4 PKHA A0 Register 0x810 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_5 PKHA A0 Register 0x814 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_6 PKHA A0 Register 0x818 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_7 PKHA A0 Register 0x81C 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_8 PKHA A0 Register 0x820 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_9 PKHA A0 Register 0x824 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[0] PKHA A0 Register 0x1000 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[10] PKHA A0 Register 0x60DC 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[11] PKHA A0 Register 0x6908 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[12] PKHA A0 Register 0x7138 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[13] PKHA A0 Register 0x796C 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[14] PKHA A0 Register 0x81A4 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[15] PKHA A0 Register 0x89E0 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[16] PKHA A0 Register 0x9220 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[17] PKHA A0 Register 0x9A64 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[18] PKHA A0 Register 0xA2AC 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[19] PKHA A0 Register 0xAAF8 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[1] PKHA A0 Register 0x1804 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[20] PKHA A0 Register 0xB348 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[21] PKHA A0 Register 0xBB9C 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[22] PKHA A0 Register 0xC3F4 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[23] PKHA A0 Register 0xCC50 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[24] PKHA A0 Register 0xD4B0 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[25] PKHA A0 Register 0xDD14 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[26] PKHA A0 Register 0xE57C 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[27] PKHA A0 Register 0xEDE8 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[28] PKHA A0 Register 0xF658 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[29] PKHA A0 Register 0xFECC 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[2] PKHA A0 Register 0x200C 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[30] PKHA A0 Register 0x10744 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[31] PKHA A0 Register 0x10FC0 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[3] PKHA A0 Register 0x2818 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[4] PKHA A0 Register 0x3028 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[5] PKHA A0 Register 0x383C 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[6] PKHA A0 Register 0x4054 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[7] PKHA A0 Register 0x4870 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[8] PKHA A0 Register 0x5090 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA0_[9] PKHA A0 Register 0x58B4 32 read-write n 0x0 0x0 PKHA_A0 A0 VALUE 0 32 read-write PKA1_0 PKHA A1 Register 0x880 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_1 PKHA A1 Register 0x884 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_10 PKHA A1 Register 0x8A8 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_11 PKHA A1 Register 0x8AC 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_12 PKHA A1 Register 0x8B0 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_13 PKHA A1 Register 0x8B4 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_14 PKHA A1 Register 0x8B8 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_15 PKHA A1 Register 0x8BC 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_16 PKHA A1 Register 0x8C0 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_17 PKHA A1 Register 0x8C4 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_18 PKHA A1 Register 0x8C8 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_19 PKHA A1 Register 0x8CC 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_2 PKHA A1 Register 0x888 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_20 PKHA A1 Register 0x8D0 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_21 PKHA A1 Register 0x8D4 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_22 PKHA A1 Register 0x8D8 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_23 PKHA A1 Register 0x8DC 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_24 PKHA A1 Register 0x8E0 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_25 PKHA A1 Register 0x8E4 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_26 PKHA A1 Register 0x8E8 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_27 PKHA A1 Register 0x8EC 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_28 PKHA A1 Register 0x8F0 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_29 PKHA A1 Register 0x8F4 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_3 PKHA A1 Register 0x88C 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_30 PKHA A1 Register 0x8F8 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_31 PKHA A1 Register 0x8FC 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_4 PKHA A1 Register 0x890 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_5 PKHA A1 Register 0x894 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_6 PKHA A1 Register 0x898 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_7 PKHA A1 Register 0x89C 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_8 PKHA A1 Register 0x8A0 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_9 PKHA A1 Register 0x8A4 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[0] PKHA A1 Register 0x1100 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[10] PKHA A1 Register 0x66DC 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[11] PKHA A1 Register 0x6F88 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[12] PKHA A1 Register 0x7838 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[13] PKHA A1 Register 0x80EC 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[14] PKHA A1 Register 0x89A4 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[15] PKHA A1 Register 0x9260 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[16] PKHA A1 Register 0x9B20 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[17] PKHA A1 Register 0xA3E4 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[18] PKHA A1 Register 0xACAC 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[19] PKHA A1 Register 0xB578 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[1] PKHA A1 Register 0x1984 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[20] PKHA A1 Register 0xBE48 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[21] PKHA A1 Register 0xC71C 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[22] PKHA A1 Register 0xCFF4 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[23] PKHA A1 Register 0xD8D0 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[24] PKHA A1 Register 0xE1B0 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[25] PKHA A1 Register 0xEA94 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[26] PKHA A1 Register 0xF37C 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[27] PKHA A1 Register 0xFC68 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[28] PKHA A1 Register 0x10558 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[29] PKHA A1 Register 0x10E4C 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[2] PKHA A1 Register 0x220C 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[30] PKHA A1 Register 0x11744 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[31] PKHA A1 Register 0x12040 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[3] PKHA A1 Register 0x2A98 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[4] PKHA A1 Register 0x3328 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[5] PKHA A1 Register 0x3BBC 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[6] PKHA A1 Register 0x4454 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[7] PKHA A1 Register 0x4CF0 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[8] PKHA A1 Register 0x5590 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA1_[9] PKHA A1 Register 0x5E34 32 read-write n 0x0 0x0 PKHA_A1 A1 VALUE 0 32 read-write PKA2_0 PKHA A2 Register 0x900 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_1 PKHA A2 Register 0x904 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_10 PKHA A2 Register 0x928 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_11 PKHA A2 Register 0x92C 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_12 PKHA A2 Register 0x930 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_13 PKHA A2 Register 0x934 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_14 PKHA A2 Register 0x938 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_15 PKHA A2 Register 0x93C 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_16 PKHA A2 Register 0x940 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_17 PKHA A2 Register 0x944 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_18 PKHA A2 Register 0x948 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_19 PKHA A2 Register 0x94C 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_2 PKHA A2 Register 0x908 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_20 PKHA A2 Register 0x950 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_21 PKHA A2 Register 0x954 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_22 PKHA A2 Register 0x958 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_23 PKHA A2 Register 0x95C 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_24 PKHA A2 Register 0x960 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_25 PKHA A2 Register 0x964 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_26 PKHA A2 Register 0x968 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_27 PKHA A2 Register 0x96C 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_28 PKHA A2 Register 0x970 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_29 PKHA A2 Register 0x974 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_3 PKHA A2 Register 0x90C 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_30 PKHA A2 Register 0x978 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_31 PKHA A2 Register 0x97C 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_4 PKHA A2 Register 0x910 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_5 PKHA A2 Register 0x914 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_6 PKHA A2 Register 0x918 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_7 PKHA A2 Register 0x91C 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_8 PKHA A2 Register 0x920 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_9 PKHA A2 Register 0x924 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[0] PKHA A2 Register 0x1200 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[10] PKHA A2 Register 0x6CDC 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[11] PKHA A2 Register 0x7608 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[12] PKHA A2 Register 0x7F38 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[13] PKHA A2 Register 0x886C 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[14] PKHA A2 Register 0x91A4 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[15] PKHA A2 Register 0x9AE0 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[16] PKHA A2 Register 0xA420 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[17] PKHA A2 Register 0xAD64 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[18] PKHA A2 Register 0xB6AC 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[19] PKHA A2 Register 0xBFF8 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[1] PKHA A2 Register 0x1B04 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[20] PKHA A2 Register 0xC948 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[21] PKHA A2 Register 0xD29C 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[22] PKHA A2 Register 0xDBF4 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[23] PKHA A2 Register 0xE550 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[24] PKHA A2 Register 0xEEB0 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[25] PKHA A2 Register 0xF814 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[26] PKHA A2 Register 0x1017C 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[27] PKHA A2 Register 0x10AE8 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[28] PKHA A2 Register 0x11458 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[29] PKHA A2 Register 0x11DCC 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[2] PKHA A2 Register 0x240C 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[30] PKHA A2 Register 0x12744 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[31] PKHA A2 Register 0x130C0 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[3] PKHA A2 Register 0x2D18 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[4] PKHA A2 Register 0x3628 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[5] PKHA A2 Register 0x3F3C 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[6] PKHA A2 Register 0x4854 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[7] PKHA A2 Register 0x5170 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[8] PKHA A2 Register 0x5A90 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA2_[9] PKHA A2 Register 0x63B4 32 read-write n 0x0 0x0 PKHA_A2 A2 VALUE 0 32 read-write PKA3_0 PKHA A3 Register 0x980 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_1 PKHA A3 Register 0x984 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_10 PKHA A3 Register 0x9A8 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_11 PKHA A3 Register 0x9AC 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_12 PKHA A3 Register 0x9B0 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_13 PKHA A3 Register 0x9B4 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_14 PKHA A3 Register 0x9B8 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_15 PKHA A3 Register 0x9BC 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_16 PKHA A3 Register 0x9C0 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_17 PKHA A3 Register 0x9C4 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_18 PKHA A3 Register 0x9C8 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_19 PKHA A3 Register 0x9CC 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_2 PKHA A3 Register 0x988 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_20 PKHA A3 Register 0x9D0 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_21 PKHA A3 Register 0x9D4 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_22 PKHA A3 Register 0x9D8 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_23 PKHA A3 Register 0x9DC 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_24 PKHA A3 Register 0x9E0 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_25 PKHA A3 Register 0x9E4 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_26 PKHA A3 Register 0x9E8 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_27 PKHA A3 Register 0x9EC 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_28 PKHA A3 Register 0x9F0 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_29 PKHA A3 Register 0x9F4 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_3 PKHA A3 Register 0x98C 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_30 PKHA A3 Register 0x9F8 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_31 PKHA A3 Register 0x9FC 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_4 PKHA A3 Register 0x990 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_5 PKHA A3 Register 0x994 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_6 PKHA A3 Register 0x998 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_7 PKHA A3 Register 0x99C 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_8 PKHA A3 Register 0x9A0 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_9 PKHA A3 Register 0x9A4 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[0] PKHA A3 Register 0x1300 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[10] PKHA A3 Register 0x72DC 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[11] PKHA A3 Register 0x7C88 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[12] PKHA A3 Register 0x8638 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[13] PKHA A3 Register 0x8FEC 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[14] PKHA A3 Register 0x99A4 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[15] PKHA A3 Register 0xA360 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[16] PKHA A3 Register 0xAD20 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[17] PKHA A3 Register 0xB6E4 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[18] PKHA A3 Register 0xC0AC 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[19] PKHA A3 Register 0xCA78 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[1] PKHA A3 Register 0x1C84 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[20] PKHA A3 Register 0xD448 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[21] PKHA A3 Register 0xDE1C 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[22] PKHA A3 Register 0xE7F4 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[23] PKHA A3 Register 0xF1D0 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[24] PKHA A3 Register 0xFBB0 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[25] PKHA A3 Register 0x10594 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[26] PKHA A3 Register 0x10F7C 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[27] PKHA A3 Register 0x11968 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[28] PKHA A3 Register 0x12358 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[29] PKHA A3 Register 0x12D4C 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[2] PKHA A3 Register 0x260C 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[30] PKHA A3 Register 0x13744 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[31] PKHA A3 Register 0x14140 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[3] PKHA A3 Register 0x2F98 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[4] PKHA A3 Register 0x3928 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[5] PKHA A3 Register 0x42BC 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[6] PKHA A3 Register 0x4C54 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[7] PKHA A3 Register 0x55F0 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[8] PKHA A3 Register 0x5F90 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKA3_[9] PKHA A3 Register 0x6934 32 read-write n 0x0 0x0 PKHA_A3 A3 VALUE 0 32 read-write PKASZ PKHA A Size Register 0x480 32 read-write n 0x0 0x0 PKASZ PKHA A Size 0 9 read-write PKB0_0 PKHA B0 Register 0xA00 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_1 PKHA B0 Register 0xA04 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_10 PKHA B0 Register 0xA28 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_11 PKHA B0 Register 0xA2C 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_12 PKHA B0 Register 0xA30 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_13 PKHA B0 Register 0xA34 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_14 PKHA B0 Register 0xA38 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_15 PKHA B0 Register 0xA3C 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_16 PKHA B0 Register 0xA40 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_17 PKHA B0 Register 0xA44 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_18 PKHA B0 Register 0xA48 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_19 PKHA B0 Register 0xA4C 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_2 PKHA B0 Register 0xA08 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_20 PKHA B0 Register 0xA50 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_21 PKHA B0 Register 0xA54 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_22 PKHA B0 Register 0xA58 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_23 PKHA B0 Register 0xA5C 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_24 PKHA B0 Register 0xA60 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_25 PKHA B0 Register 0xA64 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_26 PKHA B0 Register 0xA68 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_27 PKHA B0 Register 0xA6C 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_28 PKHA B0 Register 0xA70 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_29 PKHA B0 Register 0xA74 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_3 PKHA B0 Register 0xA0C 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_30 PKHA B0 Register 0xA78 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_31 PKHA B0 Register 0xA7C 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_4 PKHA B0 Register 0xA10 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_5 PKHA B0 Register 0xA14 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_6 PKHA B0 Register 0xA18 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_7 PKHA B0 Register 0xA1C 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_8 PKHA B0 Register 0xA20 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_9 PKHA B0 Register 0xA24 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[0] PKHA B0 Register 0x1400 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[10] PKHA B0 Register 0x78DC 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[11] PKHA B0 Register 0x8308 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[12] PKHA B0 Register 0x8D38 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[13] PKHA B0 Register 0x976C 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[14] PKHA B0 Register 0xA1A4 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[15] PKHA B0 Register 0xABE0 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[16] PKHA B0 Register 0xB620 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[17] PKHA B0 Register 0xC064 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[18] PKHA B0 Register 0xCAAC 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[19] PKHA B0 Register 0xD4F8 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[1] PKHA B0 Register 0x1E04 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[20] PKHA B0 Register 0xDF48 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[21] PKHA B0 Register 0xE99C 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[22] PKHA B0 Register 0xF3F4 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[23] PKHA B0 Register 0xFE50 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[24] PKHA B0 Register 0x108B0 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[25] PKHA B0 Register 0x11314 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[26] PKHA B0 Register 0x11D7C 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[27] PKHA B0 Register 0x127E8 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[28] PKHA B0 Register 0x13258 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[29] PKHA B0 Register 0x13CCC 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[2] PKHA B0 Register 0x280C 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[30] PKHA B0 Register 0x14744 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[31] PKHA B0 Register 0x151C0 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[3] PKHA B0 Register 0x3218 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[4] PKHA B0 Register 0x3C28 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[5] PKHA B0 Register 0x463C 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[6] PKHA B0 Register 0x5054 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[7] PKHA B0 Register 0x5A70 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[8] PKHA B0 Register 0x6490 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB0_[9] PKHA B0 Register 0x6EB4 32 read-write n 0x0 0x0 PKHA_B0 B0 VALUE 0 32 read-write PKB1_0 PKHA B1 Register 0xA80 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_1 PKHA B1 Register 0xA84 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_10 PKHA B1 Register 0xAA8 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_11 PKHA B1 Register 0xAAC 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_12 PKHA B1 Register 0xAB0 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_13 PKHA B1 Register 0xAB4 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_14 PKHA B1 Register 0xAB8 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_15 PKHA B1 Register 0xABC 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_16 PKHA B1 Register 0xAC0 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_17 PKHA B1 Register 0xAC4 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_18 PKHA B1 Register 0xAC8 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_19 PKHA B1 Register 0xACC 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_2 PKHA B1 Register 0xA88 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_20 PKHA B1 Register 0xAD0 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_21 PKHA B1 Register 0xAD4 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_22 PKHA B1 Register 0xAD8 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_23 PKHA B1 Register 0xADC 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_24 PKHA B1 Register 0xAE0 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_25 PKHA B1 Register 0xAE4 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_26 PKHA B1 Register 0xAE8 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_27 PKHA B1 Register 0xAEC 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_28 PKHA B1 Register 0xAF0 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_29 PKHA B1 Register 0xAF4 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_3 PKHA B1 Register 0xA8C 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_30 PKHA B1 Register 0xAF8 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_31 PKHA B1 Register 0xAFC 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_4 PKHA B1 Register 0xA90 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_5 PKHA B1 Register 0xA94 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_6 PKHA B1 Register 0xA98 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_7 PKHA B1 Register 0xA9C 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_8 PKHA B1 Register 0xAA0 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_9 PKHA B1 Register 0xAA4 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[0] PKHA B1 Register 0x1500 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[10] PKHA B1 Register 0x7EDC 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[11] PKHA B1 Register 0x8988 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[12] PKHA B1 Register 0x9438 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[13] PKHA B1 Register 0x9EEC 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[14] PKHA B1 Register 0xA9A4 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[15] PKHA B1 Register 0xB460 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[16] PKHA B1 Register 0xBF20 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[17] PKHA B1 Register 0xC9E4 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[18] PKHA B1 Register 0xD4AC 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[19] PKHA B1 Register 0xDF78 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[1] PKHA B1 Register 0x1F84 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[20] PKHA B1 Register 0xEA48 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[21] PKHA B1 Register 0xF51C 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[22] PKHA B1 Register 0xFFF4 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[23] PKHA B1 Register 0x10AD0 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[24] PKHA B1 Register 0x115B0 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[25] PKHA B1 Register 0x12094 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[26] PKHA B1 Register 0x12B7C 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[27] PKHA B1 Register 0x13668 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[28] PKHA B1 Register 0x14158 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[29] PKHA B1 Register 0x14C4C 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[2] PKHA B1 Register 0x2A0C 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[30] PKHA B1 Register 0x15744 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[31] PKHA B1 Register 0x16240 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[3] PKHA B1 Register 0x3498 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[4] PKHA B1 Register 0x3F28 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[5] PKHA B1 Register 0x49BC 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[6] PKHA B1 Register 0x5454 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[7] PKHA B1 Register 0x5EF0 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[8] PKHA B1 Register 0x6990 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB1_[9] PKHA B1 Register 0x7434 32 read-write n 0x0 0x0 PKHA_B1 B1 VALUE 0 32 read-write PKB2_0 PKHA B2 Register 0xB00 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_1 PKHA B2 Register 0xB04 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_10 PKHA B2 Register 0xB28 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_11 PKHA B2 Register 0xB2C 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_12 PKHA B2 Register 0xB30 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_13 PKHA B2 Register 0xB34 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_14 PKHA B2 Register 0xB38 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_15 PKHA B2 Register 0xB3C 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_16 PKHA B2 Register 0xB40 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_17 PKHA B2 Register 0xB44 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_18 PKHA B2 Register 0xB48 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_19 PKHA B2 Register 0xB4C 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_2 PKHA B2 Register 0xB08 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_20 PKHA B2 Register 0xB50 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_21 PKHA B2 Register 0xB54 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_22 PKHA B2 Register 0xB58 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_23 PKHA B2 Register 0xB5C 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_24 PKHA B2 Register 0xB60 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_25 PKHA B2 Register 0xB64 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_26 PKHA B2 Register 0xB68 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_27 PKHA B2 Register 0xB6C 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_28 PKHA B2 Register 0xB70 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_29 PKHA B2 Register 0xB74 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_3 PKHA B2 Register 0xB0C 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_30 PKHA B2 Register 0xB78 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_31 PKHA B2 Register 0xB7C 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_4 PKHA B2 Register 0xB10 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_5 PKHA B2 Register 0xB14 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_6 PKHA B2 Register 0xB18 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_7 PKHA B2 Register 0xB1C 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_8 PKHA B2 Register 0xB20 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_9 PKHA B2 Register 0xB24 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[0] PKHA B2 Register 0x1600 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[10] PKHA B2 Register 0x84DC 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[11] PKHA B2 Register 0x9008 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[12] PKHA B2 Register 0x9B38 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[13] PKHA B2 Register 0xA66C 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[14] PKHA B2 Register 0xB1A4 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[15] PKHA B2 Register 0xBCE0 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[16] PKHA B2 Register 0xC820 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[17] PKHA B2 Register 0xD364 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[18] PKHA B2 Register 0xDEAC 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[19] PKHA B2 Register 0xE9F8 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[1] PKHA B2 Register 0x2104 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[20] PKHA B2 Register 0xF548 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[21] PKHA B2 Register 0x1009C 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[22] PKHA B2 Register 0x10BF4 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[23] PKHA B2 Register 0x11750 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[24] PKHA B2 Register 0x122B0 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[25] PKHA B2 Register 0x12E14 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[26] PKHA B2 Register 0x1397C 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[27] PKHA B2 Register 0x144E8 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[28] PKHA B2 Register 0x15058 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[29] PKHA B2 Register 0x15BCC 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[2] PKHA B2 Register 0x2C0C 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[30] PKHA B2 Register 0x16744 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[31] PKHA B2 Register 0x172C0 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[3] PKHA B2 Register 0x3718 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[4] PKHA B2 Register 0x4228 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[5] PKHA B2 Register 0x4D3C 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[6] PKHA B2 Register 0x5854 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[7] PKHA B2 Register 0x6370 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[8] PKHA B2 Register 0x6E90 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB2_[9] PKHA B2 Register 0x79B4 32 read-write n 0x0 0x0 PKHA_B2 B2 VALUE 0 32 read-write PKB3_0 PKHA B3 Register 0xB80 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_1 PKHA B3 Register 0xB84 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_10 PKHA B3 Register 0xBA8 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_11 PKHA B3 Register 0xBAC 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_12 PKHA B3 Register 0xBB0 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_13 PKHA B3 Register 0xBB4 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_14 PKHA B3 Register 0xBB8 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_15 PKHA B3 Register 0xBBC 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_16 PKHA B3 Register 0xBC0 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_17 PKHA B3 Register 0xBC4 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_18 PKHA B3 Register 0xBC8 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_19 PKHA B3 Register 0xBCC 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_2 PKHA B3 Register 0xB88 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_20 PKHA B3 Register 0xBD0 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_21 PKHA B3 Register 0xBD4 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_22 PKHA B3 Register 0xBD8 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_23 PKHA B3 Register 0xBDC 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_24 PKHA B3 Register 0xBE0 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_25 PKHA B3 Register 0xBE4 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_26 PKHA B3 Register 0xBE8 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_27 PKHA B3 Register 0xBEC 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_28 PKHA B3 Register 0xBF0 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_29 PKHA B3 Register 0xBF4 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_3 PKHA B3 Register 0xB8C 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_30 PKHA B3 Register 0xBF8 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_31 PKHA B3 Register 0xBFC 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_4 PKHA B3 Register 0xB90 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_5 PKHA B3 Register 0xB94 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_6 PKHA B3 Register 0xB98 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_7 PKHA B3 Register 0xB9C 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_8 PKHA B3 Register 0xBA0 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_9 PKHA B3 Register 0xBA4 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[0] PKHA B3 Register 0x1700 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[10] PKHA B3 Register 0x8ADC 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[11] PKHA B3 Register 0x9688 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[12] PKHA B3 Register 0xA238 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[13] PKHA B3 Register 0xADEC 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[14] PKHA B3 Register 0xB9A4 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[15] PKHA B3 Register 0xC560 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[16] PKHA B3 Register 0xD120 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[17] PKHA B3 Register 0xDCE4 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[18] PKHA B3 Register 0xE8AC 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[19] PKHA B3 Register 0xF478 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[1] PKHA B3 Register 0x2284 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[20] PKHA B3 Register 0x10048 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[21] PKHA B3 Register 0x10C1C 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[22] PKHA B3 Register 0x117F4 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[23] PKHA B3 Register 0x123D0 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[24] PKHA B3 Register 0x12FB0 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[25] PKHA B3 Register 0x13B94 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[26] PKHA B3 Register 0x1477C 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[27] PKHA B3 Register 0x15368 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[28] PKHA B3 Register 0x15F58 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[29] PKHA B3 Register 0x16B4C 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[2] PKHA B3 Register 0x2E0C 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[30] PKHA B3 Register 0x17744 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[31] PKHA B3 Register 0x18340 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[3] PKHA B3 Register 0x3998 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[4] PKHA B3 Register 0x4528 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[5] PKHA B3 Register 0x50BC 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[6] PKHA B3 Register 0x5C54 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[7] PKHA B3 Register 0x67F0 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[8] PKHA B3 Register 0x7390 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKB3_[9] PKHA B3 Register 0x7F34 32 read-write n 0x0 0x0 PKHA_B3 B3 VALUE 0 32 read-write PKBSZ PKHA B Size Register 0x488 32 read-write n 0x0 0x0 PKBSZ PKHA B Size 0 9 read-write PKESZ PKHA E Size Register 0x498 32 read-write n 0x0 0x0 PKESZ PKHA E Size 0 9 read-write PKE_0 PKHA E Register 0xE00 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_1 PKHA E Register 0xE04 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_10 PKHA E Register 0xE28 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_100 PKHA E Register 0xF90 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_101 PKHA E Register 0xF94 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_102 PKHA E Register 0xF98 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_103 PKHA E Register 0xF9C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_104 PKHA E Register 0xFA0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_105 PKHA E Register 0xFA4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_106 PKHA E Register 0xFA8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_107 PKHA E Register 0xFAC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_108 PKHA E Register 0xFB0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_109 PKHA E Register 0xFB4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_11 PKHA E Register 0xE2C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_110 PKHA E Register 0xFB8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_111 PKHA E Register 0xFBC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_112 PKHA E Register 0xFC0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_113 PKHA E Register 0xFC4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_114 PKHA E Register 0xFC8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_115 PKHA E Register 0xFCC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_116 PKHA E Register 0xFD0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_117 PKHA E Register 0xFD4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_118 PKHA E Register 0xFD8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_119 PKHA E Register 0xFDC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_12 PKHA E Register 0xE30 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_120 PKHA E Register 0xFE0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_121 PKHA E Register 0xFE4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_122 PKHA E Register 0xFE8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_123 PKHA E Register 0xFEC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_124 PKHA E Register 0xFF0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_125 PKHA E Register 0xFF4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_126 PKHA E Register 0xFF8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_127 PKHA E Register 0xFFC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_13 PKHA E Register 0xE34 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_14 PKHA E Register 0xE38 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_15 PKHA E Register 0xE3C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_16 PKHA E Register 0xE40 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_17 PKHA E Register 0xE44 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_18 PKHA E Register 0xE48 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_19 PKHA E Register 0xE4C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_2 PKHA E Register 0xE08 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_20 PKHA E Register 0xE50 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_21 PKHA E Register 0xE54 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_22 PKHA E Register 0xE58 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_23 PKHA E Register 0xE5C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_24 PKHA E Register 0xE60 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_25 PKHA E Register 0xE64 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_26 PKHA E Register 0xE68 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_27 PKHA E Register 0xE6C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_28 PKHA E Register 0xE70 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_29 PKHA E Register 0xE74 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_3 PKHA E Register 0xE0C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_30 PKHA E Register 0xE78 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_31 PKHA E Register 0xE7C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_32 PKHA E Register 0xE80 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_33 PKHA E Register 0xE84 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_34 PKHA E Register 0xE88 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_35 PKHA E Register 0xE8C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_36 PKHA E Register 0xE90 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_37 PKHA E Register 0xE94 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_38 PKHA E Register 0xE98 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_39 PKHA E Register 0xE9C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_4 PKHA E Register 0xE10 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_40 PKHA E Register 0xEA0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_41 PKHA E Register 0xEA4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_42 PKHA E Register 0xEA8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_43 PKHA E Register 0xEAC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_44 PKHA E Register 0xEB0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_45 PKHA E Register 0xEB4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_46 PKHA E Register 0xEB8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_47 PKHA E Register 0xEBC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_48 PKHA E Register 0xEC0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_49 PKHA E Register 0xEC4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_5 PKHA E Register 0xE14 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_50 PKHA E Register 0xEC8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_51 PKHA E Register 0xECC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_52 PKHA E Register 0xED0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_53 PKHA E Register 0xED4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_54 PKHA E Register 0xED8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_55 PKHA E Register 0xEDC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_56 PKHA E Register 0xEE0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_57 PKHA E Register 0xEE4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_58 PKHA E Register 0xEE8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_59 PKHA E Register 0xEEC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_6 PKHA E Register 0xE18 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_60 PKHA E Register 0xEF0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_61 PKHA E Register 0xEF4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_62 PKHA E Register 0xEF8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_63 PKHA E Register 0xEFC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_64 PKHA E Register 0xF00 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_65 PKHA E Register 0xF04 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_66 PKHA E Register 0xF08 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_67 PKHA E Register 0xF0C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_68 PKHA E Register 0xF10 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_69 PKHA E Register 0xF14 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_7 PKHA E Register 0xE1C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_70 PKHA E Register 0xF18 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_71 PKHA E Register 0xF1C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_72 PKHA E Register 0xF20 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_73 PKHA E Register 0xF24 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_74 PKHA E Register 0xF28 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_75 PKHA E Register 0xF2C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_76 PKHA E Register 0xF30 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_77 PKHA E Register 0xF34 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_78 PKHA E Register 0xF38 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_79 PKHA E Register 0xF3C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_8 PKHA E Register 0xE20 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_80 PKHA E Register 0xF40 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_81 PKHA E Register 0xF44 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_82 PKHA E Register 0xF48 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_83 PKHA E Register 0xF4C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_84 PKHA E Register 0xF50 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_85 PKHA E Register 0xF54 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_86 PKHA E Register 0xF58 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_87 PKHA E Register 0xF5C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_88 PKHA E Register 0xF60 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_89 PKHA E Register 0xF64 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_9 PKHA E Register 0xE24 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_90 PKHA E Register 0xF68 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_91 PKHA E Register 0xF6C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_92 PKHA E Register 0xF70 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_93 PKHA E Register 0xF74 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_94 PKHA E Register 0xF78 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_95 PKHA E Register 0xF7C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_96 PKHA E Register 0xF80 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_97 PKHA E Register 0xF84 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_98 PKHA E Register 0xF88 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_99 PKHA E Register 0xF8C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[0] PKHA E Register 0x1C00 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[100] PKHA E Register 0x5E2E8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[101] PKHA E Register 0x5F27C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[102] PKHA E Register 0x60214 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[103] PKHA E Register 0x611B0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[104] PKHA E Register 0x62150 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[105] PKHA E Register 0x630F4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[106] PKHA E Register 0x6409C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[107] PKHA E Register 0x65048 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[108] PKHA E Register 0x65FF8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[109] PKHA E Register 0x66FAC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[10] PKHA E Register 0xA8DC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[110] PKHA E Register 0x67F64 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[111] PKHA E Register 0x68F20 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[112] PKHA E Register 0x69EE0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[113] PKHA E Register 0x6AEA4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[114] PKHA E Register 0x6BE6C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[115] PKHA E Register 0x6CE38 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[116] PKHA E Register 0x6DE08 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[117] PKHA E Register 0x6EDDC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[118] PKHA E Register 0x6FDB4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[119] PKHA E Register 0x70D90 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[11] PKHA E Register 0xB708 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[120] PKHA E Register 0x71D70 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[121] PKHA E Register 0x72D54 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[122] PKHA E Register 0x73D3C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[123] PKHA E Register 0x74D28 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[124] PKHA E Register 0x75D18 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[125] PKHA E Register 0x76D0C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[126] PKHA E Register 0x77D04 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[127] PKHA E Register 0x78D00 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[12] PKHA E Register 0xC538 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[13] PKHA E Register 0xD36C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[14] PKHA E Register 0xE1A4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[15] PKHA E Register 0xEFE0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[16] PKHA E Register 0xFE20 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[17] PKHA E Register 0x10C64 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[18] PKHA E Register 0x11AAC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[19] PKHA E Register 0x128F8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[1] PKHA E Register 0x2A04 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[20] PKHA E Register 0x13748 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[21] PKHA E Register 0x1459C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[22] PKHA E Register 0x153F4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[23] PKHA E Register 0x16250 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[24] PKHA E Register 0x170B0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[25] PKHA E Register 0x17F14 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[26] PKHA E Register 0x18D7C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[27] PKHA E Register 0x19BE8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[28] PKHA E Register 0x1AA58 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[29] PKHA E Register 0x1B8CC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[2] PKHA E Register 0x380C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[30] PKHA E Register 0x1C744 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[31] PKHA E Register 0x1D5C0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[32] PKHA E Register 0x1E440 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[33] PKHA E Register 0x1F2C4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[34] PKHA E Register 0x2014C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[35] PKHA E Register 0x20FD8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[36] PKHA E Register 0x21E68 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[37] PKHA E Register 0x22CFC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[38] PKHA E Register 0x23B94 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[39] PKHA E Register 0x24A30 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[3] PKHA E Register 0x4618 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[40] PKHA E Register 0x258D0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[41] PKHA E Register 0x26774 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[42] PKHA E Register 0x2761C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[43] PKHA E Register 0x284C8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[44] PKHA E Register 0x29378 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[45] PKHA E Register 0x2A22C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[46] PKHA E Register 0x2B0E4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[47] PKHA E Register 0x2BFA0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[48] PKHA E Register 0x2CE60 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[49] PKHA E Register 0x2DD24 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[4] PKHA E Register 0x5428 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[50] PKHA E Register 0x2EBEC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[51] PKHA E Register 0x2FAB8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[52] PKHA E Register 0x30988 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[53] PKHA E Register 0x3185C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[54] PKHA E Register 0x32734 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[55] PKHA E Register 0x33610 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[56] PKHA E Register 0x344F0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[57] PKHA E Register 0x353D4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[58] PKHA E Register 0x362BC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[59] PKHA E Register 0x371A8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[5] PKHA E Register 0x623C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[60] PKHA E Register 0x38098 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[61] PKHA E Register 0x38F8C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[62] PKHA E Register 0x39E84 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[63] PKHA E Register 0x3AD80 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[64] PKHA E Register 0x3BC80 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[65] PKHA E Register 0x3CB84 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[66] PKHA E Register 0x3DA8C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[67] PKHA E Register 0x3E998 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[68] PKHA E Register 0x3F8A8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[69] PKHA E Register 0x407BC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[6] PKHA E Register 0x7054 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[70] PKHA E Register 0x416D4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[71] PKHA E Register 0x425F0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[72] PKHA E Register 0x43510 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[73] PKHA E Register 0x44434 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[74] PKHA E Register 0x4535C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[75] PKHA E Register 0x46288 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[76] PKHA E Register 0x471B8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[77] PKHA E Register 0x480EC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[78] PKHA E Register 0x49024 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[79] PKHA E Register 0x49F60 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[7] PKHA E Register 0x7E70 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[80] PKHA E Register 0x4AEA0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[81] PKHA E Register 0x4BDE4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[82] PKHA E Register 0x4CD2C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[83] PKHA E Register 0x4DC78 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[84] PKHA E Register 0x4EBC8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[85] PKHA E Register 0x4FB1C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[86] PKHA E Register 0x50A74 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[87] PKHA E Register 0x519D0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[88] PKHA E Register 0x52930 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[89] PKHA E Register 0x53894 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[8] PKHA E Register 0x8C90 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[90] PKHA E Register 0x547FC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[91] PKHA E Register 0x55768 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[92] PKHA E Register 0x566D8 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[93] PKHA E Register 0x5764C 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[94] PKHA E Register 0x585C4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[95] PKHA E Register 0x59540 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[96] PKHA E Register 0x5A4C0 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[97] PKHA E Register 0x5B444 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[98] PKHA E Register 0x5C3CC 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[99] PKHA E Register 0x5D358 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKE_[9] PKHA E Register 0x9AB4 32 write-only n 0x0 0x0 PKHA_E E VALUE 0 32 write-only PKHA_CCR PKHA Clock Control Register 0x600 32 read-write n 0x0 0x0 CKTHRT Clock Throttle selection 0 3 read-write CKTHRT_0 PKHA clock division rate is 8/8 - full speed 0 CKTHRT_1 PKHA clock division rate is 1/8 0x1 CKTHRT_2 PKHA clock division rate is 2/8 0x2 CKTHRT_3 PKHA clock division rate is 3/8 0x3 CKTHRT_4 PKHA clock division rate is 4/8 0x4 CKTHRT_5 PKHA clock division rate is 5/8 0x5 CKTHRT_6 PKHA clock division rate is 6/8 0x6 CKTHRT_7 PKHA clock division rate is 7/8 0x7 ECJ Enable Clock Jitter 30 1 read-write ECJ_0 Clock Jitter is disabled 0 ECJ_1 Clock jitter is enabled 0x1 ECT Enable Clock Throttle 31 1 read-write ECT_0 PKHA clock throttle disabled meaning that PKHA is operatiing at full speed 0 ECT_1 PKHA clock throttle enabled 0x1 ELFR Enable Linear Feedback Shift Register 29 1 read-write ELFR_0 LFSR is only enabled if ECT = 1 and ECJ = 1 0 ELFR_1 LFSR is enabled independently of ECT and ECJ 0x1 LK Register Lock 24 1 read-write LK_0 Register is unlocked 0 LK_1 Register is locked 0x1 PKHA_VID1 PKHA Revision ID 1 0x4F0 32 read-only n 0x0 0x0 IP_ID Hardware Revision ID 16 16 read-only MAJ_REV Major Revision Number 8 8 read-only MIN_REV Minor Revision Number 0 8 read-only PKHA_VID2 PKHA Revision ID 2 0x4F4 32 read-only n 0x0 0x0 ARCH_ERA Architecture ERA 8 8 read-only ECO_REV ECO Revision Number 0 8 read-only PKN0_0 PKHA N0 Register 0xC00 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_1 PKHA N0 Register 0xC04 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_10 PKHA N0 Register 0xC28 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_11 PKHA N0 Register 0xC2C 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_12 PKHA N0 Register 0xC30 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_13 PKHA N0 Register 0xC34 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_14 PKHA N0 Register 0xC38 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_15 PKHA N0 Register 0xC3C 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_16 PKHA N0 Register 0xC40 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_17 PKHA N0 Register 0xC44 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_18 PKHA N0 Register 0xC48 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_19 PKHA N0 Register 0xC4C 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_2 PKHA N0 Register 0xC08 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_20 PKHA N0 Register 0xC50 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_21 PKHA N0 Register 0xC54 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_22 PKHA N0 Register 0xC58 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_23 PKHA N0 Register 0xC5C 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_24 PKHA N0 Register 0xC60 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_25 PKHA N0 Register 0xC64 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_26 PKHA N0 Register 0xC68 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_27 PKHA N0 Register 0xC6C 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_28 PKHA N0 Register 0xC70 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_29 PKHA N0 Register 0xC74 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_3 PKHA N0 Register 0xC0C 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_30 PKHA N0 Register 0xC78 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_31 PKHA N0 Register 0xC7C 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_4 PKHA N0 Register 0xC10 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_5 PKHA N0 Register 0xC14 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_6 PKHA N0 Register 0xC18 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_7 PKHA N0 Register 0xC1C 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_8 PKHA N0 Register 0xC20 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_9 PKHA N0 Register 0xC24 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[0] PKHA N0 Register 0x1800 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[10] PKHA N0 Register 0x90DC 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[11] PKHA N0 Register 0x9D08 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[12] PKHA N0 Register 0xA938 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[13] PKHA N0 Register 0xB56C 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[14] PKHA N0 Register 0xC1A4 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[15] PKHA N0 Register 0xCDE0 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[16] PKHA N0 Register 0xDA20 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[17] PKHA N0 Register 0xE664 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[18] PKHA N0 Register 0xF2AC 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[19] PKHA N0 Register 0xFEF8 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[1] PKHA N0 Register 0x2404 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[20] PKHA N0 Register 0x10B48 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[21] PKHA N0 Register 0x1179C 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[22] PKHA N0 Register 0x123F4 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[23] PKHA N0 Register 0x13050 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[24] PKHA N0 Register 0x13CB0 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[25] PKHA N0 Register 0x14914 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[26] PKHA N0 Register 0x1557C 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[27] PKHA N0 Register 0x161E8 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[28] PKHA N0 Register 0x16E58 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[29] PKHA N0 Register 0x17ACC 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[2] PKHA N0 Register 0x300C 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[30] PKHA N0 Register 0x18744 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[31] PKHA N0 Register 0x193C0 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[3] PKHA N0 Register 0x3C18 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[4] PKHA N0 Register 0x4828 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[5] PKHA N0 Register 0x543C 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[6] PKHA N0 Register 0x6054 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[7] PKHA N0 Register 0x6C70 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[8] PKHA N0 Register 0x7890 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN0_[9] PKHA N0 Register 0x84B4 32 read-write n 0x0 0x0 PKHA_N0 N0 VALUE 0 32 read-write PKN1_0 PKHA N1 Register 0xC80 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_1 PKHA N1 Register 0xC84 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_10 PKHA N1 Register 0xCA8 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_11 PKHA N1 Register 0xCAC 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_12 PKHA N1 Register 0xCB0 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_13 PKHA N1 Register 0xCB4 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_14 PKHA N1 Register 0xCB8 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_15 PKHA N1 Register 0xCBC 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_16 PKHA N1 Register 0xCC0 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_17 PKHA N1 Register 0xCC4 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_18 PKHA N1 Register 0xCC8 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_19 PKHA N1 Register 0xCCC 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_2 PKHA N1 Register 0xC88 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_20 PKHA N1 Register 0xCD0 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_21 PKHA N1 Register 0xCD4 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_22 PKHA N1 Register 0xCD8 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_23 PKHA N1 Register 0xCDC 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_24 PKHA N1 Register 0xCE0 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_25 PKHA N1 Register 0xCE4 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_26 PKHA N1 Register 0xCE8 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_27 PKHA N1 Register 0xCEC 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_28 PKHA N1 Register 0xCF0 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_29 PKHA N1 Register 0xCF4 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_3 PKHA N1 Register 0xC8C 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_30 PKHA N1 Register 0xCF8 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_31 PKHA N1 Register 0xCFC 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_4 PKHA N1 Register 0xC90 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_5 PKHA N1 Register 0xC94 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_6 PKHA N1 Register 0xC98 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_7 PKHA N1 Register 0xC9C 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_8 PKHA N1 Register 0xCA0 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_9 PKHA N1 Register 0xCA4 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[0] PKHA N1 Register 0x1900 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[10] PKHA N1 Register 0x96DC 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[11] PKHA N1 Register 0xA388 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[12] PKHA N1 Register 0xB038 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[13] PKHA N1 Register 0xBCEC 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[14] PKHA N1 Register 0xC9A4 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[15] PKHA N1 Register 0xD660 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[16] PKHA N1 Register 0xE320 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[17] PKHA N1 Register 0xEFE4 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[18] PKHA N1 Register 0xFCAC 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[19] PKHA N1 Register 0x10978 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[1] PKHA N1 Register 0x2584 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[20] PKHA N1 Register 0x11648 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[21] PKHA N1 Register 0x1231C 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[22] PKHA N1 Register 0x12FF4 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[23] PKHA N1 Register 0x13CD0 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[24] PKHA N1 Register 0x149B0 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[25] PKHA N1 Register 0x15694 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[26] PKHA N1 Register 0x1637C 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[27] PKHA N1 Register 0x17068 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[28] PKHA N1 Register 0x17D58 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[29] PKHA N1 Register 0x18A4C 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[2] PKHA N1 Register 0x320C 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[30] PKHA N1 Register 0x19744 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[31] PKHA N1 Register 0x1A440 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[3] PKHA N1 Register 0x3E98 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[4] PKHA N1 Register 0x4B28 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[5] PKHA N1 Register 0x57BC 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[6] PKHA N1 Register 0x6454 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[7] PKHA N1 Register 0x70F0 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[8] PKHA N1 Register 0x7D90 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN1_[9] PKHA N1 Register 0x8A34 32 read-write n 0x0 0x0 PKHA_N1 N1 VALUE 0 32 read-write PKN2_0 PKHA N2 Register 0xD00 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_1 PKHA N2 Register 0xD04 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_10 PKHA N2 Register 0xD28 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_11 PKHA N2 Register 0xD2C 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_12 PKHA N2 Register 0xD30 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_13 PKHA N2 Register 0xD34 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_14 PKHA N2 Register 0xD38 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_15 PKHA N2 Register 0xD3C 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_16 PKHA N2 Register 0xD40 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_17 PKHA N2 Register 0xD44 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_18 PKHA N2 Register 0xD48 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_19 PKHA N2 Register 0xD4C 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_2 PKHA N2 Register 0xD08 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_20 PKHA N2 Register 0xD50 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_21 PKHA N2 Register 0xD54 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_22 PKHA N2 Register 0xD58 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_23 PKHA N2 Register 0xD5C 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_24 PKHA N2 Register 0xD60 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_25 PKHA N2 Register 0xD64 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_26 PKHA N2 Register 0xD68 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_27 PKHA N2 Register 0xD6C 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_28 PKHA N2 Register 0xD70 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_29 PKHA N2 Register 0xD74 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_3 PKHA N2 Register 0xD0C 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_30 PKHA N2 Register 0xD78 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_31 PKHA N2 Register 0xD7C 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_4 PKHA N2 Register 0xD10 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_5 PKHA N2 Register 0xD14 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_6 PKHA N2 Register 0xD18 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_7 PKHA N2 Register 0xD1C 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_8 PKHA N2 Register 0xD20 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_9 PKHA N2 Register 0xD24 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[0] PKHA N2 Register 0x1A00 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[10] PKHA N2 Register 0x9CDC 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[11] PKHA N2 Register 0xAA08 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[12] PKHA N2 Register 0xB738 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[13] PKHA N2 Register 0xC46C 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[14] PKHA N2 Register 0xD1A4 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[15] PKHA N2 Register 0xDEE0 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[16] PKHA N2 Register 0xEC20 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[17] PKHA N2 Register 0xF964 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[18] PKHA N2 Register 0x106AC 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[19] PKHA N2 Register 0x113F8 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[1] PKHA N2 Register 0x2704 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[20] PKHA N2 Register 0x12148 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[21] PKHA N2 Register 0x12E9C 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[22] PKHA N2 Register 0x13BF4 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[23] PKHA N2 Register 0x14950 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[24] PKHA N2 Register 0x156B0 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[25] PKHA N2 Register 0x16414 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[26] PKHA N2 Register 0x1717C 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[27] PKHA N2 Register 0x17EE8 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[28] PKHA N2 Register 0x18C58 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[29] PKHA N2 Register 0x199CC 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[2] PKHA N2 Register 0x340C 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[30] PKHA N2 Register 0x1A744 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[31] PKHA N2 Register 0x1B4C0 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[3] PKHA N2 Register 0x4118 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[4] PKHA N2 Register 0x4E28 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[5] PKHA N2 Register 0x5B3C 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[6] PKHA N2 Register 0x6854 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[7] PKHA N2 Register 0x7570 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[8] PKHA N2 Register 0x8290 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN2_[9] PKHA N2 Register 0x8FB4 32 read-write n 0x0 0x0 PKHA_N2 N2 VALUE 0 32 read-write PKN3_0 PKHA N3 Register 0xD80 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_1 PKHA N3 Register 0xD84 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_10 PKHA N3 Register 0xDA8 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_11 PKHA N3 Register 0xDAC 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_12 PKHA N3 Register 0xDB0 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_13 PKHA N3 Register 0xDB4 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_14 PKHA N3 Register 0xDB8 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_15 PKHA N3 Register 0xDBC 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_16 PKHA N3 Register 0xDC0 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_17 PKHA N3 Register 0xDC4 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_18 PKHA N3 Register 0xDC8 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_19 PKHA N3 Register 0xDCC 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_2 PKHA N3 Register 0xD88 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_20 PKHA N3 Register 0xDD0 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_21 PKHA N3 Register 0xDD4 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_22 PKHA N3 Register 0xDD8 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_23 PKHA N3 Register 0xDDC 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_24 PKHA N3 Register 0xDE0 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_25 PKHA N3 Register 0xDE4 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_26 PKHA N3 Register 0xDE8 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_27 PKHA N3 Register 0xDEC 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_28 PKHA N3 Register 0xDF0 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_29 PKHA N3 Register 0xDF4 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_3 PKHA N3 Register 0xD8C 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_30 PKHA N3 Register 0xDF8 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_31 PKHA N3 Register 0xDFC 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_4 PKHA N3 Register 0xD90 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_5 PKHA N3 Register 0xD94 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_6 PKHA N3 Register 0xD98 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_7 PKHA N3 Register 0xD9C 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_8 PKHA N3 Register 0xDA0 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_9 PKHA N3 Register 0xDA4 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[0] PKHA N3 Register 0x1B00 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[10] PKHA N3 Register 0xA2DC 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[11] PKHA N3 Register 0xB088 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[12] PKHA N3 Register 0xBE38 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[13] PKHA N3 Register 0xCBEC 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[14] PKHA N3 Register 0xD9A4 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[15] PKHA N3 Register 0xE760 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[16] PKHA N3 Register 0xF520 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[17] PKHA N3 Register 0x102E4 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[18] PKHA N3 Register 0x110AC 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[19] PKHA N3 Register 0x11E78 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[1] PKHA N3 Register 0x2884 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[20] PKHA N3 Register 0x12C48 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[21] PKHA N3 Register 0x13A1C 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[22] PKHA N3 Register 0x147F4 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[23] PKHA N3 Register 0x155D0 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[24] PKHA N3 Register 0x163B0 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[25] PKHA N3 Register 0x17194 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[26] PKHA N3 Register 0x17F7C 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[27] PKHA N3 Register 0x18D68 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[28] PKHA N3 Register 0x19B58 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[29] PKHA N3 Register 0x1A94C 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[2] PKHA N3 Register 0x360C 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[30] PKHA N3 Register 0x1B744 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[31] PKHA N3 Register 0x1C540 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[3] PKHA N3 Register 0x4398 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[4] PKHA N3 Register 0x5128 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[5] PKHA N3 Register 0x5EBC 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[6] PKHA N3 Register 0x6C54 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[7] PKHA N3 Register 0x79F0 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[8] PKHA N3 Register 0x8790 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKN3_[9] PKHA N3 Register 0x9534 32 read-write n 0x0 0x0 PKHA_N3 N3 VALUE 0 32 read-write PKNSZ PKHA N Size Register 0x490 32 read-write n 0x0 0x0 PKNSZ PKHA N Size 0 9 read-write SEMA4 Semaphore Register 0xF0 32 read-write n 0x0 0x0 DID Domain ID of Locked Semaphore Owner 0 4 read-only LK Semaphore Lock and Release Control 31 1 write-only LK_0 Semaphore release 0 LK_1 Semaphore lock 0x1 MSTRN Master Number of Locked Semaphore Owner 8 6 read-only NS Non Secure Attribute of the Locked Semaphore Owner 7 1 read-only NS_0 If semaphore is locked, owner is operating in secure mode 0 NS_1 If semaphore is locked, owner is operating in nonsecure mode 0x1 PR Privilege Attribute of Locked Semaphore Owner 6 1 read-only PR_0 If semaphore is locked, then owner is operating in user mode 0 PR_1 If semaphore is locked, then owner is operating in privileged mode 0x1 SMOWNR Semaphore Ownership Register 0xF4 32 read-only n 0x0 0x0 LOCK Semaphore Locked 0 1 read-only LOCK_0 Semaphore not locked 0 LOCK_1 Semaphore locked 0x1 NOWNER Semaphore Ownership 31 1 read-only NOWNER_0 The host making the current read access is the semaphore owner 0 NOWNER_1 The host making the current read access is NOT the semaphore owner 0x1 SR Status Register 0x14 32 read-write n 0x0 0x0 ASREIRQ AHB slave response error interrupt Request 3 1 read-write oneToClear ASREIRQ_0 no error 0 ASREIRQ_1 AHB slave response error detected 0x1 DBG Debug mode 17 1 read-only DBG_0 CAU3 is not in debug mode 0 DBG_1 CAU3 is in debug mode 0x1 DIADIRQ DMEM illegal access interrupt request 5 1 read-write oneToClear DIADIRQ_0 no illegal address 0 DIADIRQ_1 illegal address 0x1 IIADIRQ IMEM Illegal address interrupt request 4 1 read-write oneToClear IIADIRQ_0 no error 0 IIADIRQ_1 illegal IMEM address detected 0x1 ILLIRQ Illegal instruction interrupt request 1 1 read-write oneToClear ILLIRQ_0 no error 0 ILLIRQ_1 illegal instruction detected 0x1 MDISF Module disable flag 31 1 read-only MDISF_0 CCore is not in low power mode 0 MDISF_1 CCore is in low power mode 0x1 SVF Security violation flag 16 1 read-only SVF_0 SoC security violation is not asserted 0 SVF_1 SoC security violation was asserted 0x1 SVIRQ Security violation interrupt request 6 1 read-write oneToClear SVIRQ_0 No security violation 0 SVIRQ_1 Security violation 0x1 TCCFG Task completion configuration 24 3 read-only TCCFG_0 No action 0 TCCFG_1 Assert an interrupt request 0x1 TCCFG_2 Assert the Event Completion Signal 0x2 TCCFG_4 Issue a DMA request 0x4 TCIRQ Task completion with no error interrupt request 7 1 read-write oneToClear TCIRQ_0 Task not finished or finished with error 0 TCIRQ_1 Task execution finished with no error 0x1 TCSEIRQ Task completion with software error interrupt request 0 1 read-write oneToClear TCSEIRQ_0 Task not finished or finished with no software error 0 TCSEIRQ_1 Task execution finished with software error 0x1 TKCS Task completion status 8 4 read-only TKCS_0 Initialization RUN 0 TKCS_1 Running 0x1 TKCS_2 Debug Halted 0x2 TKCS_9 Stop - Error Free 0x9 TKCS_10 Stop - Error 0xA TKCS_14 Stop - Security Violation, assert security violation output signal and set SVIRQ 0xE TKCS_15 Stop - Security Violation and set SVIRQ 0xF STA Status Register 0x448 32 read-write n 0x0 0x0 DI Done Interrupt 16 1 read-write oneToClear EI Error Interrupt 20 1 read-only NOT_ERROR_INT Not Error. 0 ERROR_INT Error Interrupt. 0x1 PB PKHA Busy 6 1 read-only PKHA_IDLE PKHA Idle 0 PKHA_BUSY PKHA Busy. 0x1 PKO Public Key Operation is One 29 1 read-only PKP Public Key is Prime 28 1 read-only PKZ Public Key Operation is Zero 30 1 read-only CRC CRC CRC 0x0 0x0 0xC registers n CTRL CRC Control register 0x8 32 read-write n 0x0 0x0 FXOR Complement Read Of CRC Data Register 26 1 read-write FXOR_0 No XOR on reading. 0 FXOR_1 Invert or complement the read value of the CRC Data register. 0x1 TCRC TCRC 24 1 read-write TCRC_0 16-bit CRC protocol. 0 TCRC_1 32-bit CRC protocol. 0x1 TOT Type Of Transpose For Writes 30 2 read-write TOT_0 No transposition. 0 TOT_1 Bits in bytes are transposed bytes are not transposed. 0x1 TOT_2 Both bits in bytes and bytes are transposed. 0x2 TOT_3 Only bytes are transposed no bits in a byte are transposed. 0x3 TOTR Type Of Transpose For Read 28 2 read-write TOTR_0 No transposition. 0 TOTR_1 Bits in bytes are transposed bytes are not transposed. 0x1 TOTR_2 Both bits in bytes and bytes are transposed. 0x2 TOTR_3 Only bytes are transposed no bits in a byte are transposed. 0x3 WAS Write CRC Data Register As Seed 25 1 read-write WAS_0 Writes to the CRC data register are data values. 0 WAS_1 Writes to the CRC data register are seed values. 0x1 DATA CRC Data register 0x0 32 read-write n 0x0 0x0 HL CRC High Lower Byte 16 8 read-write HU CRC High Upper Byte 24 8 read-write LL CRC Low Lower Byte 0 8 read-write LU CRC Low Upper Byte 8 8 read-write GPOLY CRC Polynomial register 0x4 32 read-write n 0x0 0x0 HIGH High Polynominal Half-word 16 16 read-write LOW Low Polynominal Half-word 0 16 read-write DMA0 DMA DMA0 0x0 0x0 0x1200 registers n DMA0 1 DMA1 2 DMA2 3 DMA3 4 DMA4 5 DMA5 6 DMA6 7 DMA7 8 DMA8 9 DMA9 10 DMA10 11 DMA11 12 DMA12 13 DMA13 14 DMA14 15 DMA15 16 DMA0_Error 17 CDNE Clear DONE Status Bit Register 0x1C 8 write-only n 0x0 0x0 CADN Clears All DONE Bits 6 1 write-only CADN_0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field 0 CADN_1 Clears all bits in TCDn_CSR[DONE] 0x1 CDNE Clear DONE Bit 0 4 write-only NOP No Op enable 7 1 write-only NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 CEEI Clear Enable Error Interrupt Register 0x18 8 write-only n 0x0 0x0 CAEE Clear All Enable Error Interrupts 6 1 write-only CAEE_0 no description available 0 CAEE_1 no description available 0x1 CEEI Clear Enable Error Interrupt 0 4 write-only NOP No Op enable 7 1 write-only NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 CERQ Clear Enable Request Register 0x1A 8 write-only n 0x0 0x0 CAER Clear All Enable Requests 6 1 write-only CAER_0 no description available 0 CAER_1 no description available 0x1 CERQ Clear Enable Request 0 4 write-only NOP No Op enable 7 1 write-only NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 CERR Clear Error Register 0x1E 8 write-only n 0x0 0x0 CAEI Clear All Error Indicators 6 1 write-only CAEI_0 no description available 0 CAEI_1 no description available 0x1 CERR Clear Error Indicator 0 4 write-only NOP No Op enable 7 1 write-only NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 CINT Clear Interrupt Request Register 0x1F 8 write-only n 0x0 0x0 CAIR Clear All Interrupt Requests 6 1 write-only CAIR_0 no description available 0 CAIR_1 no description available 0x1 CINT Clear Interrupt Request 0 4 write-only NOP No Op enable 7 1 write-only NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 CR Control Register 0x0 32 read-write n 0x0 0x0 ACTIVE DMA Active Status 31 1 read-only ACTIVE_0 eDMA is idle. 0 ACTIVE_1 eDMA is executing a channel. 0x1 CLM Continuous Link Mode 6 1 read-write CLM_0 A minor loop channel link made to itself goes through channel arbitration before being activated again. 0 CLM_1 A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. 0x1 CX Cancel Transfer 17 1 read-write CX_0 Normal operation 0 CX_1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. 0x1 ECX Error Cancel Transfer 16 1 read-write ECX_0 Normal operation 0 ECX_1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt. 0x1 EDBG Enable Debug 1 1 read-write EDBG_0 no description available 0 EDBG_1 no description available 0x1 EMLM Enable Minor Loop Mapping 7 1 read-write EMLM_0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. 0 EMLM_1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. 0x1 ERCA Enable Round Robin Channel Arbitration 2 1 read-write ERCA_0 no description available 0 ERCA_1 no description available 0x1 HALT Halt DMA Operations 5 1 read-write HALT_0 Normal operation 0 HALT_1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. 0x1 HOE Halt On Error 4 1 read-write HOE_0 Normal operation 0 HOE_1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. 0x1 DCHPRI0 Channel Priority Register 0x103 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI1 Channel Priority Register 0x102 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI10 Channel Priority Register 0x109 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI11 Channel Priority Register 0x108 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI12 Channel Priority Register 0x10F 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI13 Channel Priority Register 0x10E 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI14 Channel Priority Register 0x10D 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI15 Channel Priority Register 0x10C 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI2 Channel Priority Register 0x101 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI3 Channel Priority Register 0x100 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI4 Channel Priority Register 0x107 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI5 Channel Priority Register 0x106 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI6 Channel Priority Register 0x105 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI7 Channel Priority Register 0x104 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI8 Channel Priority Register 0x10B 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 DCHPRI9 Channel Priority Register 0x10A 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable Preempt Ability. This field resets to 0. 6 1 read-write DPA_0 Channel n can suspend a lower priority channel. 0 DPA_1 Channel n cannot suspend any channel, regardless of channel priority. 0x1 ECP Enable Channel Preemption. This field resets to 0. 7 1 read-write ECP_0 Channel n cannot be suspended by a higher priority channel's service request. 0 ECP_1 Channel n can be temporarily suspended by the service request of a higher priority channel. 0x1 EARS Enable Asynchronous Request in Stop Register 0x44 32 read-write n 0x0 0x0 EDREQ_0 Enable asynchronous DMA request in stop mode for channel 0. 0 1 read-write EDREQ_0_0 Disable asynchronous DMA request for channel 0. 0 EDREQ_0_1 Enable asynchronous DMA request for channel 0. 0x1 EDREQ_1 Enable asynchronous DMA request in stop mode for channel 1. 1 1 read-write EDREQ_1_0 Disable asynchronous DMA request for channel 1 0 EDREQ_1_1 Enable asynchronous DMA request for channel 1. 0x1 EDREQ_10 Enable asynchronous DMA request in stop mode for channel 10 10 1 read-write EDREQ_10_0 Disable asynchronous DMA request for channel 10. 0 EDREQ_10_1 Enable asynchronous DMA request for channel 10. 0x1 EDREQ_11 Enable asynchronous DMA request in stop mode for channel 11 11 1 read-write EDREQ_11_0 Disable asynchronous DMA request for channel 11. 0 EDREQ_11_1 Enable asynchronous DMA request for channel 11. 0x1 EDREQ_12 Enable asynchronous DMA request in stop mode for channel 12 12 1 read-write EDREQ_12_0 Disable asynchronous DMA request for channel 12. 0 EDREQ_12_1 Enable asynchronous DMA request for channel 12. 0x1 EDREQ_13 Enable asynchronous DMA request in stop mode for channel 13 13 1 read-write EDREQ_13_0 Disable asynchronous DMA request for channel 13. 0 EDREQ_13_1 Enable asynchronous DMA request for channel 13. 0x1 EDREQ_14 Enable asynchronous DMA request in stop mode for channel 14 14 1 read-write EDREQ_14_0 Disable asynchronous DMA request for channel 14. 0 EDREQ_14_1 Enable asynchronous DMA request for channel 14. 0x1 EDREQ_15 Enable asynchronous DMA request in stop mode for channel 15 15 1 read-write EDREQ_15_0 Disable asynchronous DMA request for channel 15. 0 EDREQ_15_1 Enable asynchronous DMA request for channel 15. 0x1 EDREQ_2 Enable asynchronous DMA request in stop mode for channel 2. 2 1 read-write EDREQ_2_0 Disable asynchronous DMA request for channel 2. 0 EDREQ_2_1 Enable asynchronous DMA request for channel 2. 0x1 EDREQ_3 Enable asynchronous DMA request in stop mode for channel 3. 3 1 read-write EDREQ_3_0 Disable asynchronous DMA request for channel 3. 0 EDREQ_3_1 Enable asynchronous DMA request for channel 3. 0x1 EDREQ_4 Enable asynchronous DMA request in stop mode for channel 4 4 1 read-write EDREQ_4_0 Disable asynchronous DMA request for channel 4. 0 EDREQ_4_1 Enable asynchronous DMA request for channel 4. 0x1 EDREQ_5 Enable asynchronous DMA request in stop mode for channel 5 5 1 read-write EDREQ_5_0 Disable asynchronous DMA request for channel 5. 0 EDREQ_5_1 Enable asynchronous DMA request for channel 5. 0x1 EDREQ_6 Enable asynchronous DMA request in stop mode for channel 6 6 1 read-write EDREQ_6_0 Disable asynchronous DMA request for channel 6. 0 EDREQ_6_1 Enable asynchronous DMA request for channel 6. 0x1 EDREQ_7 Enable asynchronous DMA request in stop mode for channel 7 7 1 read-write EDREQ_7_0 Disable asynchronous DMA request for channel 7. 0 EDREQ_7_1 Enable asynchronous DMA request for channel 7. 0x1 EDREQ_8 Enable asynchronous DMA request in stop mode for channel 8 8 1 read-write EDREQ_8_0 Disable asynchronous DMA request for channel 8. 0 EDREQ_8_1 Enable asynchronous DMA request for channel 8. 0x1 EDREQ_9 Enable asynchronous DMA request in stop mode for channel 9 9 1 read-write EDREQ_9_0 Disable asynchronous DMA request for channel 9. 0 EDREQ_9_1 Enable asynchronous DMA request for channel 9. 0x1 EEI Enable Error Interrupt Register 0x14 32 read-write n 0x0 0x0 EEI0 Enable Error Interrupt 0 0 1 read-write EEI0_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI0_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI1 Enable Error Interrupt 1 1 1 read-write EEI1_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI1_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI10 Enable Error Interrupt 10 10 1 read-write EEI10_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI10_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI11 Enable Error Interrupt 11 11 1 read-write EEI11_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI11_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI12 Enable Error Interrupt 12 12 1 read-write EEI12_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI12_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI13 Enable Error Interrupt 13 13 1 read-write EEI13_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI13_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI14 Enable Error Interrupt 14 14 1 read-write EEI14_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI14_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI15 Enable Error Interrupt 15 15 1 read-write EEI15_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI15_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI2 Enable Error Interrupt 2 2 1 read-write EEI2_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI2_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI3 Enable Error Interrupt 3 3 1 read-write EEI3_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI3_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI4 Enable Error Interrupt 4 4 1 read-write EEI4_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI4_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI5 Enable Error Interrupt 5 5 1 read-write EEI5_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI5_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI6 Enable Error Interrupt 6 6 1 read-write EEI6_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI6_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI7 Enable Error Interrupt 7 7 1 read-write EEI7_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI7_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI8 Enable Error Interrupt 8 8 1 read-write EEI8_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI8_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 EEI9 Enable Error Interrupt 9 9 1 read-write EEI9_0 The error signal for corresponding channel does not generate an error interrupt 0 EEI9_1 The assertion of the error signal for corresponding channel generates an error interrupt request 0x1 ERQ Enable Request Register 0xC 32 read-write n 0x0 0x0 ERQ0 Enable DMA Request 0 0 1 read-write ERQ0_0 The DMA request signal for the corresponding channel is disabled 0 ERQ0_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ1 Enable DMA Request 1 1 1 read-write ERQ1_0 The DMA request signal for the corresponding channel is disabled 0 ERQ1_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ10 Enable DMA Request 10 10 1 read-write ERQ10_0 The DMA request signal for the corresponding channel is disabled 0 ERQ10_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ11 Enable DMA Request 11 11 1 read-write ERQ11_0 The DMA request signal for the corresponding channel is disabled 0 ERQ11_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ12 Enable DMA Request 12 12 1 read-write ERQ12_0 The DMA request signal for the corresponding channel is disabled 0 ERQ12_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ13 Enable DMA Request 13 13 1 read-write ERQ13_0 The DMA request signal for the corresponding channel is disabled 0 ERQ13_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ14 Enable DMA Request 14 14 1 read-write ERQ14_0 The DMA request signal for the corresponding channel is disabled 0 ERQ14_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ15 Enable DMA Request 15 15 1 read-write ERQ15_0 The DMA request signal for the corresponding channel is disabled 0 ERQ15_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ2 Enable DMA Request 2 2 1 read-write ERQ2_0 The DMA request signal for the corresponding channel is disabled 0 ERQ2_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ3 Enable DMA Request 3 3 1 read-write ERQ3_0 The DMA request signal for the corresponding channel is disabled 0 ERQ3_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ4 Enable DMA Request 4 4 1 read-write ERQ4_0 The DMA request signal for the corresponding channel is disabled 0 ERQ4_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ5 Enable DMA Request 5 5 1 read-write ERQ5_0 The DMA request signal for the corresponding channel is disabled 0 ERQ5_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ6 Enable DMA Request 6 6 1 read-write ERQ6_0 The DMA request signal for the corresponding channel is disabled 0 ERQ6_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ7 Enable DMA Request 7 7 1 read-write ERQ7_0 The DMA request signal for the corresponding channel is disabled 0 ERQ7_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ8 Enable DMA Request 8 8 1 read-write ERQ8_0 The DMA request signal for the corresponding channel is disabled 0 ERQ8_1 The DMA request signal for the corresponding channel is enabled 0x1 ERQ9 Enable DMA Request 9 9 1 read-write ERQ9_0 The DMA request signal for the corresponding channel is disabled 0 ERQ9_1 The DMA request signal for the corresponding channel is enabled 0x1 ERR Error Register 0x2C 32 read-write n 0x0 0x0 ERR0 Error In Channel 0 0 1 read-write oneToClear ERR0_0 An error in this channel has not occurred 0 ERR0_1 An error in this channel has occurred 0x1 ERR1 Error In Channel 1 1 1 read-write oneToClear ERR1_0 An error in this channel has not occurred 0 ERR1_1 An error in this channel has occurred 0x1 ERR10 Error In Channel 10 10 1 read-write oneToClear ERR10_0 An error in this channel has not occurred 0 ERR10_1 An error in this channel has occurred 0x1 ERR11 Error In Channel 11 11 1 read-write oneToClear ERR11_0 An error in this channel has not occurred 0 ERR11_1 An error in this channel has occurred 0x1 ERR12 Error In Channel 12 12 1 read-write oneToClear ERR12_0 An error in this channel has not occurred 0 ERR12_1 An error in this channel has occurred 0x1 ERR13 Error In Channel 13 13 1 read-write oneToClear ERR13_0 An error in this channel has not occurred 0 ERR13_1 An error in this channel has occurred 0x1 ERR14 Error In Channel 14 14 1 read-write oneToClear ERR14_0 An error in this channel has not occurred 0 ERR14_1 An error in this channel has occurred 0x1 ERR15 Error In Channel 15 15 1 read-write oneToClear ERR15_0 An error in this channel has not occurred 0 ERR15_1 An error in this channel has occurred 0x1 ERR2 Error In Channel 2 2 1 read-write oneToClear ERR2_0 An error in this channel has not occurred 0 ERR2_1 An error in this channel has occurred 0x1 ERR3 Error In Channel 3 3 1 read-write oneToClear ERR3_0 An error in this channel has not occurred 0 ERR3_1 An error in this channel has occurred 0x1 ERR4 Error In Channel 4 4 1 read-write oneToClear ERR4_0 An error in this channel has not occurred 0 ERR4_1 An error in this channel has occurred 0x1 ERR5 Error In Channel 5 5 1 read-write oneToClear ERR5_0 An error in this channel has not occurred 0 ERR5_1 An error in this channel has occurred 0x1 ERR6 Error In Channel 6 6 1 read-write oneToClear ERR6_0 An error in this channel has not occurred 0 ERR6_1 An error in this channel has occurred 0x1 ERR7 Error In Channel 7 7 1 read-write oneToClear ERR7_0 An error in this channel has not occurred 0 ERR7_1 An error in this channel has occurred 0x1 ERR8 Error In Channel 8 8 1 read-write oneToClear ERR8_0 An error in this channel has not occurred 0 ERR8_1 An error in this channel has occurred 0x1 ERR9 Error In Channel 9 9 1 read-write oneToClear ERR9_0 An error in this channel has not occurred 0 ERR9_1 An error in this channel has occurred 0x1 ES Error Status Register 0x4 32 read-only n 0x0 0x0 CPE Channel Priority Error 14 1 read-only CPE_0 No channel priority error 0 CPE_1 no description available 0x1 DAE Destination Address Error 5 1 read-only DAE_0 No destination address configuration error 0 DAE_1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. 0x1 DBE Destination Bus Error 0 1 read-only DBE_0 No destination bus error 0 DBE_1 The last recorded error was a bus error on a destination write 0x1 DOE Destination Offset Error 4 1 read-only DOE_0 No destination offset configuration error 0 DOE_1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. 0x1 ECX Transfer Canceled 16 1 read-only ECX_0 No canceled transfers 0 ECX_1 The last recorded entry was a canceled transfer by the error cancel transfer input 0x1 ERRCHN Error Channel Number or Canceled Channel Number 8 4 read-only NCE NBYTES/CITER Configuration Error 3 1 read-only NCE_0 No NBYTES/CITER configuration error 0 NCE_1 no description available 0x1 SAE Source Address Error 7 1 read-only SAE_0 No source address configuration error. 0 SAE_1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. 0x1 SBE Source Bus Error 1 1 read-only SBE_0 No source bus error 0 SBE_1 The last recorded error was a bus error on a source read 0x1 SGE Scatter/Gather Configuration Error 2 1 read-only SGE_0 No scatter/gather configuration error 0 SGE_1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. 0x1 SOE Source Offset Error 6 1 read-only SOE_0 No source offset configuration error 0 SOE_1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. 0x1 VLD VLD 31 1 read-only VLD_0 No ERR bits are set. 0 VLD_1 At least one ERR bit is set indicating a valid error exists that has not been cleared. 0x1 HRS Hardware Request Status Register 0x34 32 read-only n 0x0 0x0 HRS0 Hardware Request Status Channel 0 0 1 read-only HRS0_0 A hardware service request for channel 0 is not present 0 HRS0_1 A hardware service request for channel 0 is present 0x1 HRS1 Hardware Request Status Channel 1 1 1 read-only HRS1_0 A hardware service request for channel 1 is not present 0 HRS1_1 A hardware service request for channel 1 is present 0x1 HRS10 Hardware Request Status Channel 10 10 1 read-only HRS10_0 A hardware service request for channel 10 is not present 0 HRS10_1 A hardware service request for channel 10 is present 0x1 HRS11 Hardware Request Status Channel 11 11 1 read-only HRS11_0 A hardware service request for channel 11 is not present 0 HRS11_1 A hardware service request for channel 11 is present 0x1 HRS12 Hardware Request Status Channel 12 12 1 read-only HRS12_0 A hardware service request for channel 12 is not present 0 HRS12_1 A hardware service request for channel 12 is present 0x1 HRS13 Hardware Request Status Channel 13 13 1 read-only HRS13_0 A hardware service request for channel 13 is not present 0 HRS13_1 A hardware service request for channel 13 is present 0x1 HRS14 Hardware Request Status Channel 14 14 1 read-only HRS14_0 A hardware service request for channel 14 is not present 0 HRS14_1 A hardware service request for channel 14 is present 0x1 HRS15 Hardware Request Status Channel 15 15 1 read-only HRS15_0 A hardware service request for channel 15 is not present 0 HRS15_1 A hardware service request for channel 15 is present 0x1 HRS2 Hardware Request Status Channel 2 2 1 read-only HRS2_0 A hardware service request for channel 2 is not present 0 HRS2_1 A hardware service request for channel 2 is present 0x1 HRS3 Hardware Request Status Channel 3 3 1 read-only HRS3_0 A hardware service request for channel 3 is not present 0 HRS3_1 A hardware service request for channel 3 is present 0x1 HRS4 Hardware Request Status Channel 4 4 1 read-only HRS4_0 A hardware service request for channel 4 is not present 0 HRS4_1 A hardware service request for channel 4 is present 0x1 HRS5 Hardware Request Status Channel 5 5 1 read-only HRS5_0 A hardware service request for channel 5 is not present 0 HRS5_1 A hardware service request for channel 5 is present 0x1 HRS6 Hardware Request Status Channel 6 6 1 read-only HRS6_0 A hardware service request for channel 6 is not present 0 HRS6_1 A hardware service request for channel 6 is present 0x1 HRS7 Hardware Request Status Channel 7 7 1 read-only HRS7_0 A hardware service request for channel 7 is not present 0 HRS7_1 A hardware service request for channel 7 is present 0x1 HRS8 Hardware Request Status Channel 8 8 1 read-only HRS8_0 A hardware service request for channel 8 is not present 0 HRS8_1 A hardware service request for channel 8 is present 0x1 HRS9 Hardware Request Status Channel 9 9 1 read-only HRS9_0 A hardware service request for channel 9 is not present 0 HRS9_1 A hardware service request for channel 9 is present 0x1 INT Interrupt Request Register 0x24 32 read-write n 0x0 0x0 INT0 Interrupt Request 0 0 1 read-write oneToClear INT0_0 The interrupt request for corresponding channel is cleared 0 INT0_1 The interrupt request for corresponding channel is active 0x1 INT1 Interrupt Request 1 1 1 read-write oneToClear INT1_0 The interrupt request for corresponding channel is cleared 0 INT1_1 The interrupt request for corresponding channel is active 0x1 INT10 Interrupt Request 10 10 1 read-write oneToClear INT10_0 The interrupt request for corresponding channel is cleared 0 INT10_1 The interrupt request for corresponding channel is active 0x1 INT11 Interrupt Request 11 11 1 read-write oneToClear INT11_0 The interrupt request for corresponding channel is cleared 0 INT11_1 The interrupt request for corresponding channel is active 0x1 INT12 Interrupt Request 12 12 1 read-write oneToClear INT12_0 The interrupt request for corresponding channel is cleared 0 INT12_1 The interrupt request for corresponding channel is active 0x1 INT13 Interrupt Request 13 13 1 read-write oneToClear INT13_0 The interrupt request for corresponding channel is cleared 0 INT13_1 The interrupt request for corresponding channel is active 0x1 INT14 Interrupt Request 14 14 1 read-write oneToClear INT14_0 The interrupt request for corresponding channel is cleared 0 INT14_1 The interrupt request for corresponding channel is active 0x1 INT15 Interrupt Request 15 15 1 read-write oneToClear INT15_0 The interrupt request for corresponding channel is cleared 0 INT15_1 The interrupt request for corresponding channel is active 0x1 INT2 Interrupt Request 2 2 1 read-write oneToClear INT2_0 The interrupt request for corresponding channel is cleared 0 INT2_1 The interrupt request for corresponding channel is active 0x1 INT3 Interrupt Request 3 3 1 read-write oneToClear INT3_0 The interrupt request for corresponding channel is cleared 0 INT3_1 The interrupt request for corresponding channel is active 0x1 INT4 Interrupt Request 4 4 1 read-write oneToClear INT4_0 The interrupt request for corresponding channel is cleared 0 INT4_1 The interrupt request for corresponding channel is active 0x1 INT5 Interrupt Request 5 5 1 read-write oneToClear INT5_0 The interrupt request for corresponding channel is cleared 0 INT5_1 The interrupt request for corresponding channel is active 0x1 INT6 Interrupt Request 6 6 1 read-write oneToClear INT6_0 The interrupt request for corresponding channel is cleared 0 INT6_1 The interrupt request for corresponding channel is active 0x1 INT7 Interrupt Request 7 7 1 read-write oneToClear INT7_0 The interrupt request for corresponding channel is cleared 0 INT7_1 The interrupt request for corresponding channel is active 0x1 INT8 Interrupt Request 8 8 1 read-write oneToClear INT8_0 The interrupt request for corresponding channel is cleared 0 INT8_1 The interrupt request for corresponding channel is active 0x1 INT9 Interrupt Request 9 9 1 read-write oneToClear INT9_0 The interrupt request for corresponding channel is cleared 0 INT9_1 The interrupt request for corresponding channel is active 0x1 SEEI Set Enable Error Interrupt Register 0x19 8 write-only n 0x0 0x0 NOP No Op enable 7 1 write-only NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 SAEE Sets All Enable Error Interrupts 6 1 write-only SAEE_0 no description available 0 SAEE_1 no description available 0x1 SEEI Set Enable Error Interrupt 0 4 write-only SERQ Set Enable Request Register 0x1B 8 write-only n 0x0 0x0 NOP No Op enable 7 1 write-only NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 SAER Set All Enable Requests 6 1 write-only SAER_0 no description available 0 SAER_1 no description available 0x1 SERQ Set Enable Request 0 4 write-only SSRT Set START Bit Register 0x1D 8 write-only n 0x0 0x0 NOP No Op enable 7 1 write-only NOP_0 Normal operation 0 NOP_1 No operation, ignore the other bits in this register 0x1 SAST Set All START Bits (activates all channels) 6 1 write-only SAST_0 Set only the TCDn_CSR[START] bit specified in the SSRT field 0 SAST_1 Set all bits in TCDn_CSR[START] 0x1 SSRT Set START Bit 0 4 write-only TCD0_ATTR TCD Transfer Attributes 0x1006 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 no description available 0x4 SSIZE_5 no description available 0x5 TCD0_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x101E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD0_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x101E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Link Channel Number 9 4 read-write TCD0_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1016 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD0_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1016 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Minor Loop Link Channel Number 9 4 read-write TCD0_CSR TCD Control and Status 0x101C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 DONE Channel Done 7 1 read-write zeroToClear DREQ Disable Request 3 1 read-write DREQ_0 no description available 0 DREQ_1 no description available 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 MAJORLINKCH Major Loop Link Channel Number 8 4 read-write START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 TCD0_DADDR TCD Destination Address 0x1010 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD0_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1018 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD0_DOFF TCD Signed Destination Address Offset 0x1014 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD0_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1008 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD0_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1008 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD0_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1008 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD0_SADDR TCD Source Address 0x1000 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD0_SLAST TCD Last Source Address Adjustment 0x100C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD0_SOFF TCD Signed Source Address Offset 0x1004 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD10_ATTR TCD Transfer Attributes 0x1146 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 no description available 0x4 SSIZE_5 no description available 0x5 TCD10_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x115E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD10_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x115E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Link Channel Number 9 4 read-write TCD10_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1156 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD10_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1156 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Minor Loop Link Channel Number 9 4 read-write TCD10_CSR TCD Control and Status 0x115C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 DONE Channel Done 7 1 read-write zeroToClear DREQ Disable Request 3 1 read-write DREQ_0 no description available 0 DREQ_1 no description available 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 MAJORLINKCH Major Loop Link Channel Number 8 4 read-write START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 TCD10_DADDR TCD Destination Address 0x1150 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD10_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1158 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD10_DOFF TCD Signed Destination Address Offset 0x1154 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD10_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1148 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD10_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1148 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD10_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1148 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD10_SADDR TCD Source Address 0x1140 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD10_SLAST TCD Last Source Address Adjustment 0x114C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD10_SOFF TCD Signed Source Address Offset 0x1144 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD11_ATTR TCD Transfer Attributes 0x1166 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 no description available 0x4 SSIZE_5 no description available 0x5 TCD11_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x117E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD11_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x117E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Link Channel Number 9 4 read-write TCD11_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1176 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD11_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1176 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Minor Loop Link Channel Number 9 4 read-write TCD11_CSR TCD Control and Status 0x117C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 DONE Channel Done 7 1 read-write zeroToClear DREQ Disable Request 3 1 read-write DREQ_0 no description available 0 DREQ_1 no description available 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 MAJORLINKCH Major Loop Link Channel Number 8 4 read-write START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 TCD11_DADDR TCD Destination Address 0x1170 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD11_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1178 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD11_DOFF TCD Signed Destination Address Offset 0x1174 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD11_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1168 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD11_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1168 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD11_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1168 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD11_SADDR TCD Source Address 0x1160 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD11_SLAST TCD Last Source Address Adjustment 0x116C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD11_SOFF TCD Signed Source Address Offset 0x1164 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD12_ATTR TCD Transfer Attributes 0x1186 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 no description available 0x4 SSIZE_5 no description available 0x5 TCD12_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x119E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD12_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x119E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Link Channel Number 9 4 read-write TCD12_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1196 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD12_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1196 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Minor Loop Link Channel Number 9 4 read-write TCD12_CSR TCD Control and Status 0x119C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 DONE Channel Done 7 1 read-write zeroToClear DREQ Disable Request 3 1 read-write DREQ_0 no description available 0 DREQ_1 no description available 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 MAJORLINKCH Major Loop Link Channel Number 8 4 read-write START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 TCD12_DADDR TCD Destination Address 0x1190 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD12_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1198 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD12_DOFF TCD Signed Destination Address Offset 0x1194 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD12_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1188 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD12_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1188 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD12_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1188 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD12_SADDR TCD Source Address 0x1180 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD12_SLAST TCD Last Source Address Adjustment 0x118C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD12_SOFF TCD Signed Source Address Offset 0x1184 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD13_ATTR TCD Transfer Attributes 0x11A6 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 no description available 0x4 SSIZE_5 no description available 0x5 TCD13_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x11BE 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD13_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x11BE 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Link Channel Number 9 4 read-write TCD13_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x11B6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD13_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x11B6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Minor Loop Link Channel Number 9 4 read-write TCD13_CSR TCD Control and Status 0x11BC 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 DONE Channel Done 7 1 read-write zeroToClear DREQ Disable Request 3 1 read-write DREQ_0 no description available 0 DREQ_1 no description available 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 MAJORLINKCH Major Loop Link Channel Number 8 4 read-write START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 TCD13_DADDR TCD Destination Address 0x11B0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD13_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x11B8 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD13_DOFF TCD Signed Destination Address Offset 0x11B4 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD13_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x11A8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD13_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x11A8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD13_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x11A8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD13_SADDR TCD Source Address 0x11A0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD13_SLAST TCD Last Source Address Adjustment 0x11AC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD13_SOFF TCD Signed Source Address Offset 0x11A4 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD14_ATTR TCD Transfer Attributes 0x11C6 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 no description available 0x4 SSIZE_5 no description available 0x5 TCD14_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x11DE 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD14_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x11DE 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Link Channel Number 9 4 read-write TCD14_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x11D6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD14_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x11D6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Minor Loop Link Channel Number 9 4 read-write TCD14_CSR TCD Control and Status 0x11DC 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 DONE Channel Done 7 1 read-write zeroToClear DREQ Disable Request 3 1 read-write DREQ_0 no description available 0 DREQ_1 no description available 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 MAJORLINKCH Major Loop Link Channel Number 8 4 read-write START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 TCD14_DADDR TCD Destination Address 0x11D0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD14_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x11D8 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD14_DOFF TCD Signed Destination Address Offset 0x11D4 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD14_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x11C8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD14_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x11C8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD14_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x11C8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD14_SADDR TCD Source Address 0x11C0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD14_SLAST TCD Last Source Address Adjustment 0x11CC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD14_SOFF TCD Signed Source Address Offset 0x11C4 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD15_ATTR TCD Transfer Attributes 0x11E6 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 no description available 0x4 SSIZE_5 no description available 0x5 TCD15_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x11FE 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD15_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x11FE 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Link Channel Number 9 4 read-write TCD15_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x11F6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD15_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x11F6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Minor Loop Link Channel Number 9 4 read-write TCD15_CSR TCD Control and Status 0x11FC 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 DONE Channel Done 7 1 read-write zeroToClear DREQ Disable Request 3 1 read-write DREQ_0 no description available 0 DREQ_1 no description available 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 MAJORLINKCH Major Loop Link Channel Number 8 4 read-write START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 TCD15_DADDR TCD Destination Address 0x11F0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD15_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x11F8 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD15_DOFF TCD Signed Destination Address Offset 0x11F4 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD15_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x11E8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD15_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x11E8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD15_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x11E8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD15_SADDR TCD Source Address 0x11E0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD15_SLAST TCD Last Source Address Adjustment 0x11EC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD15_SOFF TCD Signed Source Address Offset 0x11E4 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD1_ATTR TCD Transfer Attributes 0x1026 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 no description available 0x4 SSIZE_5 no description available 0x5 TCD1_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x103E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD1_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x103E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Link Channel Number 9 4 read-write TCD1_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1036 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD1_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1036 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Minor Loop Link Channel Number 9 4 read-write TCD1_CSR TCD Control and Status 0x103C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 DONE Channel Done 7 1 read-write zeroToClear DREQ Disable Request 3 1 read-write DREQ_0 no description available 0 DREQ_1 no description available 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 MAJORLINKCH Major Loop Link Channel Number 8 4 read-write START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 TCD1_DADDR TCD Destination Address 0x1030 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD1_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1038 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD1_DOFF TCD Signed Destination Address Offset 0x1034 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD1_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1028 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD1_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1028 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD1_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1028 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD1_SADDR TCD Source Address 0x1020 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD1_SLAST TCD Last Source Address Adjustment 0x102C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD1_SOFF TCD Signed Source Address Offset 0x1024 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD2_ATTR TCD Transfer Attributes 0x1046 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 no description available 0x4 SSIZE_5 no description available 0x5 TCD2_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x105E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD2_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x105E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Link Channel Number 9 4 read-write TCD2_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1056 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD2_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1056 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Minor Loop Link Channel Number 9 4 read-write TCD2_CSR TCD Control and Status 0x105C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 DONE Channel Done 7 1 read-write zeroToClear DREQ Disable Request 3 1 read-write DREQ_0 no description available 0 DREQ_1 no description available 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 MAJORLINKCH Major Loop Link Channel Number 8 4 read-write START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 TCD2_DADDR TCD Destination Address 0x1050 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD2_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1058 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD2_DOFF TCD Signed Destination Address Offset 0x1054 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD2_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1048 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD2_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1048 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD2_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1048 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD2_SADDR TCD Source Address 0x1040 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD2_SLAST TCD Last Source Address Adjustment 0x104C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD2_SOFF TCD Signed Source Address Offset 0x1044 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD3_ATTR TCD Transfer Attributes 0x1066 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 no description available 0x4 SSIZE_5 no description available 0x5 TCD3_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x107E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD3_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x107E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Link Channel Number 9 4 read-write TCD3_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1076 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD3_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1076 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Minor Loop Link Channel Number 9 4 read-write TCD3_CSR TCD Control and Status 0x107C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 DONE Channel Done 7 1 read-write zeroToClear DREQ Disable Request 3 1 read-write DREQ_0 no description available 0 DREQ_1 no description available 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 MAJORLINKCH Major Loop Link Channel Number 8 4 read-write START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 TCD3_DADDR TCD Destination Address 0x1070 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD3_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1078 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD3_DOFF TCD Signed Destination Address Offset 0x1074 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD3_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1068 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD3_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1068 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD3_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1068 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD3_SADDR TCD Source Address 0x1060 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD3_SLAST TCD Last Source Address Adjustment 0x106C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD3_SOFF TCD Signed Source Address Offset 0x1064 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD4_ATTR TCD Transfer Attributes 0x1086 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 no description available 0x4 SSIZE_5 no description available 0x5 TCD4_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x109E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD4_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x109E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Link Channel Number 9 4 read-write TCD4_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1096 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD4_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1096 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Minor Loop Link Channel Number 9 4 read-write TCD4_CSR TCD Control and Status 0x109C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 DONE Channel Done 7 1 read-write zeroToClear DREQ Disable Request 3 1 read-write DREQ_0 no description available 0 DREQ_1 no description available 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 MAJORLINKCH Major Loop Link Channel Number 8 4 read-write START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 TCD4_DADDR TCD Destination Address 0x1090 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD4_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1098 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD4_DOFF TCD Signed Destination Address Offset 0x1094 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD4_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1088 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD4_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1088 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD4_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1088 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD4_SADDR TCD Source Address 0x1080 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD4_SLAST TCD Last Source Address Adjustment 0x108C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD4_SOFF TCD Signed Source Address Offset 0x1084 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD5_ATTR TCD Transfer Attributes 0x10A6 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 no description available 0x4 SSIZE_5 no description available 0x5 TCD5_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x10BE 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD5_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x10BE 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Link Channel Number 9 4 read-write TCD5_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x10B6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD5_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x10B6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Minor Loop Link Channel Number 9 4 read-write TCD5_CSR TCD Control and Status 0x10BC 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 DONE Channel Done 7 1 read-write zeroToClear DREQ Disable Request 3 1 read-write DREQ_0 no description available 0 DREQ_1 no description available 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 MAJORLINKCH Major Loop Link Channel Number 8 4 read-write START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 TCD5_DADDR TCD Destination Address 0x10B0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD5_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x10B8 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD5_DOFF TCD Signed Destination Address Offset 0x10B4 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD5_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x10A8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD5_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x10A8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD5_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x10A8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD5_SADDR TCD Source Address 0x10A0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD5_SLAST TCD Last Source Address Adjustment 0x10AC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD5_SOFF TCD Signed Source Address Offset 0x10A4 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD6_ATTR TCD Transfer Attributes 0x10C6 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 no description available 0x4 SSIZE_5 no description available 0x5 TCD6_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x10DE 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD6_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x10DE 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Link Channel Number 9 4 read-write TCD6_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x10D6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD6_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x10D6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Minor Loop Link Channel Number 9 4 read-write TCD6_CSR TCD Control and Status 0x10DC 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 DONE Channel Done 7 1 read-write zeroToClear DREQ Disable Request 3 1 read-write DREQ_0 no description available 0 DREQ_1 no description available 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 MAJORLINKCH Major Loop Link Channel Number 8 4 read-write START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 TCD6_DADDR TCD Destination Address 0x10D0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD6_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x10D8 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD6_DOFF TCD Signed Destination Address Offset 0x10D4 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD6_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x10C8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD6_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x10C8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD6_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x10C8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD6_SADDR TCD Source Address 0x10C0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD6_SLAST TCD Last Source Address Adjustment 0x10CC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD6_SOFF TCD Signed Source Address Offset 0x10C4 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD7_ATTR TCD Transfer Attributes 0x10E6 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 no description available 0x4 SSIZE_5 no description available 0x5 TCD7_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x10FE 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD7_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x10FE 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Link Channel Number 9 4 read-write TCD7_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x10F6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD7_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x10F6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Minor Loop Link Channel Number 9 4 read-write TCD7_CSR TCD Control and Status 0x10FC 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 DONE Channel Done 7 1 read-write zeroToClear DREQ Disable Request 3 1 read-write DREQ_0 no description available 0 DREQ_1 no description available 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 MAJORLINKCH Major Loop Link Channel Number 8 4 read-write START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 TCD7_DADDR TCD Destination Address 0x10F0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD7_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x10F8 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD7_DOFF TCD Signed Destination Address Offset 0x10F4 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD7_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x10E8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD7_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x10E8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD7_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x10E8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD7_SADDR TCD Source Address 0x10E0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD7_SLAST TCD Last Source Address Adjustment 0x10EC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD7_SOFF TCD Signed Source Address Offset 0x10E4 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD8_ATTR TCD Transfer Attributes 0x1106 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 no description available 0x4 SSIZE_5 no description available 0x5 TCD8_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x111E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD8_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x111E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Link Channel Number 9 4 read-write TCD8_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1116 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD8_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1116 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Minor Loop Link Channel Number 9 4 read-write TCD8_CSR TCD Control and Status 0x111C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 DONE Channel Done 7 1 read-write zeroToClear DREQ Disable Request 3 1 read-write DREQ_0 no description available 0 DREQ_1 no description available 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 MAJORLINKCH Major Loop Link Channel Number 8 4 read-write START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 TCD8_DADDR TCD Destination Address 0x1110 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD8_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1118 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD8_DOFF TCD Signed Destination Address Offset 0x1114 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD8_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1108 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD8_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1108 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD8_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1108 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD8_SADDR TCD Source Address 0x1100 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD8_SLAST TCD Last Source Address Adjustment 0x110C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD8_SOFF TCD Signed Source Address Offset 0x1104 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write TCD9_ATTR TCD Transfer Attributes 0x1126 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination data transfer size 0 3 read-write SMOD Source Address Modulo 11 5 read-write SMOD_0 Source address modulo feature is disabled 0 SMOD_1 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x1 SMOD_2 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x2 SMOD_3 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x3 SMOD_4 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x4 SMOD_5 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x5 SMOD_6 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x6 SMOD_7 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x7 SMOD_8 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x8 SMOD_9 This value defines a specific address range specified to be the value after SADDR + SOFF calculation is performed on the original register value. Setting this field provides the ability to implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. The value programmed into this field specifies the number of lower address bits allowed to change. For a circular queue application, the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD function constraining the addresses to a 0-modulo-size range. 0x9 SSIZE Source data transfer size 8 3 read-write SSIZE_0 8-bit 0 SSIZE_1 16-bit 0x1 SSIZE_2 32-bit 0x2 SSIZE_4 no description available 0x4 SSIZE_5 no description available 0x5 TCD9_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_BITER_ELINK 0x113E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD9_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_BITER_ELINK 0x113E 16 read-write n 0x0 0x0 BITER Starting major iteration count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Link Channel Number 9 4 read-write TCD9_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) TCD_CITER_ELINK 0x1136 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 TCD9_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) TCD_CITER_ELINK 0x1136 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write ELINK_0 The channel-to-channel linking is disabled 0 ELINK_1 The channel-to-channel linking is enabled 0x1 LINKCH Minor Loop Link Channel Number 9 4 read-write TCD9_CSR TCD Control and Status 0x113C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-only BWC Bandwidth Control 14 2 read-write BWC_0 No eDMA engine stalls. 0 BWC_2 eDMA engine stalls for 4 cycles after each R/W. 0x2 BWC_3 eDMA engine stalls for 8 cycles after each R/W. 0x3 DONE Channel Done 7 1 read-write zeroToClear DREQ Disable Request 3 1 read-write DREQ_0 no description available 0 DREQ_1 no description available 0x1 ESG Enable Scatter/Gather Processing 4 1 read-write ESG_0 The current channel's TCD is normal format. 0 ESG_1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. 0x1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write INTHALF_0 The half-point interrupt is disabled. 0 INTHALF_1 The half-point interrupt is enabled. 0x1 INTMAJOR Enable an interrupt when major iteration count completes. 1 1 read-write INTMAJOR_0 The end-of-major loop interrupt is disabled. 0 INTMAJOR_1 The end-of-major loop interrupt is enabled. 0x1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write MAJORELINK_0 The channel-to-channel linking is disabled. 0 MAJORELINK_1 The channel-to-channel linking is enabled. 0x1 MAJORLINKCH Major Loop Link Channel Number 8 4 read-write START Channel Start 0 1 read-write START_0 The channel is not explicitly started. 0 START_1 The channel is explicitly started via a software initiated service request. 0x1 TCD9_DADDR TCD Destination Address 0x1130 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD9_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1138 32 read-write n 0x0 0x0 DLASTSGA DLASTSGA 0 32 read-write TCD9_DOFF TCD Signed Destination Address Offset 0x1134 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD9_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Mapping Disabled) TCD_NBYTES 0x1128 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD9_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) TCD_NBYTES 0x1128 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD9_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) TCD_NBYTES 0x1128 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write DMLOE_0 The minor loop offset is not applied to the DADDR 0 DMLOE_1 The minor loop offset is applied to the DADDR 0x1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write SMLOE_0 The minor loop offset is not applied to the SADDR 0 SMLOE_1 The minor loop offset is applied to the SADDR 0x1 TCD9_SADDR TCD Source Address 0x1120 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD9_SLAST TCD Last Source Address Adjustment 0x112C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD9_SOFF TCD Signed Source Address Offset 0x1124 16 read-write n 0x0 0x0 SOFF Source address signed offset 0 16 read-write DMAMUX0 DMA_CH_MUX DMAMUX0 0x0 0x0 0x40 registers n CHCFG0 Channel 0 Configuration Register 0x0 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG1 Channel 0 Configuration Register 0x4 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG10 Channel 0 Configuration Register 0x28 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG11 Channel 0 Configuration Register 0x2C 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG12 Channel 0 Configuration Register 0x30 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG13 Channel 0 Configuration Register 0x34 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG14 Channel 0 Configuration Register 0x38 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG15 Channel 0 Configuration Register 0x3C 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG2 Channel 0 Configuration Register 0x8 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG3 Channel 0 Configuration Register 0xC 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG4 Channel 0 Configuration Register 0x10 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG5 Channel 0 Configuration Register 0x14 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG6 Channel 0 Configuration Register 0x18 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG7 Channel 0 Configuration Register 0x1C 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG8 Channel 0 Configuration Register 0x20 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG9 Channel 0 Configuration Register 0x24 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG[0] Channel 0 Configuration Register 0x0 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG[10] Channel 0 Configuration Register 0xDC 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG[11] Channel 0 Configuration Register 0x108 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG[12] Channel 0 Configuration Register 0x138 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG[13] Channel 0 Configuration Register 0x16C 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG[14] Channel 0 Configuration Register 0x1A4 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG[15] Channel 0 Configuration Register 0x1E0 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG[1] Channel 0 Configuration Register 0x4 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG[2] Channel 0 Configuration Register 0xC 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG[3] Channel 0 Configuration Register 0x18 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG[4] Channel 0 Configuration Register 0x28 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG[5] Channel 0 Configuration Register 0x3C 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG[6] Channel 0 Configuration Register 0x54 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG[7] Channel 0 Configuration Register 0x70 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG[8] Channel 0 Configuration Register 0x90 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 CHCFG[9] Channel 0 Configuration Register 0xB4 32 read-write n 0x0 0x0 A_ON DMA Channel Always Enable 29 1 read-write A_ON_0 DMA Channel Always ON function is disabled 0 A_ON_1 DMA Channel Always ON function is enabled 0x1 ENBL DMA Mux Channel Enable 31 1 read-write ENBL_0 DMA Mux channel is disabled 0 ENBL_1 DMA Mux channel is enabled 0x1 SOURCE DMA Channel Source (Slot Number) 0 6 read-write TRIG DMA Channel Trigger Enable 30 1 read-write TRIG_0 Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 0 TRIG_1 Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. 0x1 EMVSIM0 EMVSIM EMVSIM0 0x0 0x0 0x4C registers n EMVSIM0 34 BGT_VAL Block Guard Time Value Register 0x40 32 read-write n 0x0 0x0 BGT Block Guard Time Value 0 16 read-write BWT_VAL Block Wait Time Value Register 0x3C 32 read-write n 0x0 0x0 BWT Block Wait Time Value 0 32 read-write CLKCFG Clock Configuration Register 0x8 32 read-write n 0x0 0x0 CLK_PRSC Clock Prescaler Value 0 8 read-write CLK_PRSC_2 Divide by 2 0x2 GPCNT0_CLK_SEL General Purpose Counter 0 Clock Select 10 2 read-write GPCNT0_CLK_SEL_0 Disabled / Reset (default) 0 GPCNT0_CLK_SEL_1 Card Clock 0x1 GPCNT0_CLK_SEL_2 Receive Clock 0x2 GPCNT0_CLK_SEL_3 ETU Clock (transmit clock) 0x3 GPCNT1_CLK_SEL General Purpose Counter 1 Clock Select 8 2 read-write GPCNT1_CLK_SEL_0 Disabled / Reset (default) 0 GPCNT1_CLK_SEL_1 Card Clock 0x1 GPCNT1_CLK_SEL_2 Receive Clock 0x2 GPCNT1_CLK_SEL_3 ETU Clock (transmit clock) 0x3 CTRL Control Register 0x10 32 read-write n 0x0 0x0 ANACK Auto NACK Enable 2 1 read-write ANACK_0 NACK generation on errors disabled 0 ANACK_1 NACK generation on errors enabled (default) 0x1 BWT_EN Block Wait Time Counter Enable 31 1 read-write BWT_EN_0 Disable BWT, BGT Counters (default) 0 BWT_EN_1 Enable BWT, BGT Counters 0x1 CRC_EN CRC Enable 29 1 read-write CRC_EN_0 16-bit Cyclic Redundancy Checking disabled (default) 0 CRC_EN_1 16-bit Cyclic Redundancy Checking enabled 0x1 CRC_IN_FLIP CRC Input Byte's Bit Reversal or Flip Control 26 1 read-write CRC_IN_FLIP_0 Bits in the input byte will not be reversed (i.e. 7:0 will remain 7:0) before the CRC calculation (default) 0 CRC_IN_FLIP_1 Bits in the input byte will be reversed (i.e. 7:0 will become 0:7) before CRC calculation 0x1 CRC_OUT_FLIP CRC Output Value Bit Reversal or Flip 25 1 read-write CRC_OUT_FLIP_0 Bits within the CRC output bytes will not be reversed i.e. 15:0 will remain 15:0 (default) 0 CRC_OUT_FLIP_1 Bits within the CRC output bytes will be reversed i.e. 15:0 will become {8:15,0:7} 0x1 CWT_EN Character Wait Time Counter Enable 27 1 read-write CWT_EN_0 Character Wait time Counter is disabled (default) 0 CWT_EN_1 Character Wait time counter is enabled 0x1 DOZE_EN Doze Enable 12 1 read-write DOZE_EN_0 DOZE instruction will gate all internal EMV SIM clocks as well as the Smart Card clock when the transmit FIFO is empty (default) 0 DOZE_EN_1 DOZE instruction has no effect on EMV SIM module 0x1 FLSH_RX Flush Receiver Bit 8 1 write-only FLSH_RX_0 EMV SIM Receiver normal operation (default) 0 FLSH_RX_1 EMV SIM Receiver held in Reset 0x1 FLSH_TX Flush Transmitter Bit 9 1 write-only FLSH_TX_0 EMV SIM Transmitter normal operation (default) 0 FLSH_TX_1 EMV SIM Transmitter held in Reset 0x1 IC Inverse Convention 0 1 read-write IC_0 Direction convention transfers enabled (default) 0 IC_1 Inverse convention transfers enabled 0x1 ICM Initial Character Mode 1 1 read-write ICM_0 Initial Character Mode disabled 0 ICM_1 Initial Character Mode enabled (default) 0x1 INV_CRC_VAL Invert bits in the CRC Output Value 24 1 read-write INV_CRC_VAL_0 Bits in CRC Output value will not be inverted. 0 INV_CRC_VAL_1 Bits in CRC Output value will be inverted. (default) 0x1 KILL_CLOCKS Kill all internal clocks 11 1 read-write KILL_CLOCKS_0 EMV SIM input clock enabled (default) 0 KILL_CLOCKS_1 EMV SIM input clock is disabled 0x1 LRC_EN LRC Enable 28 1 read-write LRC_EN_0 8-bit Linear Redundancy Checking disabled (default) 0 LRC_EN_1 8-bit Linear Redundancy Checking enabled 0x1 ONACK Overrun NACK Enable 3 1 read-write ONACK_0 NACK generation on overrun is disabled (default) 0 ONACK_1 NACK generation on overrun is enabled 0x1 RCVR_11 Receiver 11 ETU Mode Enable 18 1 read-write RCVR_11_0 Receiver configured for 12 ETU operation mode (default) 0 RCVR_11_1 Receiver configured for 11 ETU operation mode 0x1 RCV_EN Receiver Enable 16 1 read-write RCV_EN_0 EMV SIM Receiver disabled (default) 0 RCV_EN_1 EMV SIM Receiver enabled 0x1 RX_DMA_EN Receive DMA Enable 19 1 read-write RX_DMA_EN_0 No DMA Read Request asserted for Receiver (default) 0 RX_DMA_EN_1 DMA Read Request asserted for Receiver 0x1 STOP_EN STOP Enable 13 1 read-write STOP_EN_0 STOP instruction shuts down all EMV SIM clocks (default) 0 STOP_EN_1 STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card) 0x1 SW_RST Software Reset Bit 10 1 write-only SW_RST_0 EMV SIM Normal operation (default) 0 SW_RST_1 EMV SIM held in Reset 0x1 TX_DMA_EN Transmit DMA Enable 20 1 read-write TX_DMA_EN_0 No DMA Write Request asserted for Transmitter (default) 0 TX_DMA_EN_1 DMA Write Request asserted for Transmitter 0x1 XMT_CRC_LRC Transmit CRC or LRC Enable 30 1 read-write XMT_CRC_LRC_0 No CRC or LRC value is transmitted (default) 0 XMT_CRC_LRC_1 Transmit LRC or CRC info when FIFO empties (whichever is enabled) 0x1 XMT_EN Transmitter Enable 17 1 read-write XMT_EN_0 EMV SIM Transmitter disabled (default) 0 XMT_EN_1 EMV SIM Transmitter enabled 0x1 CWT_VAL Character Wait Time Value Register 0x38 32 read-write n 0x0 0x0 CWT Character Wait Time Value 0 16 read-write DIVISOR Baud Rate Divisor Register 0xC 32 read-write n 0x0 0x0 DIVISOR_VALUE Divisor (F/D) Value 0 9 read-write DIVISOR_VALUE_0 Invalid. As per ISO 7816 specification, minimum value of F/D is 5 0 DIVISOR_VALUE_1 Invalid. As per ISO 7816 specification, minimum value of F/D is 5 0x1 DIVISOR_VALUE_372 Divisor value for F = 372 and D = 1 (default) 0x174 DIVISOR_VALUE_2 Invalid. As per ISO 7816 specification, minimum value of F/D is 5 0x2 DIVISOR_VALUE_3 Invalid. As per ISO 7816 specification, minimum value of F/D is 5 0x3 DIVISOR_VALUE_4 Invalid. As per ISO 7816 specification, minimum value of F/D is 5 0x4 GPCNT0_VAL General Purpose Counter 0 Timeout Value Register 0x44 32 read-write n 0x0 0x0 GPCNT0 General Purpose Counter 0 Timeout Value 0 16 read-write GPCNT1_VAL General Purpose Counter 1 Timeout Value 0x48 32 read-write n 0x0 0x0 GPCNT1 General Purpose Counter 1 Timeout Value 0 16 read-write INT_MASK Interrupt Mask Register 0x14 32 read-write n 0x0 0x0 BGT_ERR_IM Block Guard Time Error Interrupt 12 1 read-write BGT_ERR_IM_0 BGT_ERR interrupt enabled 0 BGT_ERR_IM_1 BGT_ERR interrupt masked (default) 0x1 BWT_ERR_IM Block Wait Time Error Interrupt Mask 11 1 read-write BWT_ERR_IM_0 BWT_ERR interrupt enabled 0 BWT_ERR_IM_1 BWT_ERR interrupt masked (default) 0x1 CWT_ERR_IM Character Wait Time Error Interrupt Mask 9 1 read-write CWT_ERR_IM_0 CWT_ERR interrupt enabled 0 CWT_ERR_IM_1 CWT_ERR interrupt masked (default) 0x1 ETC_IM Early Transmit Complete Interrupt Mask 3 1 read-write ETC_IM_0 ETC interrupt enabled 0 ETC_IM_1 ETC interrupt masked (default) 0x1 GPCNT0_IM General Purpose Timer 0 Timeout Interrupt Mask 8 1 read-write GPCNT0_IM_0 GPCNT0_TO interrupt enabled 0 GPCNT0_IM_1 GPCNT0_TO interrupt masked (default) 0x1 GPCNT1_IM General Purpose Counter 1 Timeout Interrupt Mask 13 1 read-write GPCNT1_IM_0 GPCNT1_TO interrupt enabled 0 GPCNT1_IM_1 GPCNT1_TO interrupt masked (default) 0x1 PEF_IM Parity Error Interrupt Mask 15 1 read-write PEF_IM_0 PEF interrupt enabled 0 PEF_IM_1 PEF interrupt masked (default) 0x1 RDT_IM Receive Data Threshold Interrupt Mask 0 1 read-write RDT_IM_0 RDTF interrupt enabled 0 RDT_IM_1 RDTF interrupt masked (default) 0x1 RFO_IM Receive FIFO Overflow Interrupt Mask 2 1 read-write RFO_IM_0 RFO interrupt enabled 0 RFO_IM_1 RFO interrupt masked (default) 0x1 RNACK_IM Receiver NACK Threshold Interrupt Mask 10 1 read-write RNACK_IM_0 RTE interrupt enabled 0 RNACK_IM_1 RTE interrupt masked (default) 0x1 RX_DATA_IM Receive Data Interrupt Mask 14 1 read-write RX_DATA_IM_0 RX_DATA interrupt enabled 0 RX_DATA_IM_1 RX_DATA interrupt masked (default) 0x1 TC_IM Transmit Complete Interrupt Mask 1 1 read-write TC_IM_0 TCF interrupt enabled 0 TC_IM_1 TCF interrupt masked (default) 0x1 TDT_IM Transmit Data Threshold Interrupt Mask 7 1 read-write TDT_IM_0 TDTF interrupt enabled 0 TDT_IM_1 TDTF interrupt masked (default) 0x1 TFE_IM Transmit FIFO Empty Interrupt Mask 4 1 read-write TFE_IM_0 TFE interrupt enabled 0 TFE_IM_1 TFE interrupt masked (default) 0x1 TFF_IM Transmit FIFO Full Interrupt Mask 6 1 read-write TFF_IM_0 TFF interrupt enabled 0 TFF_IM_1 TFF interrupt masked (default) 0x1 TNACK_IM Transmit NACK Threshold Interrupt Mask 5 1 read-write TNACK_IM_0 TNTE interrupt enabled 0 TNACK_IM_1 TNTE interrupt masked (default) 0x1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 RX_FIFO_DEPTH Receive FIFO Depth 0 8 read-only TX_FIFO_DEPTH Transmit FIFO Depth 8 8 read-only PCSR Port Control and Status Register 0x28 32 read-write n 0x0 0x0 SAPD Auto Power Down Enable 0 1 read-write SAPD_0 Auto power down disabled (default) 0 SAPD_1 Auto power down enabled 0x1 SCEN Clock Enable for Smart Card 4 1 read-write SCEN_0 Smart Card Clock Disabled 0 SCEN_1 Smart Card Clock Enabled 0x1 SCSP Smart Card Clock Stop Polarity 5 1 read-write SCSP_0 Clock is logic 0 when stopped by SCEN 0 SCSP_1 Clock is logic 1 when stopped by SCEN 0x1 SPD Auto Power Down Control 7 1 read-write SPD_0 No effect (default) 0 SPD_1 Start Auto Powerdown or Power Down is in progress 0x1 SPDES SIM Presence Detect Edge Select 27 1 read-write SPDES_0 Falling edge on the pin (default) 0 SPDES_1 Rising edge on the pin 0x1 SPDIF Smart Card Presence Detect Interrupt Flag 25 1 read-write oneToClear SPDIF_0 No insertion or removal of Smart Card detected on Port (default) 0 SPDIF_1 Insertion or removal of Smart Card detected on Port 0x1 SPDIM Smart Card Presence Detect Interrupt Mask 24 1 read-write SPDIM_0 SIM presence detect interrupt is enabled 0 SPDIM_1 SIM presence detect interrupt is masked (default) 0x1 SPDP Smart Card Presence Detect Pin Status 26 1 read-only SPDP_0 SIM Presence Detect pin is logic low 0 SPDP_1 SIM Presence Detectpin is logic high 0x1 SRST Reset to Smart Card 3 1 read-write SRST_0 Smart Card Reset is asserted (default) 0 SRST_1 Smart Card Reset is de-asserted 0x1 SVCC_EN Vcc Enable for Smart Card 1 1 read-write SVCC_EN_0 Smart Card Voltage disabled (default) 0 SVCC_EN_1 Smart Card Voltage enabled 0x1 VCCENP VCC Enable Polarity Control 2 1 read-write VCCENP_0 VCC_EN is active high. Polarity of SVCC_EN is unchanged. 0 VCCENP_1 VCC_EN is active low. Polarity of SVCC_EN is inverted. 0x1 RX_BUF Receive Data Read Buffer 0x2C 32 read-only n 0x0 0x0 RX_BYTE Receive Data Byte Read 0 8 read-only RX_STATUS Receive Status Register 0x20 32 read-write n 0x0 0x0 BGT_ERR Block Guard Time Error Flag 11 1 read-write oneToClear BGT_ERR_0 Block guard time was sufficient 0 BGT_ERR_1 Block guard time was too small 0x1 BWT_ERR Block Wait Time Error Flag 10 1 read-write oneToClear BWT_ERR_0 Block wait time not exceeded 0 BWT_ERR_1 Block wait time was exceeded 0x1 CRC_OK CRC Check OK Flag 7 1 read-only CRC_OK_0 Current CRC value does not match remainder. 0 CRC_OK_1 Current calculated CRC value matches the expected result. 0x1 CWT_ERR Character Wait Time Error Flag 8 1 read-write oneToClear CWT_ERR_0 No CWT violation has occurred (default). 0 CWT_ERR_1 Time between two consecutive characters has exceeded the value in CHAR_WAIT. 0x1 FEF Frame Error Flag 13 1 read-write oneToClear FEF_0 No frame error detected 0 FEF_1 Frame error detected 0x1 LRC_OK LRC Check OK Flag 6 1 read-only LRC_OK_0 Current LRC value does not match remainder. 0 LRC_OK_1 Current calculated LRC value matches the expected result (i.e. zero). 0x1 PEF Parity Error Flag 12 1 read-write oneToClear PEF_0 No parity error detected 0 PEF_1 Parity error detected 0x1 RDTF Receive Data Threshold Interrupt Flag 5 1 read-only RDTF_0 Number of unread bytes in receive FIFO less than the value set by RDT[3:0] (default). 0 RDTF_1 Number of unread bytes in receive FIFO greater or than equal to value set by RDT[3:0]. 0x1 RFO Receive FIFO Overflow Flag 0 1 read-write oneToClear RFO_0 No overrun error has occurred (default) 0 RFO_1 A byte was received when the received FIFO was already full 0x1 RTE Received NACK Threshold Error Flag 9 1 read-write oneToClear RTE_0 Number of NACKs generated by the receiver is less than the value programmed in RTH[3:0] 0 RTE_1 Number of NACKs generated by the receiver is equal to the value programmed in RTH[3:0] 0x1 RX_CNT Receive FIFO Byte Count 24 4 read-only RX_CNT_0 FIFO is emtpy 0 RX_DATA Receive Data Interrupt Flag 4 1 read-write oneToClear RX_DATA_0 No new byte is received 0 RX_DATA_1 New byte is received ans stored in Receive FIFO 0x1 RX_WPTR Receive FIFO Write Pointer Value 16 4 read-only RX_THD Receiver Threshold Register 0x18 32 read-write n 0x0 0x0 RDT Receiver Data Threshold Value 0 4 read-write RNCK_THD Receiver NACK Threshold Value 8 4 read-write RNCK_THD_0 Zero Threshold. RTE will not be set 0 TX_BUF Transmit Data Buffer 0x30 32 read-write n 0x0 0x0 TX_BYTE Transmit Data Byte 0 8 write-only TX_GETU Transmitter Guard ETU Value Register 0x34 32 read-write n 0x0 0x0 GETU Transmitter Guard Time Value in ETU 0 8 read-write GETU_0 no additional ETUs inserted (default) 0 GETU_1 1 additional ETU inserted 0x1 GETU_254 254 additional ETUs inserted 0xFE GETU_255 Subtracts one ETU by reducing the number of STOP bits from two to one 0xFF TX_STATUS Transmitter Status Register 0x24 32 read-write n 0x0 0x0 ETCF Early Transmit Complete Flag 4 1 read-write oneToClear ETCF_0 Transmit pending or in progress 0 ETCF_1 Transmit complete (default) 0x1 GPCNT0_TO General Purpose Counter 0 Timeout Flag 8 1 read-write oneToClear GPCNT0_TO_0 GPCNT0_VAL time not reached, or bit has been cleared. (default) 0 GPCNT0_TO_1 General Purpose counter has reached the GPCNT0_VAL value 0x1 GPCNT1_TO General Purpose Counter 1 Timeout Flag 9 1 read-write oneToClear GPCNT1_TO_0 GPCNT1_VAL time not reached, or bit has been cleared. (default) 0 GPCNT1_TO_1 General Purpose counter has reached the GPCNT1_VAL value 0x1 TCF Transmit Complete Flag 5 1 read-write oneToClear TCF_0 Transmit pending or in progress 0 TCF_1 Transmit complete (default) 0x1 TDTF Transmit Data Threshold Flag 7 1 read-only TDTF_0 Number of bytes in FIFO is greater than TDT[3:0], or bit has been cleared 0 TDTF_1 Number of bytes in FIFO is less than or equal to TDT[3:0] (default) 0x1 TFE Transmit FIFO Empty Flag 3 1 read-write oneToClear TFE_0 Transmit FIFO is not empty 0 TFE_1 Transmit FIFO is empty (default) 0x1 TFF Transmit FIFO Full Flag 6 1 read-write oneToClear TFF_0 no description available 0 TFF_1 A Transmit FIFO Full condition has occurred 0x1 TNTE Transmit NACK Threshold Error Flag 0 1 read-write oneToClear TNTE_0 Transmit NACK threshold has not been reached (default) 0 TNTE_1 Transmit NACK threshold reached transmitter frozen 0x1 TX_CNT Transmit FIFO Byte Count 24 4 read-only TX_CNT_0 FIFO is emtpy 0 TX_RPTR Transmit FIFO Read Pointer 16 4 read-only TX_THD Transmitter Threshold Register 0x1C 32 read-write n 0x0 0x0 TDT Transmitter Data Threshold Value 0 4 read-write TNCK_THD Transmitter NACK Threshold Value 8 4 read-write TNCK_THD_0 TNTE will never be set retransmission after NACK reception is disabled. 0 TNCK_THD_1 TNTE will be set after 1 nack is received 0 retransmissions occurs. 0x1 TNCK_THD_2 TNTE will be set after 2 nacks are received at most 1 retransmission occurs. 0x2 TNCK_THD_3 TNTE will be set after 3 nacks are received at most 2 retransmissions occurs. 0x3 TNCK_THD_15 TNTE will be set after 15 nacks are received at most 14 retransmissions occurs. 0xF VER_ID Version ID Register 0x0 32 read-only n 0x0 0x0 VER Version ID of the module 0 32 read-only EWM EWM EWM 0x0 0x0 0x6 registers n EWM 19 CLKPRESCALER Clock Prescaler Register 0x5 8 read-writeOnce n 0x0 0x0 CLK_DIV CLK_DIV 0 8 read-writeOnce CMPH Compare High Register 0x3 8 read-writeOnce n 0x0 0x0 COMPAREH COMPAREH 0 8 read-writeOnce CMPL Compare Low Register 0x2 8 read-writeOnce n 0x0 0x0 COMPAREL COMPAREL 0 8 read-writeOnce CTRL Control Register 0x0 8 read-write n 0x0 0x0 ASSIN EWM_in's Assertion State Select. 1 1 read-writeOnce EWMEN EWM enable. 0 1 read-writeOnce INEN Input Enable. 2 1 read-writeOnce INTEN Interrupt Enable. 3 1 read-write SERV Service Register 0x1 8 write-only n 0x0 0x0 SERVICE SERVICE 0 8 write-only FB FB FLEXBUS 0x0 0x0 0x64 registers n CSAR Chip Select Address Register 0x0 32 read-write n 0x0 0x0 BA Base Address 16 16 read-write CSCR Chip Select Control Register 0x8 32 read-write n 0x0 0x0 AA Auto-Acknowledge Enable 8 1 read-write AA_0 Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. 0 AA_1 Enabled. Internal transfer acknowledge is asserted as specified by WS. 0x1 ASET Address Setup 20 2 read-write ASET_0 no description available 0 ASET_1 no description available 0x1 ASET_2 no description available 0x2 ASET_3 no description available 0x3 BEM Byte-Enable Mode 5 1 read-write BEM_0 no description available 0 BEM_1 no description available 0x1 BLS Byte-Lane Shift 9 1 read-write BLS_0 Not shifted. Data is left-aligned on FB_AD. 0 BLS_1 Shifted. Data is right-aligned on FB_AD. 0x1 BSTR Burst-Read Enable 4 1 read-write BSTR_0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. 0 BSTR_1 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. 0x1 BSTW Burst-Write Enable 3 1 read-write BSTW_0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. 0 BSTW_1 Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. 0x1 EXTS EXTS 22 1 read-write EXTS_0 no description available 0 EXTS_1 no description available 0x1 PS Port Size 6 2 read-write PS_2 no description available #1x PS_0 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. 0 PS_1 no description available 0x1 RDAH Read Address Hold or Deselect 18 2 read-write RDAH_0 When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. 0 RDAH_1 When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. 0x1 RDAH_2 When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. 0x2 RDAH_3 When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. 0x3 SWS Secondary Wait States 26 6 read-write SWSEN Secondary Wait State Enable 23 1 read-write SWSEN_0 Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. 0 SWSEN_1 Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. 0x1 WRAH Write Address Hold or Deselect 16 2 read-write WRAH_0 no description available 0 WRAH_1 2 cycles 0x1 WRAH_2 3 cycles 0x2 WRAH_3 no description available 0x3 WS Wait States 10 6 read-write CSMR Chip Select Mask Register 0x4 32 read-write n 0x0 0x0 BAM Base Address Mask 16 16 read-write BAM_0 The corresponding address bit in CSAR is used in the chip-select decode. 0 BAM_1 The corresponding address bit in CSAR is a don't care in the chip-select decode. 0x1 V Valid 0 1 read-write V_0 Chip-select is invalid. 0 V_1 Chip-select is valid. 0x1 WP Write Protect 8 1 read-write WP_0 Write accesses are allowed. 0 WP_1 Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. 0x1 CSPMCR Chip Select Port Multiplexing Control Register 0x60 32 read-write n 0x0 0x0 GROUP1 FlexBus Signal Group 1 Multiplex control 28 4 read-write GROUP1_0 FB_ALE 0 GROUP1_1 no description available 0x1 GROUP1_2 no description available 0x2 GROUP2 FlexBus Signal Group 2 Multiplex control 24 4 read-write GROUP2_0 no description available 0 GROUP2_1 FB_TSIZ0 0x1 GROUP2_2 no description available 0x2 GROUP3 FlexBus Signal Group 3 Multiplex control 20 4 read-write GROUP3_0 no description available 0 GROUP3_1 FB_TSIZ1 0x1 GROUP3_2 no description available 0x2 GROUP4 FlexBus Signal Group 4 Multiplex control 16 4 read-write GROUP4_0 no description available 0 GROUP4_1 no description available 0x1 GROUP4_2 no description available 0x2 GROUP5 FlexBus Signal Group 5 Multiplex control 12 4 read-write GROUP5_0 no description available 0 GROUP5_1 no description available 0x1 GROUP5_2 no description available 0x2 CS[0]-CSAR Chip Select Address Register 0x0 32 read-write n 0x0 0x0 BA Base Address 16 16 read-write CS[0]-CSCR Chip Select Control Register 0x8 32 read-write n 0x0 0x0 AA Auto-Acknowledge Enable 8 1 read-write AA_0 Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. 0 AA_1 Enabled. Internal transfer acknowledge is asserted as specified by WS. 0x1 ASET Address Setup 20 2 read-write ASET_0 no description available 0 ASET_1 no description available 0x1 ASET_2 no description available 0x2 ASET_3 no description available 0x3 BEM Byte-Enable Mode 5 1 read-write BEM_0 no description available 0 BEM_1 no description available 0x1 BLS Byte-Lane Shift 9 1 read-write BLS_0 Not shifted. Data is left-aligned on FB_AD. 0 BLS_1 Shifted. Data is right-aligned on FB_AD. 0x1 BSTR Burst-Read Enable 4 1 read-write BSTR_0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. 0 BSTR_1 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. 0x1 BSTW Burst-Write Enable 3 1 read-write BSTW_0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. 0 BSTW_1 Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. 0x1 EXTS EXTS 22 1 read-write EXTS_0 no description available 0 EXTS_1 no description available 0x1 PS Port Size 6 2 read-write PS_2 no description available #1x PS_0 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. 0 PS_1 no description available 0x1 RDAH Read Address Hold or Deselect 18 2 read-write RDAH_0 When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. 0 RDAH_1 When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. 0x1 RDAH_2 When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. 0x2 RDAH_3 When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. 0x3 SWS Secondary Wait States 26 6 read-write SWSEN Secondary Wait State Enable 23 1 read-write SWSEN_0 Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. 0 SWSEN_1 Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. 0x1 WRAH Write Address Hold or Deselect 16 2 read-write WRAH_0 no description available 0 WRAH_1 2 cycles 0x1 WRAH_2 3 cycles 0x2 WRAH_3 no description available 0x3 WS Wait States 10 6 read-write CS[0]-CSMR Chip Select Mask Register 0x4 32 read-write n 0x0 0x0 BAM Base Address Mask 16 16 read-write BAM_0 The corresponding address bit in CSAR is used in the chip-select decode. 0 BAM_1 The corresponding address bit in CSAR is a don't care in the chip-select decode. 0x1 V Valid 0 1 read-write V_0 Chip-select is invalid. 0 V_1 Chip-select is valid. 0x1 WP Write Protect 8 1 read-write WP_0 Write accesses are allowed. 0 WP_1 Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. 0x1 CS[1]-CS[0]-CSAR Chip Select Address Register 0xC 32 read-write n 0x0 0x0 BA Base Address 16 16 read-write CS[1]-CS[0]-CSCR Chip Select Control Register 0x14 32 read-write n 0x0 0x0 AA Auto-Acknowledge Enable 8 1 read-write AA_0 Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. 0 AA_1 Enabled. Internal transfer acknowledge is asserted as specified by WS. 0x1 ASET Address Setup 20 2 read-write ASET_0 no description available 0 ASET_1 no description available 0x1 ASET_2 no description available 0x2 ASET_3 no description available 0x3 BEM Byte-Enable Mode 5 1 read-write BEM_0 no description available 0 BEM_1 no description available 0x1 BLS Byte-Lane Shift 9 1 read-write BLS_0 Not shifted. Data is left-aligned on FB_AD. 0 BLS_1 Shifted. Data is right-aligned on FB_AD. 0x1 BSTR Burst-Read Enable 4 1 read-write BSTR_0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. 0 BSTR_1 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. 0x1 BSTW Burst-Write Enable 3 1 read-write BSTW_0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. 0 BSTW_1 Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. 0x1 EXTS EXTS 22 1 read-write EXTS_0 no description available 0 EXTS_1 no description available 0x1 PS Port Size 6 2 read-write PS_2 no description available #1x PS_0 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. 0 PS_1 no description available 0x1 RDAH Read Address Hold or Deselect 18 2 read-write RDAH_0 When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. 0 RDAH_1 When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. 0x1 RDAH_2 When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. 0x2 RDAH_3 When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. 0x3 SWS Secondary Wait States 26 6 read-write SWSEN Secondary Wait State Enable 23 1 read-write SWSEN_0 Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. 0 SWSEN_1 Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. 0x1 WRAH Write Address Hold or Deselect 16 2 read-write WRAH_0 no description available 0 WRAH_1 2 cycles 0x1 WRAH_2 3 cycles 0x2 WRAH_3 no description available 0x3 WS Wait States 10 6 read-write CS[1]-CS[0]-CSMR Chip Select Mask Register 0x10 32 read-write n 0x0 0x0 BAM Base Address Mask 16 16 read-write BAM_0 The corresponding address bit in CSAR is used in the chip-select decode. 0 BAM_1 The corresponding address bit in CSAR is a don't care in the chip-select decode. 0x1 V Valid 0 1 read-write V_0 Chip-select is invalid. 0 V_1 Chip-select is valid. 0x1 WP Write Protect 8 1 read-write WP_0 Write accesses are allowed. 0 WP_1 Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. 0x1 CS[2]-CS[1]-CS[0]-CSAR Chip Select Address Register 0x24 32 read-write n 0x0 0x0 BA Base Address 16 16 read-write CS[2]-CS[1]-CS[0]-CSCR Chip Select Control Register 0x2C 32 read-write n 0x0 0x0 AA Auto-Acknowledge Enable 8 1 read-write AA_0 Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. 0 AA_1 Enabled. Internal transfer acknowledge is asserted as specified by WS. 0x1 ASET Address Setup 20 2 read-write ASET_0 no description available 0 ASET_1 no description available 0x1 ASET_2 no description available 0x2 ASET_3 no description available 0x3 BEM Byte-Enable Mode 5 1 read-write BEM_0 no description available 0 BEM_1 no description available 0x1 BLS Byte-Lane Shift 9 1 read-write BLS_0 Not shifted. Data is left-aligned on FB_AD. 0 BLS_1 Shifted. Data is right-aligned on FB_AD. 0x1 BSTR Burst-Read Enable 4 1 read-write BSTR_0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. 0 BSTR_1 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. 0x1 BSTW Burst-Write Enable 3 1 read-write BSTW_0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. 0 BSTW_1 Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. 0x1 EXTS EXTS 22 1 read-write EXTS_0 no description available 0 EXTS_1 no description available 0x1 PS Port Size 6 2 read-write PS_2 no description available #1x PS_0 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. 0 PS_1 no description available 0x1 RDAH Read Address Hold or Deselect 18 2 read-write RDAH_0 When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. 0 RDAH_1 When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. 0x1 RDAH_2 When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. 0x2 RDAH_3 When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. 0x3 SWS Secondary Wait States 26 6 read-write SWSEN Secondary Wait State Enable 23 1 read-write SWSEN_0 Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. 0 SWSEN_1 Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. 0x1 WRAH Write Address Hold or Deselect 16 2 read-write WRAH_0 no description available 0 WRAH_1 2 cycles 0x1 WRAH_2 3 cycles 0x2 WRAH_3 no description available 0x3 WS Wait States 10 6 read-write CS[2]-CS[1]-CS[0]-CSMR Chip Select Mask Register 0x28 32 read-write n 0x0 0x0 BAM Base Address Mask 16 16 read-write BAM_0 The corresponding address bit in CSAR is used in the chip-select decode. 0 BAM_1 The corresponding address bit in CSAR is a don't care in the chip-select decode. 0x1 V Valid 0 1 read-write V_0 Chip-select is invalid. 0 V_1 Chip-select is valid. 0x1 WP Write Protect 8 1 read-write WP_0 Write accesses are allowed. 0 WP_1 Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. 0x1 CS[3]-CS[2]-CS[1]-CS[0]-CSAR Chip Select Address Register 0x48 32 read-write n 0x0 0x0 BA Base Address 16 16 read-write CS[3]-CS[2]-CS[1]-CS[0]-CSCR Chip Select Control Register 0x50 32 read-write n 0x0 0x0 AA Auto-Acknowledge Enable 8 1 read-write AA_0 Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. 0 AA_1 Enabled. Internal transfer acknowledge is asserted as specified by WS. 0x1 ASET Address Setup 20 2 read-write ASET_0 no description available 0 ASET_1 no description available 0x1 ASET_2 no description available 0x2 ASET_3 no description available 0x3 BEM Byte-Enable Mode 5 1 read-write BEM_0 no description available 0 BEM_1 no description available 0x1 BLS Byte-Lane Shift 9 1 read-write BLS_0 Not shifted. Data is left-aligned on FB_AD. 0 BLS_1 Shifted. Data is right-aligned on FB_AD. 0x1 BSTR Burst-Read Enable 4 1 read-write BSTR_0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. 0 BSTR_1 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. 0x1 BSTW Burst-Write Enable 3 1 read-write BSTW_0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. 0 BSTW_1 Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. 0x1 EXTS EXTS 22 1 read-write EXTS_0 no description available 0 EXTS_1 no description available 0x1 PS Port Size 6 2 read-write PS_2 no description available #1x PS_0 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. 0 PS_1 no description available 0x1 RDAH Read Address Hold or Deselect 18 2 read-write RDAH_0 When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. 0 RDAH_1 When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. 0x1 RDAH_2 When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. 0x2 RDAH_3 When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. 0x3 SWS Secondary Wait States 26 6 read-write SWSEN Secondary Wait State Enable 23 1 read-write SWSEN_0 Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. 0 SWSEN_1 Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. 0x1 WRAH Write Address Hold or Deselect 16 2 read-write WRAH_0 no description available 0 WRAH_1 2 cycles 0x1 WRAH_2 3 cycles 0x2 WRAH_3 no description available 0x3 WS Wait States 10 6 read-write CS[3]-CS[2]-CS[1]-CS[0]-CSMR Chip Select Mask Register 0x4C 32 read-write n 0x0 0x0 BAM Base Address Mask 16 16 read-write BAM_0 The corresponding address bit in CSAR is used in the chip-select decode. 0 BAM_1 The corresponding address bit in CSAR is a don't care in the chip-select decode. 0x1 V Valid 0 1 read-write V_0 Chip-select is invalid. 0 V_1 Chip-select is valid. 0x1 WP Write Protect 8 1 read-write WP_0 Write accesses are allowed. 0 WP_1 Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. 0x1 CS[4]-CS[3]-CS[2]-CS[1]-CS[0]-CSAR Chip Select Address Register 0x78 32 read-write n 0x0 0x0 BA Base Address 16 16 read-write CS[4]-CS[3]-CS[2]-CS[1]-CS[0]-CSCR Chip Select Control Register 0x80 32 read-write n 0x0 0x0 AA Auto-Acknowledge Enable 8 1 read-write AA_0 Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. 0 AA_1 Enabled. Internal transfer acknowledge is asserted as specified by WS. 0x1 ASET Address Setup 20 2 read-write ASET_0 no description available 0 ASET_1 no description available 0x1 ASET_2 no description available 0x2 ASET_3 no description available 0x3 BEM Byte-Enable Mode 5 1 read-write BEM_0 no description available 0 BEM_1 no description available 0x1 BLS Byte-Lane Shift 9 1 read-write BLS_0 Not shifted. Data is left-aligned on FB_AD. 0 BLS_1 Shifted. Data is right-aligned on FB_AD. 0x1 BSTR Burst-Read Enable 4 1 read-write BSTR_0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. 0 BSTR_1 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. 0x1 BSTW Burst-Write Enable 3 1 read-write BSTW_0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. 0 BSTW_1 Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. 0x1 EXTS EXTS 22 1 read-write EXTS_0 no description available 0 EXTS_1 no description available 0x1 PS Port Size 6 2 read-write PS_2 no description available #1x PS_0 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. 0 PS_1 no description available 0x1 RDAH Read Address Hold or Deselect 18 2 read-write RDAH_0 When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. 0 RDAH_1 When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. 0x1 RDAH_2 When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. 0x2 RDAH_3 When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. 0x3 SWS Secondary Wait States 26 6 read-write SWSEN Secondary Wait State Enable 23 1 read-write SWSEN_0 Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. 0 SWSEN_1 Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. 0x1 WRAH Write Address Hold or Deselect 16 2 read-write WRAH_0 no description available 0 WRAH_1 2 cycles 0x1 WRAH_2 3 cycles 0x2 WRAH_3 no description available 0x3 WS Wait States 10 6 read-write CS[4]-CS[3]-CS[2]-CS[1]-CS[0]-CSMR Chip Select Mask Register 0x7C 32 read-write n 0x0 0x0 BAM Base Address Mask 16 16 read-write BAM_0 The corresponding address bit in CSAR is used in the chip-select decode. 0 BAM_1 The corresponding address bit in CSAR is a don't care in the chip-select decode. 0x1 V Valid 0 1 read-write V_0 Chip-select is invalid. 0 V_1 Chip-select is valid. 0x1 WP Write Protect 8 1 read-write WP_0 Write accesses are allowed. 0 WP_1 Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. 0x1 CS[5]-CS[4]-CS[3]-CS[2]-CS[1]-CS[0]-CSAR Chip Select Address Register 0xB4 32 read-write n 0x0 0x0 BA Base Address 16 16 read-write CS[5]-CS[4]-CS[3]-CS[2]-CS[1]-CS[0]-CSCR Chip Select Control Register 0xBC 32 read-write n 0x0 0x0 AA Auto-Acknowledge Enable 8 1 read-write AA_0 Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. 0 AA_1 Enabled. Internal transfer acknowledge is asserted as specified by WS. 0x1 ASET Address Setup 20 2 read-write ASET_0 no description available 0 ASET_1 no description available 0x1 ASET_2 no description available 0x2 ASET_3 no description available 0x3 BEM Byte-Enable Mode 5 1 read-write BEM_0 no description available 0 BEM_1 no description available 0x1 BLS Byte-Lane Shift 9 1 read-write BLS_0 Not shifted. Data is left-aligned on FB_AD. 0 BLS_1 Shifted. Data is right-aligned on FB_AD. 0x1 BSTR Burst-Read Enable 4 1 read-write BSTR_0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. 0 BSTR_1 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. 0x1 BSTW Burst-Write Enable 3 1 read-write BSTW_0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes. 0 BSTW_1 Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. 0x1 EXTS EXTS 22 1 read-write EXTS_0 no description available 0 EXTS_1 no description available 0x1 PS Port Size 6 2 read-write PS_2 no description available #1x PS_0 32-bit port size. Valid data is sampled and driven on FB_D[31:0]. 0 PS_1 no description available 0x1 RDAH Read Address Hold or Deselect 18 2 read-write RDAH_0 When AA is 1b, 1 cycle. When AA is 0b, 0 cycles. 0 RDAH_1 When AA is 1b, 2 cycles. When AA is 0b, 1 cycle. 0x1 RDAH_2 When AA is 1b, 3 cycles. When AA is 0b, 2 cycles. 0x2 RDAH_3 When AA is 1b, 4 cycles. When AA is 0b, 3 cycles. 0x3 SWS Secondary Wait States 26 6 read-write SWSEN Secondary Wait State Enable 23 1 read-write SWSEN_0 Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers. 0 SWSEN_1 Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations. 0x1 WRAH Write Address Hold or Deselect 16 2 read-write WRAH_0 no description available 0 WRAH_1 2 cycles 0x1 WRAH_2 3 cycles 0x2 WRAH_3 no description available 0x3 WS Wait States 10 6 read-write CS[5]-CS[4]-CS[3]-CS[2]-CS[1]-CS[0]-CSMR Chip Select Mask Register 0xB8 32 read-write n 0x0 0x0 BAM Base Address Mask 16 16 read-write BAM_0 The corresponding address bit in CSAR is used in the chip-select decode. 0 BAM_1 The corresponding address bit in CSAR is a don't care in the chip-select decode. 0x1 V Valid 0 1 read-write V_0 Chip-select is invalid. 0 V_1 Chip-select is valid. 0x1 WP Write Protect 8 1 read-write WP_0 Write accesses are allowed. 0 WP_1 Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle. 0x1 FLEXIO0 FLEXIO FLEXIO0 0x0 0x0 0x7A0 registers n FLEXIO0 35 CTRL FlexIO Control Register 0x8 32 read-write n 0x0 0x0 DBGE Debug Enable 30 1 read-write DBGE_0 FlexIO is disabled in debug modes. 0 DBGE_1 FlexIO is enabled in debug modes 0x1 DOZEN Doze Enable 31 1 read-write DOZEN_0 FlexIO enabled in Doze modes. 0 DOZEN_1 FlexIO disabled in Doze modes. 0x1 FASTACC Fast Access 2 1 read-write FASTACC_0 Configures for normal register accesses to FlexIO 0 FASTACC_1 Configures for fast register accesses to FlexIO 0x1 FLEXEN FlexIO Enable 0 1 read-write FLEXEN_0 FlexIO module is disabled. 0 FLEXEN_1 FlexIO module is enabled. 0x1 SWRST Software Reset 1 1 read-write SWRST_0 Software reset is disabled 0 SWRST_1 Software reset is enabled, all FlexIO registers except the Control Register are reset. 0x1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 PIN Pin Number 16 8 read-only SHIFTER Shifter Number 0 8 read-only TIMER Timer Number 8 8 read-only TRIGGER Trigger Number 24 8 read-only PIN Pin State Register 0xC 32 read-only n 0x0 0x0 PDI Pin Data Input 0 32 read-only SHIFTBUF0 Shifter Buffer N Register 0x200 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF1 Shifter Buffer N Register 0x204 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF2 Shifter Buffer N Register 0x208 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF3 Shifter Buffer N Register 0x20C 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF4 Shifter Buffer N Register 0x210 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF5 Shifter Buffer N Register 0x214 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF6 Shifter Buffer N Register 0x218 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF7 Shifter Buffer N Register 0x21C 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUFBBS0 Shifter Buffer N Bit Byte Swapped Register 0x380 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS1 Shifter Buffer N Bit Byte Swapped Register 0x384 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS2 Shifter Buffer N Bit Byte Swapped Register 0x388 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS3 Shifter Buffer N Bit Byte Swapped Register 0x38C 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS4 Shifter Buffer N Bit Byte Swapped Register 0x390 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS5 Shifter Buffer N Bit Byte Swapped Register 0x394 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS6 Shifter Buffer N Bit Byte Swapped Register 0x398 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS7 Shifter Buffer N Bit Byte Swapped Register 0x39C 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS[0] Shifter Buffer N Bit Byte Swapped Register 0x700 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS[1] Shifter Buffer N Bit Byte Swapped Register 0xA84 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS[2] Shifter Buffer N Bit Byte Swapped Register 0xE0C 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS[3] Shifter Buffer N Bit Byte Swapped Register 0x1198 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS[4] Shifter Buffer N Bit Byte Swapped Register 0x1528 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS[5] Shifter Buffer N Bit Byte Swapped Register 0x18BC 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS[6] Shifter Buffer N Bit Byte Swapped Register 0x1C54 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBBS[7] Shifter Buffer N Bit Byte Swapped Register 0x1FF0 32 read-write n 0x0 0x0 SHIFTBUFBBS Shift Buffer 0 32 read-write SHIFTBUFBIS0 Shifter Buffer N Bit Swapped Register 0x280 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS1 Shifter Buffer N Bit Swapped Register 0x284 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS2 Shifter Buffer N Bit Swapped Register 0x288 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS3 Shifter Buffer N Bit Swapped Register 0x28C 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS4 Shifter Buffer N Bit Swapped Register 0x290 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS5 Shifter Buffer N Bit Swapped Register 0x294 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS6 Shifter Buffer N Bit Swapped Register 0x298 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS7 Shifter Buffer N Bit Swapped Register 0x29C 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS[0] Shifter Buffer N Bit Swapped Register 0x500 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS[1] Shifter Buffer N Bit Swapped Register 0x784 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS[2] Shifter Buffer N Bit Swapped Register 0xA0C 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS[3] Shifter Buffer N Bit Swapped Register 0xC98 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS[4] Shifter Buffer N Bit Swapped Register 0xF28 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS[5] Shifter Buffer N Bit Swapped Register 0x11BC 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS[6] Shifter Buffer N Bit Swapped Register 0x1454 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBIS[7] Shifter Buffer N Bit Swapped Register 0x16F0 32 read-write n 0x0 0x0 SHIFTBUFBIS Shift Buffer 0 32 read-write SHIFTBUFBYS0 Shifter Buffer N Byte Swapped Register 0x300 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS1 Shifter Buffer N Byte Swapped Register 0x304 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS2 Shifter Buffer N Byte Swapped Register 0x308 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS3 Shifter Buffer N Byte Swapped Register 0x30C 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS4 Shifter Buffer N Byte Swapped Register 0x310 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS5 Shifter Buffer N Byte Swapped Register 0x314 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS6 Shifter Buffer N Byte Swapped Register 0x318 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS7 Shifter Buffer N Byte Swapped Register 0x31C 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS[0] Shifter Buffer N Byte Swapped Register 0x600 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS[1] Shifter Buffer N Byte Swapped Register 0x904 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS[2] Shifter Buffer N Byte Swapped Register 0xC0C 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS[3] Shifter Buffer N Byte Swapped Register 0xF18 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS[4] Shifter Buffer N Byte Swapped Register 0x1228 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS[5] Shifter Buffer N Byte Swapped Register 0x153C 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS[6] Shifter Buffer N Byte Swapped Register 0x1854 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFBYS[7] Shifter Buffer N Byte Swapped Register 0x1B70 32 read-write n 0x0 0x0 SHIFTBUFBYS Shift Buffer 0 32 read-write SHIFTBUFHWS0 Shifter Buffer N Half Word Swapped Register 0x700 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS1 Shifter Buffer N Half Word Swapped Register 0x704 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS2 Shifter Buffer N Half Word Swapped Register 0x708 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS3 Shifter Buffer N Half Word Swapped Register 0x70C 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS4 Shifter Buffer N Half Word Swapped Register 0x710 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS5 Shifter Buffer N Half Word Swapped Register 0x714 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS6 Shifter Buffer N Half Word Swapped Register 0x718 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS7 Shifter Buffer N Half Word Swapped Register 0x71C 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS[0] Shifter Buffer N Half Word Swapped Register 0xE00 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS[1] Shifter Buffer N Half Word Swapped Register 0x1504 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS[2] Shifter Buffer N Half Word Swapped Register 0x1C0C 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS[3] Shifter Buffer N Half Word Swapped Register 0x2318 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS[4] Shifter Buffer N Half Word Swapped Register 0x2A28 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS[5] Shifter Buffer N Half Word Swapped Register 0x313C 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS[6] Shifter Buffer N Half Word Swapped Register 0x3854 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFHWS[7] Shifter Buffer N Half Word Swapped Register 0x3F70 32 read-write n 0x0 0x0 SHIFTBUFHWS Shift Buffer 0 32 read-write SHIFTBUFNBS0 Shifter Buffer N Nibble Byte Swapped Register 0x680 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS1 Shifter Buffer N Nibble Byte Swapped Register 0x684 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS2 Shifter Buffer N Nibble Byte Swapped Register 0x688 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS3 Shifter Buffer N Nibble Byte Swapped Register 0x68C 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS4 Shifter Buffer N Nibble Byte Swapped Register 0x690 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS5 Shifter Buffer N Nibble Byte Swapped Register 0x694 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS6 Shifter Buffer N Nibble Byte Swapped Register 0x698 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS7 Shifter Buffer N Nibble Byte Swapped Register 0x69C 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS[0] Shifter Buffer N Nibble Byte Swapped Register 0xD00 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS[1] Shifter Buffer N Nibble Byte Swapped Register 0x1384 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS[2] Shifter Buffer N Nibble Byte Swapped Register 0x1A0C 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS[3] Shifter Buffer N Nibble Byte Swapped Register 0x2098 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS[4] Shifter Buffer N Nibble Byte Swapped Register 0x2728 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS[5] Shifter Buffer N Nibble Byte Swapped Register 0x2DBC 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS[6] Shifter Buffer N Nibble Byte Swapped Register 0x3454 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNBS[7] Shifter Buffer N Nibble Byte Swapped Register 0x3AF0 32 read-write n 0x0 0x0 SHIFTBUFNBS Shift Buffer 0 32 read-write SHIFTBUFNIS0 Shifter Buffer N Nibble Swapped Register 0x780 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS1 Shifter Buffer N Nibble Swapped Register 0x784 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS2 Shifter Buffer N Nibble Swapped Register 0x788 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS3 Shifter Buffer N Nibble Swapped Register 0x78C 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS4 Shifter Buffer N Nibble Swapped Register 0x790 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS5 Shifter Buffer N Nibble Swapped Register 0x794 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS6 Shifter Buffer N Nibble Swapped Register 0x798 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS7 Shifter Buffer N Nibble Swapped Register 0x79C 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS[0] Shifter Buffer N Nibble Swapped Register 0xF00 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS[1] Shifter Buffer N Nibble Swapped Register 0x1684 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS[2] Shifter Buffer N Nibble Swapped Register 0x1E0C 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS[3] Shifter Buffer N Nibble Swapped Register 0x2598 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS[4] Shifter Buffer N Nibble Swapped Register 0x2D28 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS[5] Shifter Buffer N Nibble Swapped Register 0x34BC 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS[6] Shifter Buffer N Nibble Swapped Register 0x3C54 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUFNIS[7] Shifter Buffer N Nibble Swapped Register 0x43F0 32 read-write n 0x0 0x0 SHIFTBUFNIS Shift Buffer 0 32 read-write SHIFTBUF[0] Shifter Buffer N Register 0x400 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF[1] Shifter Buffer N Register 0x604 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF[2] Shifter Buffer N Register 0x80C 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF[3] Shifter Buffer N Register 0xA18 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF[4] Shifter Buffer N Register 0xC28 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF[5] Shifter Buffer N Register 0xE3C 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF[6] Shifter Buffer N Register 0x1054 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTBUF[7] Shifter Buffer N Register 0x1270 32 read-write n 0x0 0x0 SHIFTBUF Shift Buffer 0 32 read-write SHIFTCFG0 Shifter Configuration N Register 0x100 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 SHIFTCFG1 Shifter Configuration N Register 0x104 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 SHIFTCFG2 Shifter Configuration N Register 0x108 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 SHIFTCFG3 Shifter Configuration N Register 0x10C 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 SHIFTCFG4 Shifter Configuration N Register 0x110 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 SHIFTCFG5 Shifter Configuration N Register 0x114 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 SHIFTCFG6 Shifter Configuration N Register 0x118 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 SHIFTCFG7 Shifter Configuration N Register 0x11C 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 SHIFTCFG[0] Shifter Configuration N Register 0x200 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 SHIFTCFG[1] Shifter Configuration N Register 0x304 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 SHIFTCFG[2] Shifter Configuration N Register 0x40C 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 SHIFTCFG[3] Shifter Configuration N Register 0x518 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 SHIFTCFG[4] Shifter Configuration N Register 0x628 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 SHIFTCFG[5] Shifter Configuration N Register 0x73C 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 SHIFTCFG[6] Shifter Configuration N Register 0x854 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 SHIFTCFG[7] Shifter Configuration N Register 0x970 32 read-write n 0x0 0x0 INSRC Input Source 8 1 read-write INSRC_0 Pin 0 INSRC_1 Shifter N+1 Output 0x1 PWIDTH Parallel Width 16 5 read-write SSTART Shifter Start bit 0 2 read-write SSTART_0 Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable 0 SSTART_1 Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift 0x1 SSTART_2 Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0 0x2 SSTART_3 Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 0x3 SSTOP Shifter Stop bit 4 2 read-write SSTOP_0 Stop bit disabled for transmitter/receiver/match store 0 SSTOP_2 Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0 0x2 SSTOP_3 Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 0x3 SHIFTCTL0 Shifter Control N Register 0x80 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 SMOD_6 no description available 0x6 SMOD_7 no description available 0x7 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write SHIFTCTL1 Shifter Control N Register 0x84 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 SMOD_6 no description available 0x6 SMOD_7 no description available 0x7 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write SHIFTCTL2 Shifter Control N Register 0x88 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 SMOD_6 no description available 0x6 SMOD_7 no description available 0x7 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write SHIFTCTL3 Shifter Control N Register 0x8C 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 SMOD_6 no description available 0x6 SMOD_7 no description available 0x7 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write SHIFTCTL4 Shifter Control N Register 0x90 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 SMOD_6 no description available 0x6 SMOD_7 no description available 0x7 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write SHIFTCTL5 Shifter Control N Register 0x94 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 SMOD_6 no description available 0x6 SMOD_7 no description available 0x7 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write SHIFTCTL6 Shifter Control N Register 0x98 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 SMOD_6 no description available 0x6 SMOD_7 no description available 0x7 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write SHIFTCTL7 Shifter Control N Register 0x9C 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 SMOD_6 no description available 0x6 SMOD_7 no description available 0x7 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write SHIFTCTL[0] Shifter Control N Register 0x100 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 SMOD_6 no description available 0x6 SMOD_7 no description available 0x7 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write SHIFTCTL[1] Shifter Control N Register 0x184 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 SMOD_6 no description available 0x6 SMOD_7 no description available 0x7 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write SHIFTCTL[2] Shifter Control N Register 0x20C 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 SMOD_6 no description available 0x6 SMOD_7 no description available 0x7 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write SHIFTCTL[3] Shifter Control N Register 0x298 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 SMOD_6 no description available 0x6 SMOD_7 no description available 0x7 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write SHIFTCTL[4] Shifter Control N Register 0x328 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 SMOD_6 no description available 0x6 SMOD_7 no description available 0x7 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write SHIFTCTL[5] Shifter Control N Register 0x3BC 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 SMOD_6 no description available 0x6 SMOD_7 no description available 0x7 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write SHIFTCTL[6] Shifter Control N Register 0x454 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 SMOD_6 no description available 0x6 SMOD_7 no description available 0x7 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write SHIFTCTL[7] Shifter Control N Register 0x4F0 32 read-write n 0x0 0x0 PINCFG Shifter Pin Configuration 16 2 read-write PINCFG_0 Shifter pin output disabled 0 PINCFG_1 Shifter pin open drain or bidirectional output enable 0x1 PINCFG_2 Shifter pin bidirectional output data 0x2 PINCFG_3 Shifter pin output 0x3 PINPOL Shifter Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Shifter Pin Select 8 5 read-write SMOD Shifter Mode 0 3 read-write SMOD_0 Disabled. 0 SMOD_1 Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer. 0x1 SMOD_2 Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer. 0x2 SMOD_4 Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer. 0x4 SMOD_5 Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents. 0x5 SMOD_6 no description available 0x6 SMOD_7 no description available 0x7 TIMPOL Timer Polarity 23 1 read-write TIMPOL_0 Shift on posedge of Shift clock 0 TIMPOL_1 Shift on negedge of Shift clock 0x1 TIMSEL Timer Select 24 3 read-write SHIFTEIEN Shifter Error Interrupt Enable 0x24 32 read-write n 0x0 0x0 SEIE Shifter Error Interrupt Enable 0 8 read-write SHIFTERR Shifter Error Register 0x14 32 read-write n 0x0 0x0 SEF Shifter Error Flags 0 8 read-write oneToClear SHIFTSDEN Shifter Status DMA Enable 0x30 32 read-write n 0x0 0x0 SSDE Shifter Status DMA Enable 0 8 read-write SHIFTSIEN Shifter Status Interrupt Enable 0x20 32 read-write n 0x0 0x0 SSIE Shifter Status Interrupt Enable 0 8 read-write SHIFTSTAT Shifter Status Register 0x10 32 read-write n 0x0 0x0 SSF Shifter Status Flag 0 8 read-write oneToClear SHIFTSTATE Shifter State Register 0x40 32 read-write n 0x0 0x0 STATE Current State Pointer 0 3 read-write TIMCFG0 Timer Configuration N Register 0x480 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMCFG1 Timer Configuration N Register 0x484 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMCFG2 Timer Configuration N Register 0x488 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMCFG3 Timer Configuration N Register 0x48C 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMCFG4 Timer Configuration N Register 0x490 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMCFG5 Timer Configuration N Register 0x494 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMCFG6 Timer Configuration N Register 0x498 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMCFG7 Timer Configuration N Register 0x49C 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMCFG[0] Timer Configuration N Register 0x900 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMCFG[1] Timer Configuration N Register 0xD84 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMCFG[2] Timer Configuration N Register 0x120C 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMCFG[3] Timer Configuration N Register 0x1698 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMCFG[4] Timer Configuration N Register 0x1B28 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMCFG[5] Timer Configuration N Register 0x1FBC 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMCFG[6] Timer Configuration N Register 0x2454 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMCFG[7] Timer Configuration N Register 0x28F0 32 read-write n 0x0 0x0 TIMDEC Timer Decrement 20 2 read-write TIMDEC_0 Decrement counter on FlexIO clock, Shift clock equals Timer output. 0 TIMDEC_1 Decrement counter on Trigger input (both edges), Shift clock equals Timer output. 0x1 TIMDEC_2 Decrement counter on Pin input (both edges), Shift clock equals Pin input. 0x2 TIMDEC_3 Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. 0x3 TIMDIS Timer Disable 12 3 read-write TIMDIS_0 Timer never disabled 0 TIMDIS_1 Timer disabled on Timer N-1 disable 0x1 TIMDIS_2 Timer disabled on Timer compare (upper 8-bits match and decrement) 0x2 TIMDIS_3 Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low 0x3 TIMDIS_4 Timer disabled on Pin rising or falling edge 0x4 TIMDIS_5 Timer disabled on Pin rising or falling edge provided Trigger is high 0x5 TIMDIS_6 Timer disabled on Trigger falling edge 0x6 TIMENA Timer Enable 8 3 read-write TIMENA_0 Timer always enabled 0 TIMENA_1 Timer enabled on Timer N-1 enable 0x1 TIMENA_2 Timer enabled on Trigger high 0x2 TIMENA_3 Timer enabled on Trigger high and Pin high 0x3 TIMENA_4 Timer enabled on Pin rising edge 0x4 TIMENA_5 Timer enabled on Pin rising edge and Trigger high 0x5 TIMENA_6 Timer enabled on Trigger rising edge 0x6 TIMENA_7 Timer enabled on Trigger rising or falling edge 0x7 TIMOUT Timer Output 24 2 read-write TIMOUT_0 Timer output is logic one when enabled and is not affected by timer reset 0 TIMOUT_1 Timer output is logic zero when enabled and is not affected by timer reset 0x1 TIMOUT_2 Timer output is logic one when enabled and on timer reset 0x2 TIMOUT_3 Timer output is logic zero when enabled and on timer reset 0x3 TIMRST Timer Reset 16 3 read-write TIMRST_0 Timer never reset 0 TIMRST_2 Timer reset on Timer Pin equal to Timer Output 0x2 TIMRST_3 Timer reset on Timer Trigger equal to Timer Output 0x3 TIMRST_4 Timer reset on Timer Pin rising edge 0x4 TIMRST_6 Timer reset on Trigger rising edge 0x6 TIMRST_7 Timer reset on Trigger rising or falling edge 0x7 TSTART Timer Start Bit 1 1 read-write TSTART_0 Start bit disabled 0 TSTART_1 Start bit enabled 0x1 TSTOP Timer Stop Bit 4 2 read-write TSTOP_0 Stop bit disabled 0 TSTOP_1 Stop bit is enabled on timer compare 0x1 TSTOP_2 Stop bit is enabled on timer disable 0x2 TSTOP_3 Stop bit is enabled on timer compare and timer disable 0x3 TIMCMP0 Timer Compare N Register 0x500 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP1 Timer Compare N Register 0x504 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP2 Timer Compare N Register 0x508 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP3 Timer Compare N Register 0x50C 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP4 Timer Compare N Register 0x510 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP5 Timer Compare N Register 0x514 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP6 Timer Compare N Register 0x518 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP7 Timer Compare N Register 0x51C 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP[0] Timer Compare N Register 0xA00 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP[1] Timer Compare N Register 0xF04 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP[2] Timer Compare N Register 0x140C 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP[3] Timer Compare N Register 0x1918 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP[4] Timer Compare N Register 0x1E28 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP[5] Timer Compare N Register 0x233C 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP[6] Timer Compare N Register 0x2854 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCMP[7] Timer Compare N Register 0x2D70 32 read-write n 0x0 0x0 CMP Timer Compare Value 0 16 read-write TIMCTL0 Timer Control N Register 0x400 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TIMCTL1 Timer Control N Register 0x404 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TIMCTL2 Timer Control N Register 0x408 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TIMCTL3 Timer Control N Register 0x40C 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TIMCTL4 Timer Control N Register 0x410 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TIMCTL5 Timer Control N Register 0x414 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TIMCTL6 Timer Control N Register 0x418 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TIMCTL7 Timer Control N Register 0x41C 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TIMCTL[0] Timer Control N Register 0x800 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TIMCTL[1] Timer Control N Register 0xC04 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TIMCTL[2] Timer Control N Register 0x100C 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TIMCTL[3] Timer Control N Register 0x1418 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TIMCTL[4] Timer Control N Register 0x1828 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TIMCTL[5] Timer Control N Register 0x1C3C 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TIMCTL[6] Timer Control N Register 0x2054 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TIMCTL[7] Timer Control N Register 0x2470 32 read-write n 0x0 0x0 PINCFG Timer Pin Configuration 16 2 read-write PINCFG_0 Timer pin output disabled 0 PINCFG_1 Timer pin open drain or bidirectional output enable 0x1 PINCFG_2 Timer pin bidirectional output data 0x2 PINCFG_3 Timer pin output 0x3 PINPOL Timer Pin Polarity 7 1 read-write PINPOL_0 Pin is active high 0 PINPOL_1 Pin is active low 0x1 PINSEL Timer Pin Select 8 5 read-write TIMOD Timer Mode 0 2 read-write TIMOD_0 Timer Disabled. 0 TIMOD_1 Dual 8-bit counters baud mode. 0x1 TIMOD_2 Dual 8-bit counters PWM high mode. 0x2 TIMOD_3 Single 16-bit counter mode. 0x3 TRGPOL Trigger Polarity 23 1 read-write TRGPOL_0 Trigger active high 0 TRGPOL_1 Trigger active low 0x1 TRGSEL Trigger Select 24 6 read-write TRGSRC Trigger Source 22 1 read-write TRGSRC_0 External trigger selected 0 TRGSRC_1 Internal trigger selected 0x1 TIMIEN Timer Interrupt Enable Register 0x28 32 read-write n 0x0 0x0 TEIE Timer Status Interrupt Enable 0 8 read-write TIMSTAT Timer Status Register 0x18 32 read-write n 0x0 0x0 TSF Timer Status Flags 0 8 read-write oneToClear VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only FEATURE_0 Standard features implemented. 0 FEATURE_1 Supports state, logic and parallel modes. 0x1 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only FTFE Flash FTFE 0x0 0x0 0x54 registers n FTFE_Command_Complete 20 FTFE_Read_Collision 21 FACSN Primary Flash Access Segment Number Register 0x2D 8 read-only n 0x0 0x0 NUMSG Number of Segments Indicator 0 8 read-only NUMSG_48 Primary Program flash memory is divided into 48 segments (768 Kbytes, 1.5 Mbytes) 0x30 NUMSG_64 Primary Program flash memory is divided into 64 segments (512 Kbytes, 1 Mbyte, 2 Mbytes) 0x40 FACSNS Secondary Flash Access Segment Number Register 0x2F 8 read-only n 0x0 0x0 NUMSG_S Number of Segments Indicator 0 8 read-only NUMSG_S_16 Secondary Program flash memory is divided into 16 segments 0x10 FACSS Primary Flash Access Segment Size Register 0x2C 8 read-only n 0x0 0x0 SGSIZE Segment Size 0 8 read-only FACSSS Secondary Flash Access Segment Size Register 0x2E 8 read-only n 0x0 0x0 SGSIZE_S Segment Size 0 8 read-only FCCOB0 Flash Common Command Object Registers 0x7 8 read-write n 0x0 0x0 CCOBn CCOBn 0 8 read-write FCCOB1 Flash Common Command Object Registers 0x6 8 read-write n 0x0 0x0 CCOBn CCOBn 0 8 read-write FCCOB2 Flash Common Command Object Registers 0x5 8 read-write n 0x0 0x0 CCOBn CCOBn 0 8 read-write FCCOB3 Flash Common Command Object Registers 0x4 8 read-write n 0x0 0x0 CCOBn CCOBn 0 8 read-write FCCOB4 Flash Common Command Object Registers 0xB 8 read-write n 0x0 0x0 CCOBn CCOBn 0 8 read-write FCCOB5 Flash Common Command Object Registers 0xA 8 read-write n 0x0 0x0 CCOBn CCOBn 0 8 read-write FCCOB6 Flash Common Command Object Registers 0x9 8 read-write n 0x0 0x0 CCOBn CCOBn 0 8 read-write FCCOB7 Flash Common Command Object Registers 0x8 8 read-write n 0x0 0x0 CCOBn CCOBn 0 8 read-write FCCOB8 Flash Common Command Object Registers 0xF 8 read-write n 0x0 0x0 CCOBn CCOBn 0 8 read-write FCCOB9 Flash Common Command Object Registers 0xE 8 read-write n 0x0 0x0 CCOBn CCOBn 0 8 read-write FCCOBA Flash Common Command Object Registers 0xD 8 read-write n 0x0 0x0 CCOBn CCOBn 0 8 read-write FCCOBB Flash Common Command Object Registers 0xC 8 read-write n 0x0 0x0 CCOBn CCOBn 0 8 read-write FCNFG Flash Configuration Register 0x1 8 read-write n 0x0 0x0 CCIE Command Complete Interrupt Enable 7 1 read-write CCIE_0 Command complete interrupt disabled 0 CCIE_1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. 0x1 CRCRDY CRC Ready 2 1 read-only CRCRDY_0 Programming acceleration RAM is not available for CRC operations 0 CRCRDY_1 Programming acceleration RAM is available for CRC operations 0x1 ERSAREQ Erase All Request 5 1 read-only ERSAREQ_0 No request or request complete 0 ERSAREQ_1 Request to: (1) run the Erase All Blocks command, (2) verify the erased state, (3) program the security byte in the Flash Configuration Field to the unsecure state, and (4) release MCU security by setting the FSEC[SEC] field to the unsecure state. 0x1 ERSSUSP Erase Suspend 4 1 read-write ERSSUSP_0 No suspend requested 0 ERSSUSP_1 Suspend the current Erase Flash Sector command execution 0x1 RAMRDY RAM Ready 1 1 read-only RAMRDY_0 Programming acceleration RAM is not available 0 RAMRDY_1 Programming acceleration RAM is available 0x1 RDCOLLIE Read Collision Error Interrupt Enable 6 1 read-write RDCOLLIE_0 Read collision error interrupt disabled 0 RDCOLLIE_1 Read collision error interrupt enabled. An interrupt request is generated whenever a flash read collision error is detected (see the description of FSTAT[RDCOLERR]). 0x1 SWAP Swap 3 1 read-only SWAP_0 Program flash 0 block is located at relative address 0x0000 0 SWAP_1 Program flash 1 block is located at relative address 0x0000 0x1 FOPT0 Flash Option Registers 0x13 8 read-only n 0x0 0x0 OPT Nonvolatile Option 0 8 read-only FOPT1 Flash Option Registers 0x12 8 read-only n 0x0 0x0 OPT Nonvolatile Option 0 8 read-only FOPT2 Flash Option Registers 0x11 8 read-only n 0x0 0x0 OPT Nonvolatile Option 0 8 read-only FOPT3 Flash Option Registers 0x10 8 read-only n 0x0 0x0 OPT Nonvolatile Option 0 8 read-only FPROTH0 Primary Program Flash Protection Registers 0x1B 8 read-write n 0x0 0x0 PROT Primary Program Flash Region Protect 0 8 read-write FPROTH1 Primary Program Flash Protection Registers 0x1A 8 read-write n 0x0 0x0 PROT Primary Program Flash Region Protect 0 8 read-write FPROTH2 Primary Program Flash Protection Registers 0x19 8 read-write n 0x0 0x0 PROT Primary Program Flash Region Protect 0 8 read-write FPROTH3 Primary Program Flash Protection Registers 0x18 8 read-write n 0x0 0x0 PROT Primary Program Flash Region Protect 0 8 read-write FPROTL0 Primary Program Flash Protection Registers 0x1F 8 read-write n 0x0 0x0 PROT Primary Program Flash Region Protect 0 8 read-write FPROTL1 Primary Program Flash Protection Registers 0x1E 8 read-write n 0x0 0x0 PROT Primary Program Flash Region Protect 0 8 read-write FPROTL2 Primary Program Flash Protection Registers 0x1D 8 read-write n 0x0 0x0 PROT Primary Program Flash Region Protect 0 8 read-write FPROTL3 Primary Program Flash Protection Registers 0x1C 8 read-write n 0x0 0x0 PROT Primary Program Flash Region Protect 0 8 read-write FPROTSH Secondary Program Flash Protection Registers 0x25 8 read-write n 0x0 0x0 PROTS Secondary Program Flash Region Protect 0 8 read-write FPROTSL Secondary Program Flash Protection Registers 0x24 8 read-write n 0x0 0x0 PROTS Secondary Program Flash Region Protect 0 8 read-write FSEC Flash Security Register 0x2 8 read-only n 0x0 0x0 FSLACC Factory Security Level Access Code 2 2 read-only FSLACC_0 Factory access granted 0 FSLACC_1 Factory access denied 0x1 FSLACC_2 Factory access denied 0x2 FSLACC_3 Factory access granted 0x3 KEYEN Backdoor Key Security Enable 6 2 read-only KEYEN_0 Backdoor key access disabled 0 KEYEN_1 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) 0x1 KEYEN_2 Backdoor key access enabled 0x2 KEYEN_3 Backdoor key access disabled 0x3 MEEN Mass Erase Enable Bits 4 2 read-only MEEN_0 Mass erase is enabled 0 MEEN_1 Mass erase is enabled 0x1 MEEN_2 no description available 0x2 MEEN_3 Mass erase is enabled 0x3 SEC Flash Security 0 2 read-only SEC_0 no description available 0 SEC_1 no description available 0x1 SEC_2 MCU security status is unsecure (The standard shipping condition of the flash module is unsecure.) 0x2 SEC_3 no description available 0x3 FSTAT Flash Status Register 0x0 8 read-write n 0x0 0x0 ACCERR Flash Access Error Flag 5 1 read-write oneToClear ACCERR_0 No access error detected 0 ACCERR_1 Access error detected 0x1 CCIF Command Complete Interrupt Flag 7 1 read-write oneToClear CCIF_0 no description available 0 CCIF_1 no description available 0x1 FPVIOL Flash Protection Violation Flag 4 1 read-write oneToClear FPVIOL_0 No protection violation detected 0 FPVIOL_1 Protection violation detected 0x1 MGSTAT0 Memory Controller Command Completion Status Flag 0 1 read-only RDCOLERR Flash Read Collision Error Flag 6 1 read-write oneToClear RDCOLERR_0 No collision error detected 0 RDCOLERR_1 Collision error detected 0x1 FSTDBY Flash Standby Register 0x53 8 read-write n 0x0 0x0 STDBY0 Standy Mode for Flash Block 0 0 1 read-write STDBY0_0 Standby mode not enabled for flash block 0 0 STDBY0_1 If STDBYDIS is clear, standby mode is enabled for flash block 0 (when SWAP=0/1, flash block 1/0 is the inactive block) 0x1 STDBY1 Standy Mode for Flash Block 1 1 1 read-write STDBY1_0 Standby mode not enabled for flash block 1 0 STDBY1_1 If STDBYDIS is clear, standby mode is enabled for flash block 1 (when SWAP=0/1, flash block 1/0 is the inactive block) 0x1 STDBY2 Standy Mode for Flash Block 2 2 1 read-write STDBY2_0 Standby mode not enabled for flash block 2 0 STDBY2_1 If STDBYDIS is clear, standby mode is enabled for flash block 2 0x1 FSTDBYCTL Flash Standby Control Register 0x52 8 read-only n 0x0 0x0 STDBYDIS Standy Mode Disable 0 1 read-only STDBYDIS_0 Standby mode enabled for flash blocks selected by STDBYx 0 STDBYDIS_1 Standby mode disabled (STDBYx ignored) 0x1 SACCH0 Primary Supervisor-only Access Registers 0x3B 8 read-only n 0x0 0x0 SA Primary Supervisor-only access control 0 8 read-only SACCH1 Primary Supervisor-only Access Registers 0x3A 8 read-only n 0x0 0x0 SA Primary Supervisor-only access control 0 8 read-only SACCH2 Primary Supervisor-only Access Registers 0x39 8 read-only n 0x0 0x0 SA Primary Supervisor-only access control 0 8 read-only SACCH3 Primary Supervisor-only Access Registers 0x38 8 read-only n 0x0 0x0 SA Primary Supervisor-only access control 0 8 read-only SACCL0 Primary Supervisor-only Access Registers 0x3F 8 read-only n 0x0 0x0 SA Primary Supervisor-only access control 0 8 read-only SACCL1 Primary Supervisor-only Access Registers 0x3E 8 read-only n 0x0 0x0 SA Primary Supervisor-only access control 0 8 read-only SACCL2 Primary Supervisor-only Access Registers 0x3D 8 read-only n 0x0 0x0 SA Primary Supervisor-only access control 0 8 read-only SACCL3 Primary Supervisor-only Access Registers 0x3C 8 read-only n 0x0 0x0 SA Primary Supervisor-only access control 0 8 read-only SACCSH Secondary Supervisor-only Access Registers 0x4D 8 read-only n 0x0 0x0 SA_S Secondary Supervisor-only access control 0 8 read-only SACCSL Secondary Supervisor-only Access Registers 0x4C 8 read-only n 0x0 0x0 SA_S Secondary Supervisor-only access control 0 8 read-only XACCH0 Primary Execute-only Access Registers 0x33 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only XACCH1 Primary Execute-only Access Registers 0x32 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only XACCH2 Primary Execute-only Access Registers 0x31 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only XACCH3 Primary Execute-only Access Registers 0x30 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only XACCL0 Primary Execute-only Access Registers 0x37 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only XACCL1 Primary Execute-only Access Registers 0x36 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only XACCL2 Primary Execute-only Access Registers 0x35 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only XACCL3 Primary Execute-only Access Registers 0x34 8 read-only n 0x0 0x0 XA Execute-only access control 0 8 read-only XACCSH Secondary Execute-only Access Registers 0x45 8 read-only n 0x0 0x0 XA_S Execute-only access control 0 8 read-only XACCSL Secondary Execute-only Access Registers 0x44 8 read-only n 0x0 0x0 XA_S Execute-only access control 0 8 read-only GPIOA GPIO GPIO 0x0 0x0 0x18 registers n PORTA 48 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only GPIOB GPIO GPIO 0x0 0x0 0x18 registers n PORTB 49 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only GPIOC GPIO GPIO 0x0 0x0 0x18 registers n PORTC 50 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only GPIOD GPIO GPIO 0x0 0x0 0x18 registers n PORTD 51 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only GPIOE GPIO GPIO 0x0 0x0 0x18 registers n PORTE 64 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port Data Direction 0 32 read-write PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only I2S0 I2S I2S0 0x0 0x0 0xE4 registers n I2S0 39 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 DATALINE Number of Datalines 0 4 read-only FIFO FIFO Size 8 4 read-only FRAME Frame Size 16 4 read-only RCR1 SAI Receive Configuration 1 Register 0x8C 32 read-write n 0x0 0x0 RFW Receive FIFO Watermark 0 3 read-write RCR2 SAI Receive Configuration 2 Register 0x90 32 read-write n 0x0 0x0 BCD Bit Clock Direction 24 1 read-write BCD_0 Bit clock is generated externally in Slave mode. 0 BCD_1 Bit clock is generated internally in Master mode. 0x1 BCI Bit Clock Input 28 1 read-write BCI_0 No effect. 0 BCI_1 Internal logic is clocked as if bit clock was externally generated. 0x1 BCP Bit Clock Polarity 25 1 read-write BCP_0 Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0 BCP_1 Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. 0x1 BCS Bit Clock Swap 29 1 read-write BCS_0 Use the normal bit clock source. 0 BCS_1 Swap the bit clock source. 0x1 DIV Bit Clock Divide 0 8 read-write MSEL MCLK Select 26 2 read-write MSEL_0 Bus Clock selected. 0 MSEL_1 Master Clock (MCLK) 1 option selected. 0x1 MSEL_2 Master Clock (MCLK) 2 option selected. 0x2 MSEL_3 Master Clock (MCLK) 3 option selected. 0x3 SYNC Synchronous Mode 30 2 read-write SYNC_0 Asynchronous mode. 0 SYNC_1 Synchronous with transmitter. 0x1 SYNC_2 Synchronous with another SAI receiver. 0x2 SYNC_3 Synchronous with another SAI transmitter. 0x3 RCR3 SAI Receive Configuration 3 Register 0x94 32 read-write n 0x0 0x0 CFR Channel FIFO Reset 24 2 write-only RCE Receive Channel Enable 16 2 read-write WDFL Word Flag Configuration 0 5 read-write RCR4 SAI Receive Configuration 4 Register 0x98 32 read-write n 0x0 0x0 FCOMB FIFO Combine Mode 26 2 read-write FCOMB_0 FIFO combine mode disabled. 0 FCOMB_1 FIFO combine mode enabled on FIFO writes (from receive shift registers). 0x1 FCOMB_2 FIFO combine mode enabled on FIFO reads (by software). 0x2 FCOMB_3 FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). 0x3 FCONT FIFO Continue on Error 28 1 read-write FCONT_0 On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0 FCONT_1 On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. 0x1 FPACK FIFO Packing Mode 24 2 read-write FPACK_0 FIFO packing is disabled 0 FPACK_2 8-bit FIFO packing is enabled 0x2 FPACK_3 16-bit FIFO packing is enabled 0x3 FRSZ Frame Size 16 5 read-write FSD Frame Sync Direction 0 1 read-write FSD_0 Frame Sync is generated externally in Slave mode. 0 FSD_1 Frame Sync is generated internally in Master mode. 0x1 FSE Frame Sync Early 3 1 read-write FSE_0 Frame sync asserts with the first bit of the frame. 0 FSE_1 Frame sync asserts one bit before the first bit of the frame. 0x1 FSP Frame Sync Polarity 1 1 read-write FSP_0 Frame sync is active high. 0 FSP_1 Frame sync is active low. 0x1 MF MSB First 4 1 read-write MF_0 LSB is received first. 0 MF_1 MSB is received first. 0x1 ONDEM On Demand Mode 2 1 read-write ONDEM_0 Internal frame sync is generated continuously. 0 ONDEM_1 Internal frame sync is generated when the FIFO warning flag is clear. 0x1 SYWD Sync Width 8 5 read-write RCR5 SAI Receive Configuration 5 Register 0x9C 32 read-write n 0x0 0x0 FBT First Bit Shifted 8 5 read-write W0W Word 0 Width 16 5 read-write WNW Word N Width 24 5 read-write RCSR SAI Receive Control Register 0x88 32 read-write n 0x0 0x0 BCE Bit Clock Enable 28 1 read-write BCE_0 Receive bit clock is disabled. 0 BCE_1 Receive bit clock is enabled. 0x1 DBGE Debug Enable 29 1 read-write DBGE_0 Receiver is disabled in Debug mode, after completing the current frame. 0 DBGE_1 Receiver is enabled in Debug mode. 0x1 FEF FIFO Error Flag 18 1 read-write oneToClear FEF_0 Receive overflow not detected. 0 FEF_1 Receive overflow detected. 0x1 FEIE FIFO Error Interrupt Enable 10 1 read-write FEIE_0 Disables the interrupt. 0 FEIE_1 Enables the interrupt. 0x1 FR FIFO Reset 25 1 write-only FR_0 No effect. 0 FR_1 FIFO reset. 0x1 FRDE FIFO Request DMA Enable 0 1 read-write FRDE_0 Disables the DMA request. 0 FRDE_1 Enables the DMA request. 0x1 FRF FIFO Request Flag 16 1 read-only FRF_0 Receive FIFO watermark not reached. 0 FRF_1 Receive FIFO watermark has been reached. 0x1 FRIE FIFO Request Interrupt Enable 8 1 read-write FRIE_0 Disables the interrupt. 0 FRIE_1 Enables the interrupt. 0x1 FWDE FIFO Warning DMA Enable 1 1 read-write FWDE_0 Disables the DMA request. 0 FWDE_1 Enables the DMA request. 0x1 FWF FIFO Warning Flag 17 1 read-only FWF_0 No enabled receive FIFO is full. 0 FWF_1 Enabled receive FIFO is full. 0x1 FWIE FIFO Warning Interrupt Enable 9 1 read-write FWIE_0 Disables the interrupt. 0 FWIE_1 Enables the interrupt. 0x1 RE Receiver Enable 31 1 read-write RE_0 Receiver is disabled. 0 RE_1 Receiver is enabled, or receiver has been disabled and has not yet reached end of frame. 0x1 SEF Sync Error Flag 19 1 read-write oneToClear SEF_0 Sync error not detected. 0 SEF_1 Frame sync error detected. 0x1 SEIE Sync Error Interrupt Enable 11 1 read-write SEIE_0 Disables interrupt. 0 SEIE_1 Enables interrupt. 0x1 SR Software Reset 24 1 read-write SR_0 No effect. 0 SR_1 Software reset. 0x1 STOPE Stop Enable 30 1 read-write STOPE_0 Receiver disabled in Stop mode. 0 STOPE_1 Receiver enabled in Stop mode. 0x1 WSF Word Start Flag 20 1 read-write oneToClear WSF_0 Start of word not detected. 0 WSF_1 Start of word detected. 0x1 WSIE Word Start Interrupt Enable 12 1 read-write WSIE_0 Disables interrupt. 0 WSIE_1 Enables interrupt. 0x1 RDR0 SAI Receive Data Register 0xA0 32 read-only n 0x0 0x0 RDR Receive Data Register 0 32 read-only RDR1 SAI Receive Data Register 0xA4 32 read-only n 0x0 0x0 RDR Receive Data Register 0 32 read-only RDR[0] SAI Receive Data Register 0x140 32 read-only n 0x0 0x0 RDR Receive Data Register 0 32 read-only RDR[1] SAI Receive Data Register 0x1E4 32 read-only n 0x0 0x0 RDR Receive Data Register 0 32 read-only RFR0 SAI Receive FIFO Register 0xC0 32 read-only n 0x0 0x0 RCP Receive Channel Pointer 15 1 read-only RCP_0 No effect. 0 RCP_1 FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. 0x1 RFP Read FIFO Pointer 0 4 read-only WFP Write FIFO Pointer 16 4 read-only RFR1 SAI Receive FIFO Register 0xC4 32 read-only n 0x0 0x0 RCP Receive Channel Pointer 15 1 read-only RCP_0 No effect. 0 RCP_1 FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. 0x1 RFP Read FIFO Pointer 0 4 read-only WFP Write FIFO Pointer 16 4 read-only RFR[0] SAI Receive FIFO Register 0x180 32 read-only n 0x0 0x0 RCP Receive Channel Pointer 15 1 read-only RCP_0 No effect. 0 RCP_1 FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. 0x1 RFP Read FIFO Pointer 0 4 read-only WFP Write FIFO Pointer 16 4 read-only RFR[1] SAI Receive FIFO Register 0x244 32 read-only n 0x0 0x0 RCP Receive Channel Pointer 15 1 read-only RCP_0 No effect. 0 RCP_1 FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. 0x1 RFP Read FIFO Pointer 0 4 read-only WFP Write FIFO Pointer 16 4 read-only RMR SAI Receive Mask Register 0xE0 32 read-write n 0x0 0x0 RWM Receive Word Mask 0 32 read-write RWM_0 Word N is enabled. 0 RWM_1 Word N is masked. 0x1 TCR1 SAI Transmit Configuration 1 Register 0xC 32 read-write n 0x0 0x0 TFW Transmit FIFO Watermark 0 3 read-write TCR2 SAI Transmit Configuration 2 Register 0x10 32 read-write n 0x0 0x0 BCD Bit Clock Direction 24 1 read-write BCD_0 Bit clock is generated externally in Slave mode. 0 BCD_1 Bit clock is generated internally in Master mode. 0x1 BCI Bit Clock Input 28 1 read-write BCI_0 No effect. 0 BCI_1 Internal logic is clocked as if bit clock was externally generated. 0x1 BCP Bit Clock Polarity 25 1 read-write BCP_0 Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 0 BCP_1 Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. 0x1 BCS Bit Clock Swap 29 1 read-write BCS_0 Use the normal bit clock source. 0 BCS_1 Swap the bit clock source. 0x1 DIV Bit Clock Divide 0 8 read-write MSEL MCLK Select 26 2 read-write MSEL_0 Bus Clock selected. 0 MSEL_1 Master Clock (MCLK) 1 option selected. 0x1 MSEL_2 Master Clock (MCLK) 2 option selected. 0x2 MSEL_3 Master Clock (MCLK) 3 option selected. 0x3 SYNC Synchronous Mode 30 2 read-write SYNC_0 Asynchronous mode. 0 SYNC_1 Synchronous with receiver. 0x1 SYNC_2 Synchronous with another SAI transmitter. 0x2 SYNC_3 Synchronous with another SAI receiver. 0x3 TCR3 SAI Transmit Configuration 3 Register 0x14 32 read-write n 0x0 0x0 CFR Channel FIFO Reset 24 2 write-only TCE Transmit Channel Enable 16 2 read-write WDFL Word Flag Configuration 0 5 read-write TCR4 SAI Transmit Configuration 4 Register 0x18 32 read-write n 0x0 0x0 CHMOD Channel Mode 5 1 read-write CHMOD_0 TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. 0 CHMOD_1 Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. 0x1 FCOMB FIFO Combine Mode 26 2 read-write FCOMB_0 FIFO combine mode disabled. 0 FCOMB_1 FIFO combine mode enabled on FIFO reads (from transmit shift registers). 0x1 FCOMB_2 FIFO combine mode enabled on FIFO writes (by software). 0x2 FCOMB_3 FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). 0x3 FCONT FIFO Continue on Error 28 1 read-write FCONT_0 On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared. 0 FCONT_1 On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. 0x1 FPACK FIFO Packing Mode 24 2 read-write FPACK_0 FIFO packing is disabled 0 FPACK_2 8-bit FIFO packing is enabled 0x2 FPACK_3 16-bit FIFO packing is enabled 0x3 FRSZ Frame size 16 5 read-write FSD Frame Sync Direction 0 1 read-write FSD_0 Frame sync is generated externally in Slave mode. 0 FSD_1 Frame sync is generated internally in Master mode. 0x1 FSE Frame Sync Early 3 1 read-write FSE_0 Frame sync asserts with the first bit of the frame. 0 FSE_1 Frame sync asserts one bit before the first bit of the frame. 0x1 FSP Frame Sync Polarity 1 1 read-write FSP_0 Frame sync is active high. 0 FSP_1 Frame sync is active low. 0x1 MF MSB First 4 1 read-write MF_0 LSB is transmitted first. 0 MF_1 MSB is transmitted first. 0x1 ONDEM On Demand Mode 2 1 read-write ONDEM_0 Internal frame sync is generated continuously. 0 ONDEM_1 Internal frame sync is generated when the FIFO warning flag is clear. 0x1 SYWD Sync Width 8 5 read-write TCR5 SAI Transmit Configuration 5 Register 0x1C 32 read-write n 0x0 0x0 FBT First Bit Shifted 8 5 read-write W0W Word 0 Width 16 5 read-write WNW Word N Width 24 5 read-write TCSR SAI Transmit Control Register 0x8 32 read-write n 0x0 0x0 BCE Bit Clock Enable 28 1 read-write BCE_0 Transmit bit clock is disabled. 0 BCE_1 Transmit bit clock is enabled. 0x1 DBGE Debug Enable 29 1 read-write DBGE_0 Transmitter is disabled in Debug mode, after completing the current frame. 0 DBGE_1 Transmitter is enabled in Debug mode. 0x1 FEF FIFO Error Flag 18 1 read-write oneToClear FEF_0 Transmit underrun not detected. 0 FEF_1 Transmit underrun detected. 0x1 FEIE FIFO Error Interrupt Enable 10 1 read-write FEIE_0 Disables the interrupt. 0 FEIE_1 Enables the interrupt. 0x1 FR FIFO Reset 25 1 write-only FR_0 No effect. 0 FR_1 FIFO reset. 0x1 FRDE FIFO Request DMA Enable 0 1 read-write FRDE_0 Disables the DMA request. 0 FRDE_1 Enables the DMA request. 0x1 FRF FIFO Request Flag 16 1 read-only FRF_0 Transmit FIFO watermark has not been reached. 0 FRF_1 Transmit FIFO watermark has been reached. 0x1 FRIE FIFO Request Interrupt Enable 8 1 read-write FRIE_0 Disables the interrupt. 0 FRIE_1 Enables the interrupt. 0x1 FWDE FIFO Warning DMA Enable 1 1 read-write FWDE_0 Disables the DMA request. 0 FWDE_1 Enables the DMA request. 0x1 FWF FIFO Warning Flag 17 1 read-only FWF_0 No enabled transmit FIFO is empty. 0 FWF_1 Enabled transmit FIFO is empty. 0x1 FWIE FIFO Warning Interrupt Enable 9 1 read-write FWIE_0 Disables the interrupt. 0 FWIE_1 Enables the interrupt. 0x1 SEF Sync Error Flag 19 1 read-write oneToClear SEF_0 Sync error not detected. 0 SEF_1 Frame sync error detected. 0x1 SEIE Sync Error Interrupt Enable 11 1 read-write SEIE_0 Disables interrupt. 0 SEIE_1 Enables interrupt. 0x1 SR Software Reset 24 1 read-write SR_0 No effect. 0 SR_1 Software reset. 0x1 STOPE Stop Enable 30 1 read-write STOPE_0 Transmitter disabled in Stop mode. 0 STOPE_1 Transmitter enabled in Stop mode. 0x1 TE Transmitter Enable 31 1 read-write TE_0 Transmitter is disabled. 0 TE_1 Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame. 0x1 WSF Word Start Flag 20 1 read-write oneToClear WSF_0 Start of word not detected. 0 WSF_1 Start of word detected. 0x1 WSIE Word Start Interrupt Enable 12 1 read-write WSIE_0 Disables interrupt. 0 WSIE_1 Enables interrupt. 0x1 TDR0 SAI Transmit Data Register 0x20 32 write-only n 0x0 0x0 TDR Transmit Data Register 0 32 write-only TDR1 SAI Transmit Data Register 0x24 32 write-only n 0x0 0x0 TDR Transmit Data Register 0 32 write-only TDR[0] SAI Transmit Data Register 0x40 32 write-only n 0x0 0x0 TDR Transmit Data Register 0 32 write-only TDR[1] SAI Transmit Data Register 0x64 32 write-only n 0x0 0x0 TDR Transmit Data Register 0 32 write-only TFR0 SAI Transmit FIFO Register 0x40 32 read-only n 0x0 0x0 RFP Read FIFO Pointer 0 4 read-only WCP Write Channel Pointer 31 1 read-only WCP_0 No effect. 0 WCP_1 FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. 0x1 WFP Write FIFO Pointer 16 4 read-only TFR1 SAI Transmit FIFO Register 0x44 32 read-only n 0x0 0x0 RFP Read FIFO Pointer 0 4 read-only WCP Write Channel Pointer 31 1 read-only WCP_0 No effect. 0 WCP_1 FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. 0x1 WFP Write FIFO Pointer 16 4 read-only TFR[0] SAI Transmit FIFO Register 0x80 32 read-only n 0x0 0x0 RFP Read FIFO Pointer 0 4 read-only WCP Write Channel Pointer 31 1 read-only WCP_0 No effect. 0 WCP_1 FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. 0x1 WFP Write FIFO Pointer 16 4 read-only TFR[1] SAI Transmit FIFO Register 0xC4 32 read-only n 0x0 0x0 RFP Read FIFO Pointer 0 4 read-only WCP Write Channel Pointer 31 1 read-only WCP_0 No effect. 0 WCP_1 FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write. 0x1 WFP Write FIFO Pointer 16 4 read-only TMR SAI Transmit Mask Register 0x60 32 read-write n 0x0 0x0 TWM Transmit Word Mask 0 32 read-write TWM_0 Word N is enabled. 0 TWM_1 Word N is masked. The transmit data pins are tri-stated or drive zero when masked. 0x1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only FEATURE_0 Standard feature set. 0 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LLWU0 LLWU LLWU0 0x0 0x0 0x5C registers n LLWU0 22 DE Module DMA/Trigger Enable register 0x1C 32 read-write n 0x0 0x0 Reserved3 DMA/Trigger wakeup enable for module n 3 1 read-only Reserved3_0 Internal module request not enabled as a DMA/Trigger wakeup source 0 Reserved3_1 Internal module request enabled as a DMA/Trigger wakeup source 0x1 Reserved7 DMA/Trigger wakeup enable for module n 7 1 read-only Reserved7_0 Internal module request not enabled as a DMA/Trigger wakeup source 0 Reserved7_1 Internal module request enabled as a DMA/Trigger wakeup source 0x1 WUDE0 DMA/Trigger wakeup enable for module n 0 1 read-write WUDE0_0 Internal module request not enabled as a DMA/Trigger wakeup source 0 WUDE0_1 Internal module request enabled as a DMA/Trigger wakeup source 0x1 WUDE1 DMA/Trigger wakeup enable for module n 1 1 read-write WUDE1_0 Internal module request not enabled as a DMA/Trigger wakeup source 0 WUDE1_1 Internal module request enabled as a DMA/Trigger wakeup source 0x1 WUDE2 DMA/Trigger wakeup enable for module n 2 1 read-write WUDE2_0 Internal module request not enabled as a DMA/Trigger wakeup source 0 WUDE2_1 Internal module request enabled as a DMA/Trigger wakeup source 0x1 WUDE4 DMA/Trigger wakeup enable for module n 4 1 read-write WUDE4_0 Internal module request not enabled as a DMA/Trigger wakeup source 0 WUDE4_1 Internal module request enabled as a DMA/Trigger wakeup source 0x1 WUDE5 DMA/Trigger wakeup enable for module n 5 1 read-write WUDE5_0 Internal module request not enabled as a DMA/Trigger wakeup source 0 WUDE5_1 Internal module request enabled as a DMA/Trigger wakeup source 0x1 WUDE6 DMA/Trigger wakeup enable for module n 6 1 read-write WUDE6_0 Internal module request not enabled as a DMA/Trigger wakeup source 0 WUDE6_1 Internal module request enabled as a DMA/Trigger wakeup source 0x1 FDC Pin Filter DMA/Trigger Configuration register 0x48 32 read-write n 0x0 0x0 FILTC1 Filter configuration for FILT1 0 2 read-write FILTC1_0 Filter output configured as interrupt 0 FILTC1_1 Filter output configured as DMA request 0x1 FILTC1_2 Filter output configured as trigger event 0x2 FILTC2 Filter configuration for FILT2 2 2 read-write FILTC2_0 Filter output configured as interrupt 0 FILTC2_1 Filter output configured as DMA request 0x1 FILTC2_2 Filter output configured as trigger event 0x2 FILT Pin Filter register 0x30 32 read-write n 0x0 0x0 FILTE1 Filter 1 Enable 5 2 read-write FILTE1_0 Filter disabled 0 FILTE1_1 Filter posedge detect enabled when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 FILTE1_2 Filter negedge detect enabled when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 FILTE1_3 Filter any edge detect enabled when configured as interrupt/DMA request 0x3 FILTE2 Filter 2 Enable 13 2 read-write FILTE2_0 Filter disabled 0 FILTE2_1 Filter posedge detect enabled when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 FILTE2_2 Filter negedge detect enabled when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 FILTE2_3 Filter any edge detect enabled when configured as interrupt/DMA request 0x3 FILTF1 Filter 1 Flag 7 1 read-write oneToClear FILTF1_0 Pin Filter 1 was not a wakeup source 0 FILTF1_1 Pin Filter 1 was a wakeup source 0x1 FILTF2 Filter 2 Flag 15 1 read-write oneToClear FILTF2_0 Pin Filter 2 was not a wakeup source 0 FILTF2_1 Pin Filter 2 was a wakeup source 0x1 FILTSEL1 Filter 1 Pin Select 0 5 read-write FILTSEL1_0 Select LLWU_P0 for filter 0 FILTSEL1_31 Select LLWU_P31 for filter 0x1F FILTSEL2 Filter 2 Pin Select 8 5 read-write FILTSEL2_0 Select LLWU_P0 for filter 0 FILTSEL2_31 Select LLWU_P31 for filter 0x1F FMC Pin Filter Mode Configuration register 0x58 32 read-write n 0x0 0x0 FILTM1 Filter Mode for FILT1 0 1 read-write FILTM1_0 External input pin filter detection active only during LLS/VLLS mode 0 FILTM1_1 External input pin filter detection active during all power modes 0x1 FILTM2 Filter Mode for FILT2 1 1 read-write FILTM2_0 External input pin filter detection active only during LLS/VLLS mode 0 FILTM2_1 External input pin filter detection active during all power modes 0x1 ME Module Interrupt Enable register 0x18 32 read-write n 0x0 0x0 Reserved3 Wakeup module enable for module n 3 1 read-only Reserved3_0 Internal module flag not used as wakeup source 0 Reserved3_1 Internal module flag used as wakeup source 0x1 Reserved4 Wakeup module enable for module n 4 1 read-only Reserved4_0 Internal module flag not used as wakeup source 0 Reserved4_1 Internal module flag used as wakeup source 0x1 WUME0 Wakeup module enable for module n 0 1 read-write WUME0_0 Internal module flag not used as wakeup source 0 WUME0_1 Internal module flag used as wakeup source 0x1 WUME1 Wakeup module enable for module n 1 1 read-write WUME1_0 Internal module flag not used as wakeup source 0 WUME1_1 Internal module flag used as wakeup source 0x1 WUME2 Wakeup module enable for module n 2 1 read-write WUME2_0 Internal module flag not used as wakeup source 0 WUME2_1 Internal module flag used as wakeup source 0x1 WUME5 Wakeup module enable for module n 5 1 read-write WUME5_0 Internal module flag not used as wakeup source 0 WUME5_1 Internal module flag used as wakeup source 0x1 WUME6 Wakeup module enable for module n 6 1 read-write WUME6_0 Internal module flag not used as wakeup source 0 WUME6_1 Internal module flag used as wakeup source 0x1 WUME7 Wakeup module enable for module n 7 1 read-write WUME7_0 Internal module flag not used as wakeup source 0 WUME7_1 Internal module flag used as wakeup source 0x1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 DMAS DMA Number 8 8 read-only FILTERS Filter Number 0 8 read-only MODULES Module Number 16 8 read-only PINS Pin Number 24 8 read-only PDC1 Pin DMA/Trigger Configuration 1 register 0x38 32 read-write n 0x0 0x0 WUPDC0 Wakeup pin configuration for LLWU_Pn 0 2 read-write WUPDC0_0 External input pin configured as interrupt 0 WUPDC0_1 External input pin configured as DMA request 0x1 WUPDC0_2 External input pin configured as trigger event 0x2 WUPDC1 Wakeup pin configuration for LLWU_Pn 2 2 read-write WUPDC1_0 External input pin configured as interrupt 0 WUPDC1_1 External input pin configured as DMA request 0x1 WUPDC1_2 External input pin configured as trigger event 0x2 WUPDC10 Wakeup pin configuration for LLWU_Pn 20 2 read-write WUPDC10_0 External input pin configured as interrupt 0 WUPDC10_1 External input pin configured as DMA request 0x1 WUPDC10_2 External input pin configured as trigger event 0x2 WUPDC11 Wakeup pin configuration for LLWU_Pn 22 2 read-write WUPDC11_0 External input pin configured as interrupt 0 WUPDC11_1 External input pin configured as DMA request 0x1 WUPDC11_2 External input pin configured as trigger event 0x2 WUPDC12 Wakeup pin configuration for LLWU_Pn 24 2 read-write WUPDC12_0 External input pin configured as interrupt 0 WUPDC12_1 External input pin configured as DMA request 0x1 WUPDC12_2 External input pin configured as trigger event 0x2 WUPDC13 Wakeup pin configuration for LLWU_Pn 26 2 read-write WUPDC13_0 External input pin configured as interrupt 0 WUPDC13_1 External input pin configured as DMA request 0x1 WUPDC13_2 External input pin configured as trigger event 0x2 WUPDC14 Wakeup pin configuration for LLWU_Pn 28 2 read-write WUPDC14_0 External input pin configured as interrupt 0 WUPDC14_1 External input pin configured as DMA request 0x1 WUPDC14_2 External input pin configured as trigger event 0x2 WUPDC15 Wakeup pin configuration for LLWU_Pn 30 2 read-write WUPDC15_0 External input pin configured as interrupt 0 WUPDC15_1 External input pin configured as DMA request 0x1 WUPDC15_2 External input pin configured as trigger event 0x2 WUPDC2 Wakeup pin configuration for LLWU_Pn 4 2 read-write WUPDC2_0 External input pin configured as interrupt 0 WUPDC2_1 External input pin configured as DMA request 0x1 WUPDC2_2 External input pin configured as trigger event 0x2 WUPDC3 Wakeup pin configuration for LLWU_Pn 6 2 read-write WUPDC3_0 External input pin configured as interrupt 0 WUPDC3_1 External input pin configured as DMA request 0x1 WUPDC3_2 External input pin configured as trigger event 0x2 WUPDC4 Wakeup pin configuration for LLWU_Pn 8 2 read-write WUPDC4_0 External input pin configured as interrupt 0 WUPDC4_1 External input pin configured as DMA request 0x1 WUPDC4_2 External input pin configured as trigger event 0x2 WUPDC5 Wakeup pin configuration for LLWU_Pn 10 2 read-write WUPDC5_0 External input pin configured as interrupt 0 WUPDC5_1 External input pin configured as DMA request 0x1 WUPDC5_2 External input pin configured as trigger event 0x2 WUPDC6 Wakeup pin configuration for LLWU_Pn 12 2 read-write WUPDC6_0 External input pin configured as interrupt 0 WUPDC6_1 External input pin configured as DMA request 0x1 WUPDC6_2 External input pin configured as trigger event 0x2 WUPDC7 Wakeup pin configuration for LLWU_Pn 14 2 read-write WUPDC7_0 External input pin configured as interrupt 0 WUPDC7_1 External input pin configured as DMA request 0x1 WUPDC7_2 External input pin configured as trigger event 0x2 WUPDC8 Wakeup pin configuration for LLWU_Pn 16 2 read-write WUPDC8_0 External input pin configured as interrupt 0 WUPDC8_1 External input pin configured as DMA request 0x1 WUPDC8_2 External input pin configured as trigger event 0x2 WUPDC9 Wakeup pin configuration for LLWU_Pn 18 2 read-write WUPDC9_0 External input pin configured as interrupt 0 WUPDC9_1 External input pin configured as DMA request 0x1 WUPDC9_2 External input pin configured as trigger event 0x2 PDC2 Pin DMA/Trigger Configuration 2 register 0x3C 32 read-write n 0x0 0x0 Reserved27 Wakeup pin configuration for LLWU_Pn 22 2 read-only Reserved27_0 External input pin configured as interrupt 0 Reserved27_1 External input pin configured as DMA request 0x1 Reserved27_2 External input pin configured as trigger event 0x2 Reserved28 Wakeup pin configuration for LLWU_Pn 24 2 read-only Reserved28_0 External input pin configured as interrupt 0 Reserved28_1 External input pin configured as DMA request 0x1 Reserved28_2 External input pin configured as trigger event 0x2 WUPDC16 Wakeup pin configuration for LLWU_Pn 0 2 read-write WUPDC16_0 External input pin configured as interrupt 0 WUPDC16_1 External input pin configured as DMA request 0x1 WUPDC16_2 External input pin configured as trigger event 0x2 WUPDC17 Wakeup pin configuration for LLWU_Pn 2 2 read-write WUPDC17_0 External input pin configured as interrupt 0 WUPDC17_1 External input pin configured as DMA request 0x1 WUPDC17_2 External input pin configured as trigger event 0x2 WUPDC18 Wakeup pin configuration for LLWU_Pn 4 2 read-write WUPDC18_0 External input pin configured as interrupt 0 WUPDC18_1 External input pin configured as DMA request 0x1 WUPDC18_2 External input pin configured as trigger event 0x2 WUPDC19 Wakeup pin configuration for LLWU_Pn 6 2 read-write WUPDC19_0 External input pin configured as interrupt 0 WUPDC19_1 External input pin configured as DMA request 0x1 WUPDC19_2 External input pin configured as trigger event 0x2 WUPDC20 Wakeup pin configuration for LLWU_Pn 8 2 read-write WUPDC20_0 External input pin configured as interrupt 0 WUPDC20_1 External input pin configured as DMA request 0x1 WUPDC20_2 External input pin configured as trigger event 0x2 WUPDC21 Wakeup pin configuration for LLWU_Pn 10 2 read-write WUPDC21_0 External input pin configured as interrupt 0 WUPDC21_1 External input pin configured as DMA request 0x1 WUPDC21_2 External input pin configured as trigger event 0x2 WUPDC22 Wakeup pin configuration for LLWU_Pn 12 2 read-write WUPDC22_0 External input pin configured as interrupt 0 WUPDC22_1 External input pin configured as DMA request 0x1 WUPDC22_2 External input pin configured as trigger event 0x2 WUPDC23 Wakeup pin configuration for LLWU_Pn 14 2 read-write WUPDC23_0 External input pin configured as interrupt 0 WUPDC23_1 External input pin configured as DMA request 0x1 WUPDC23_2 External input pin configured as trigger event 0x2 WUPDC24 Wakeup pin configuration for LLWU_Pn 16 2 read-write WUPDC24_0 External input pin configured as interrupt 0 WUPDC24_1 External input pin configured as DMA request 0x1 WUPDC24_2 External input pin configured as trigger event 0x2 WUPDC25 Wakeup pin configuration for LLWU_Pn 18 2 read-write WUPDC25_0 External input pin configured as interrupt 0 WUPDC25_1 External input pin configured as DMA request 0x1 WUPDC25_2 External input pin configured as trigger event 0x2 WUPDC26 Wakeup pin configuration for LLWU_Pn 20 2 read-write WUPDC26_0 External input pin configured as interrupt 0 WUPDC26_1 External input pin configured as DMA request 0x1 WUPDC26_2 External input pin configured as trigger event 0x2 WUPDC29 Wakeup pin configuration for LLWU_Pn 26 2 read-write WUPDC29_0 External input pin configured as interrupt 0 WUPDC29_1 External input pin configured as DMA request 0x1 WUPDC29_2 External input pin configured as trigger event 0x2 WUPDC30 Wakeup pin configuration for LLWU_Pn 28 2 read-write WUPDC30_0 External input pin configured as interrupt 0 WUPDC30_1 External input pin configured as DMA request 0x1 WUPDC30_2 External input pin configured as trigger event 0x2 WUPDC31 Wakeup pin configuration for LLWU_Pn 30 2 read-write WUPDC31_0 External input pin configured as interrupt 0 WUPDC31_1 External input pin configured as DMA request 0x1 WUPDC31_2 External input pin configured as trigger event 0x2 PE1 Pin Enable 1 register 0x8 32 read-write n 0x0 0x0 WUPE0 Wakeup pin enable for LLWU_Pn 0 2 read-write WUPE0_0 External input pin disabled as wakeup input 0 WUPE0_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE0_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE0_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE1 Wakeup pin enable for LLWU_Pn 2 2 read-write WUPE1_0 External input pin disabled as wakeup input 0 WUPE1_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE1_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE1_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE10 Wakeup pin enable for LLWU_Pn 20 2 read-write WUPE10_0 External input pin disabled as wakeup input 0 WUPE10_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE10_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE10_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE11 Wakeup pin enable for LLWU_Pn 22 2 read-write WUPE11_0 External input pin disabled as wakeup input 0 WUPE11_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE11_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE11_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE12 Wakeup pin enable for LLWU_Pn 24 2 read-write WUPE12_0 External input pin disabled as wakeup input 0 WUPE12_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE12_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE12_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE13 Wakeup pin enable for LLWU_Pn 26 2 read-write WUPE13_0 External input pin disabled as wakeup input 0 WUPE13_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE13_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE13_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE14 Wakeup pin enable for LLWU_Pn 28 2 read-write WUPE14_0 External input pin disabled as wakeup input 0 WUPE14_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE14_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE14_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE15 Wakeup pin enable for LLWU_Pn 30 2 read-write WUPE15_0 External input pin disabled as wakeup input 0 WUPE15_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE15_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE15_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE2 Wakeup pin enable for LLWU_Pn 4 2 read-write WUPE2_0 External input pin disabled as wakeup input 0 WUPE2_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE2_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE2_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE3 Wakeup pin enable for LLWU_Pn 6 2 read-write WUPE3_0 External input pin disabled as wakeup input 0 WUPE3_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE3_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE3_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE4 Wakeup pin enable for LLWU_Pn 8 2 read-write WUPE4_0 External input pin disabled as wakeup input 0 WUPE4_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE4_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE4_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE5 Wakeup pin enable for LLWU_Pn 10 2 read-write WUPE5_0 External input pin disabled as wakeup input 0 WUPE5_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE5_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE5_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE6 Wakeup pin enable for LLWU_Pn 12 2 read-write WUPE6_0 External input pin disabled as wakeup input 0 WUPE6_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE6_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE6_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE7 Wakeup pin enable for LLWU_Pn 14 2 read-write WUPE7_0 External input pin disabled as wakeup input 0 WUPE7_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE7_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE7_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE8 Wakeup pin enable for LLWU_Pn 16 2 read-write WUPE8_0 External input pin disabled as wakeup input 0 WUPE8_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE8_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE8_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE9 Wakeup pin enable for LLWU_Pn 18 2 read-write WUPE9_0 External input pin disabled as wakeup input 0 WUPE9_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE9_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE9_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 PE2 Pin Enable 2 register 0xC 32 read-write n 0x0 0x0 Reserved27 Wakeup pin enable for LLWU_Pn 22 2 read-only Reserved27_0 External input pin disabled as wakeup input 0 Reserved27_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 Reserved27_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 Reserved27_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 Reserved28 Wakeup pin enable for LLWU_Pn 24 2 read-only Reserved28_0 External input pin disabled as wakeup input 0 Reserved28_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 Reserved28_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 Reserved28_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE16 Wakeup pin enable for LLWU_Pn 0 2 read-write WUPE16_0 External input pin disabled as wakeup input 0 WUPE16_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE16_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE16_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE17 Wakeup pin enable for LLWU_Pn 2 2 read-write WUPE17_0 External input pin disabled as wakeup input 0 WUPE17_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE17_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE17_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE18 Wakeup pin enable for LLWU_Pn 4 2 read-write WUPE18_0 External input pin disabled as wakeup input 0 WUPE18_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE18_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE18_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE19 Wakeup pin enable for LLWU_Pn 6 2 read-write WUPE19_0 External input pin disabled as wakeup input 0 WUPE19_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE19_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE19_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE20 Wakeup pin enable for LLWU_Pn 8 2 read-write WUPE20_0 External input pin disabled as wakeup input 0 WUPE20_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE20_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE20_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE21 Wakeup pin enable for LLWU_Pn 10 2 read-write WUPE21_0 External input pin disabled as wakeup input 0 WUPE21_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE21_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE21_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE22 Wakeup pin enable for LLWU_Pn 12 2 read-write WUPE22_0 External input pin disabled as wakeup input 0 WUPE22_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE22_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE22_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE23 Wakeup pin enable for LLWU_Pn 14 2 read-write WUPE23_0 External input pin disabled as wakeup input 0 WUPE23_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE23_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE23_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE24 Wakeup pin enable for LLWU_Pn 16 2 read-write WUPE24_0 External input pin disabled as wakeup input 0 WUPE24_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE24_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE24_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE25 Wakeup pin enable for LLWU_Pn 18 2 read-write WUPE25_0 External input pin disabled as wakeup input 0 WUPE25_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE25_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE25_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE26 Wakeup pin enable for LLWU_Pn 20 2 read-write WUPE26_0 External input pin disabled as wakeup input 0 WUPE26_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE26_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE26_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE29 Wakeup pin enable for LLWU_Pn 26 2 read-write WUPE29_0 External input pin disabled as wakeup input 0 WUPE29_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE29_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE29_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE30 Wakeup pin enable for LLWU_Pn 28 2 read-write WUPE30_0 External input pin disabled as wakeup input 0 WUPE30_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE30_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE30_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE31 Wakeup pin enable for LLWU_Pn 30 2 read-write WUPE31_0 External input pin disabled as wakeup input 0 WUPE31_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE31_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE31_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 PF Pin Flag register 0x20 32 read-write n 0x0 0x0 Reserved27 Wakeup flag for LLWU_Pn 27 1 read-only Reserved27_0 LLWU_Pn input was not a wakeup source 0 Reserved27_1 LLWU_Pn input was a wakeup source 0x1 Reserved28 Wakeup flag for LLWU_Pn 28 1 read-only Reserved28_0 LLWU_Pn input was not a wakeup source 0 Reserved28_1 LLWU_Pn input was a wakeup source 0x1 WUF0 Wakeup flag for LLWU_Pn 0 1 read-write oneToClear WUF0_0 LLWU_Pn input was not a wakeup source 0 WUF0_1 LLWU_Pn input was a wakeup source 0x1 WUF1 Wakeup flag for LLWU_Pn 1 1 read-write oneToClear WUF1_0 LLWU_Pn input was not a wakeup source 0 WUF1_1 LLWU_Pn input was a wakeup source 0x1 WUF10 Wakeup flag for LLWU_Pn 10 1 read-write oneToClear WUF10_0 LLWU_Pn input was not a wakeup source 0 WUF10_1 LLWU_Pn input was a wakeup source 0x1 WUF11 Wakeup flag for LLWU_Pn 11 1 read-write oneToClear WUF11_0 LLWU_Pn input was not a wakeup source 0 WUF11_1 LLWU_Pn input was a wakeup source 0x1 WUF12 Wakeup flag for LLWU_Pn 12 1 read-write oneToClear WUF12_0 LLWU_Pn input was not a wakeup source 0 WUF12_1 LLWU_Pn input was a wakeup source 0x1 WUF13 Wakeup flag for LLWU_Pn 13 1 read-write oneToClear WUF13_0 LLWU_Pn input was not a wakeup source 0 WUF13_1 LLWU_Pn input was a wakeup source 0x1 WUF14 Wakeup flag for LLWU_Pn 14 1 read-write oneToClear WUF14_0 LLWU_Pn input was not a wakeup source 0 WUF14_1 LLWU_Pn input was a wakeup source 0x1 WUF15 Wakeup flag for LLWU_Pn 15 1 read-write oneToClear WUF15_0 LLWU_Pn input was not a wakeup source 0 WUF15_1 LLWU_Pn input was a wakeup source 0x1 WUF16 Wakeup flag for LLWU_Pn 16 1 read-write oneToClear WUF16_0 LLWU_Pn input was not a wakeup source 0 WUF16_1 LLWU_Pn input was a wakeup source 0x1 WUF17 Wakeup flag for LLWU_Pn 17 1 read-write oneToClear WUF17_0 LLWU_Pn input was not a wakeup source 0 WUF17_1 LLWU_Pn input was a wakeup source 0x1 WUF18 Wakeup flag for LLWU_Pn 18 1 read-write oneToClear WUF18_0 LLWU_Pn input was not a wakeup source 0 WUF18_1 LLWU_Pn input was a wakeup source 0x1 WUF19 Wakeup flag for LLWU_Pn 19 1 read-write oneToClear WUF19_0 LLWU_Pn input was not a wakeup source 0 WUF19_1 LLWU_Pn input was a wakeup source 0x1 WUF2 Wakeup flag for LLWU_Pn 2 1 read-write oneToClear WUF2_0 LLWU_Pn input was not a wakeup source 0 WUF2_1 LLWU_Pn input was a wakeup source 0x1 WUF20 Wakeup flag for LLWU_Pn 20 1 read-write oneToClear WUF20_0 LLWU_Pn input was not a wakeup source 0 WUF20_1 LLWU_Pn input was a wakeup source 0x1 WUF21 Wakeup flag for LLWU_Pn 21 1 read-write oneToClear WUF21_0 LLWU_Pn input was not a wakeup source 0 WUF21_1 LLWU_Pn input was a wakeup source 0x1 WUF22 Wakeup flag for LLWU_Pn 22 1 read-write oneToClear WUF22_0 LLWU_Pn input was not a wakeup source 0 WUF22_1 LLWU_Pn input was a wakeup source 0x1 WUF23 Wakeup flag for LLWU_Pn 23 1 read-write oneToClear WUF23_0 LLWU_Pn input was not a wakeup source 0 WUF23_1 LLWU_Pn input was a wakeup source 0x1 WUF24 Wakeup flag for LLWU_Pn 24 1 read-write oneToClear WUF24_0 LLWU_Pn input was not a wakeup source 0 WUF24_1 LLWU_Pn input was a wakeup source 0x1 WUF25 Wakeup flag for LLWU_Pn 25 1 read-write oneToClear WUF25_0 LLWU_Pn input was not a wakeup source 0 WUF25_1 LLWU_Pn input was a wakeup source 0x1 WUF26 Wakeup flag for LLWU_Pn 26 1 read-write oneToClear WUF26_0 LLWU_Pn input was not a wakeup source 0 WUF26_1 LLWU_Pn input was a wakeup source 0x1 WUF29 Wakeup flag for LLWU_Pn 29 1 read-write oneToClear WUF29_0 LLWU_Pn input was not a wakeup source 0 WUF29_1 LLWU_Pn input was a wakeup source 0x1 WUF3 Wakeup flag for LLWU_Pn 3 1 read-write oneToClear WUF3_0 LLWU_Pn input was not a wakeup source 0 WUF3_1 LLWU_Pn input was a wakeup source 0x1 WUF30 Wakeup flag for LLWU_Pn 30 1 read-write oneToClear WUF30_0 LLWU_Pn input was not a wakeup source 0 WUF30_1 LLWU_Pn input was a wakeup source 0x1 WUF31 Wakeup flag for LLWU_Pn 31 1 read-write oneToClear WUF31_0 LLWU_Pn input was not a wakeup source 0 WUF31_1 LLWU_Pn input was a wakeup source 0x1 WUF4 Wakeup flag for LLWU_Pn 4 1 read-write oneToClear WUF4_0 LLWU_Pn input was not a wakeup source 0 WUF4_1 LLWU_Pn input was a wakeup source 0x1 WUF5 Wakeup flag for LLWU_Pn 5 1 read-write oneToClear WUF5_0 LLWU_Pn input was not a wakeup source 0 WUF5_1 LLWU_Pn input was a wakeup source 0x1 WUF6 Wakeup flag for LLWU_Pn 6 1 read-write oneToClear WUF6_0 LLWU_Pn input was not a wakeup source 0 WUF6_1 LLWU_Pn input was a wakeup source 0x1 WUF7 Wakeup flag for LLWU_Pn 7 1 read-write oneToClear WUF7_0 LLWU_Pn input was not a wakeup source 0 WUF7_1 LLWU_Pn input was a wakeup source 0x1 WUF8 Wakeup flag for LLWU_Pn 8 1 read-write oneToClear WUF8_0 LLWU_Pn input was not a wakeup source 0 WUF8_1 LLWU_Pn input was a wakeup source 0x1 WUF9 Wakeup flag for LLWU_Pn 9 1 read-write oneToClear WUF9_0 LLWU_Pn input was not a wakeup source 0 WUF9_1 LLWU_Pn input was a wakeup source 0x1 PMC Pin Mode Configuration register 0x50 32 read-write n 0x0 0x0 Reserved27 Wakeup pin mode for LLWU_Pn 27 1 read-only Reserved27_0 External input pin detection active only during LLS/VLLS mode 0 Reserved27_1 External input pin detection active during all power modes 0x1 Reserved28 Wakeup pin mode for LLWU_Pn 28 1 read-only Reserved28_0 External input pin detection active only during LLS/VLLS mode 0 Reserved28_1 External input pin detection active during all power modes 0x1 WUPMC0 Wakeup pin mode for LLWU_Pn 0 1 read-write WUPMC0_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC0_1 External input pin detection active during all power modes 0x1 WUPMC1 Wakeup pin mode for LLWU_Pn 1 1 read-write WUPMC1_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC1_1 External input pin detection active during all power modes 0x1 WUPMC10 Wakeup pin mode for LLWU_Pn 10 1 read-write WUPMC10_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC10_1 External input pin detection active during all power modes 0x1 WUPMC11 Wakeup pin mode for LLWU_Pn 11 1 read-write WUPMC11_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC11_1 External input pin detection active during all power modes 0x1 WUPMC12 Wakeup pin mode for LLWU_Pn 12 1 read-write WUPMC12_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC12_1 External input pin detection active during all power modes 0x1 WUPMC13 Wakeup pin mode for LLWU_Pn 13 1 read-write WUPMC13_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC13_1 External input pin detection active during all power modes 0x1 WUPMC14 Wakeup pin mode for LLWU_Pn 14 1 read-write WUPMC14_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC14_1 External input pin detection active during all power modes 0x1 WUPMC15 Wakeup pin mode for LLWU_Pn 15 1 read-write WUPMC15_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC15_1 External input pin detection active during all power modes 0x1 WUPMC16 Wakeup pin mode for LLWU_Pn 16 1 read-write WUPMC16_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC16_1 External input pin detection active during all power modes 0x1 WUPMC17 Wakeup pin mode for LLWU_Pn 17 1 read-write WUPMC17_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC17_1 External input pin detection active during all power modes 0x1 WUPMC18 Wakeup pin mode for LLWU_Pn 18 1 read-write WUPMC18_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC18_1 External input pin detection active during all power modes 0x1 WUPMC19 Wakeup pin mode for LLWU_Pn 19 1 read-write WUPMC19_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC19_1 External input pin detection active during all power modes 0x1 WUPMC2 Wakeup pin mode for LLWU_Pn 2 1 read-write WUPMC2_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC2_1 External input pin detection active during all power modes 0x1 WUPMC20 Wakeup pin mode for LLWU_Pn 20 1 read-write WUPMC20_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC20_1 External input pin detection active during all power modes 0x1 WUPMC21 Wakeup pin mode for LLWU_Pn 21 1 read-write WUPMC21_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC21_1 External input pin detection active during all power modes 0x1 WUPMC22 Wakeup pin mode for LLWU_Pn 22 1 read-write WUPMC22_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC22_1 External input pin detection active during all power modes 0x1 WUPMC23 Wakeup pin mode for LLWU_Pn 23 1 read-write WUPMC23_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC23_1 External input pin detection active during all power modes 0x1 WUPMC24 Wakeup pin mode for LLWU_Pn 24 1 read-write WUPMC24_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC24_1 External input pin detection active during all power modes 0x1 WUPMC25 Wakeup pin mode for LLWU_Pn 25 1 read-write WUPMC25_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC25_1 External input pin detection active during all power modes 0x1 WUPMC26 Wakeup pin mode for LLWU_Pn 26 1 read-write WUPMC26_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC26_1 External input pin detection active during all power modes 0x1 WUPMC29 Wakeup pin mode for LLWU_Pn 29 1 read-write WUPMC29_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC29_1 External input pin detection active during all power modes 0x1 WUPMC3 Wakeup pin mode for LLWU_Pn 3 1 read-write WUPMC3_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC3_1 External input pin detection active during all power modes 0x1 WUPMC30 Wakeup pin mode for LLWU_Pn 30 1 read-write WUPMC30_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC30_1 External input pin detection active during all power modes 0x1 WUPMC31 Wakeup pin mode for LLWU_Pn 31 1 read-write WUPMC31_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC31_1 External input pin detection active during all power modes 0x1 WUPMC4 Wakeup pin mode for LLWU_Pn 4 1 read-write WUPMC4_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC4_1 External input pin detection active during all power modes 0x1 WUPMC5 Wakeup pin mode for LLWU_Pn 5 1 read-write WUPMC5_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC5_1 External input pin detection active during all power modes 0x1 WUPMC6 Wakeup pin mode for LLWU_Pn 6 1 read-write WUPMC6_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC6_1 External input pin detection active during all power modes 0x1 WUPMC7 Wakeup pin mode for LLWU_Pn 7 1 read-write WUPMC7_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC7_1 External input pin detection active during all power modes 0x1 WUPMC8 Wakeup pin mode for LLWU_Pn 8 1 read-write WUPMC8_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC8_1 External input pin detection active during all power modes 0x1 WUPMC9 Wakeup pin mode for LLWU_Pn 9 1 read-write WUPMC9_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC9_1 External input pin detection active during all power modes 0x1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only FEATURE_0 Standard features implemented 0 FEATURE_1 Support for DMA/Trigger generation from wakeup pins and filters enabled. Support for external pin/filter detection during all power modes enabled. 0x1 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LLWU1 LLWU LLWU1 0x0 0x0 0x5C registers n DE Module DMA/Trigger Enable register 0x1C 32 read-write n 0x0 0x0 Reserved3 DMA/Trigger wakeup enable for module n 3 1 read-only Reserved3_0 Internal module request not enabled as a DMA/Trigger wakeup source 0 Reserved3_1 Internal module request enabled as a DMA/Trigger wakeup source 0x1 Reserved7 DMA/Trigger wakeup enable for module n 7 1 read-only Reserved7_0 Internal module request not enabled as a DMA/Trigger wakeup source 0 Reserved7_1 Internal module request enabled as a DMA/Trigger wakeup source 0x1 WUDE0 DMA/Trigger wakeup enable for module n 0 1 read-write WUDE0_0 Internal module request not enabled as a DMA/Trigger wakeup source 0 WUDE0_1 Internal module request enabled as a DMA/Trigger wakeup source 0x1 WUDE1 DMA/Trigger wakeup enable for module n 1 1 read-write WUDE1_0 Internal module request not enabled as a DMA/Trigger wakeup source 0 WUDE1_1 Internal module request enabled as a DMA/Trigger wakeup source 0x1 WUDE2 DMA/Trigger wakeup enable for module n 2 1 read-write WUDE2_0 Internal module request not enabled as a DMA/Trigger wakeup source 0 WUDE2_1 Internal module request enabled as a DMA/Trigger wakeup source 0x1 WUDE4 DMA/Trigger wakeup enable for module n 4 1 read-write WUDE4_0 Internal module request not enabled as a DMA/Trigger wakeup source 0 WUDE4_1 Internal module request enabled as a DMA/Trigger wakeup source 0x1 WUDE5 DMA/Trigger wakeup enable for module n 5 1 read-write WUDE5_0 Internal module request not enabled as a DMA/Trigger wakeup source 0 WUDE5_1 Internal module request enabled as a DMA/Trigger wakeup source 0x1 WUDE6 DMA/Trigger wakeup enable for module n 6 1 read-write WUDE6_0 Internal module request not enabled as a DMA/Trigger wakeup source 0 WUDE6_1 Internal module request enabled as a DMA/Trigger wakeup source 0x1 FDC Pin Filter DMA/Trigger Configuration register 0x48 32 read-write n 0x0 0x0 FILTC1 Filter configuration for FILT1 0 2 read-write FILTC1_0 Filter output configured as interrupt 0 FILTC1_1 Filter output configured as DMA request 0x1 FILTC1_2 Filter output configured as trigger event 0x2 FILTC2 Filter configuration for FILT2 2 2 read-write FILTC2_0 Filter output configured as interrupt 0 FILTC2_1 Filter output configured as DMA request 0x1 FILTC2_2 Filter output configured as trigger event 0x2 FILT Pin Filter register 0x30 32 read-write n 0x0 0x0 FILTE1 Filter 1 Enable 5 2 read-write FILTE1_0 Filter disabled 0 FILTE1_1 Filter posedge detect enabled when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 FILTE1_2 Filter negedge detect enabled when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 FILTE1_3 Filter any edge detect enabled when configured as interrupt/DMA request 0x3 FILTE2 Filter 2 Enable 13 2 read-write FILTE2_0 Filter disabled 0 FILTE2_1 Filter posedge detect enabled when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 FILTE2_2 Filter negedge detect enabled when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 FILTE2_3 Filter any edge detect enabled when configured as interrupt/DMA request 0x3 FILTF1 Filter 1 Flag 7 1 read-write oneToClear FILTF1_0 Pin Filter 1 was not a wakeup source 0 FILTF1_1 Pin Filter 1 was a wakeup source 0x1 FILTF2 Filter 2 Flag 15 1 read-write oneToClear FILTF2_0 Pin Filter 2 was not a wakeup source 0 FILTF2_1 Pin Filter 2 was a wakeup source 0x1 FILTSEL1 Filter 1 Pin Select 0 5 read-write FILTSEL1_0 Select LLWU_P0 for filter 0 FILTSEL1_31 Select LLWU_P31 for filter 0x1F FILTSEL2 Filter 2 Pin Select 8 5 read-write FILTSEL2_0 Select LLWU_P0 for filter 0 FILTSEL2_31 Select LLWU_P31 for filter 0x1F FMC Pin Filter Mode Configuration register 0x58 32 read-write n 0x0 0x0 FILTM1 Filter Mode for FILT1 0 1 read-write FILTM1_0 External input pin filter detection active only during LLS/VLLS mode 0 FILTM1_1 External input pin filter detection active during all power modes 0x1 FILTM2 Filter Mode for FILT2 1 1 read-write FILTM2_0 External input pin filter detection active only during LLS/VLLS mode 0 FILTM2_1 External input pin filter detection active during all power modes 0x1 ME Module Interrupt Enable register 0x18 32 read-write n 0x0 0x0 Reserved4 Wakeup module enable for module n 4 1 read-only Reserved4_0 Internal module flag not used as wakeup source 0 Reserved4_1 Internal module flag used as wakeup source 0x1 WUME0 Wakeup module enable for module n 0 1 read-write WUME0_0 Internal module flag not used as wakeup source 0 WUME0_1 Internal module flag used as wakeup source 0x1 WUME1 Wakeup module enable for module n 1 1 read-write WUME1_0 Internal module flag not used as wakeup source 0 WUME1_1 Internal module flag used as wakeup source 0x1 WUME2 Wakeup module enable for module n 2 1 read-write WUME2_0 Internal module flag not used as wakeup source 0 WUME2_1 Internal module flag used as wakeup source 0x1 WUME3 Wakeup module enable for module n 3 1 read-write WUME3_0 Internal module flag not used as wakeup source 0 WUME3_1 Internal module flag used as wakeup source 0x1 WUME5 Wakeup module enable for module n 5 1 read-write WUME5_0 Internal module flag not used as wakeup source 0 WUME5_1 Internal module flag used as wakeup source 0x1 WUME6 Wakeup module enable for module n 6 1 read-write WUME6_0 Internal module flag not used as wakeup source 0 WUME6_1 Internal module flag used as wakeup source 0x1 WUME7 Wakeup module enable for module n 7 1 read-write WUME7_0 Internal module flag not used as wakeup source 0 WUME7_1 Internal module flag used as wakeup source 0x1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 DMAS DMA Number 8 8 read-only FILTERS Filter Number 0 8 read-only MODULES Module Number 16 8 read-only PINS Pin Number 24 8 read-only PDC1 Pin DMA/Trigger Configuration 1 register 0x38 32 read-write n 0x0 0x0 WUPDC0 Wakeup pin configuration for LLWU_Pn 0 2 read-write WUPDC0_0 External input pin configured as interrupt 0 WUPDC0_1 External input pin configured as DMA request 0x1 WUPDC0_2 External input pin configured as trigger event 0x2 WUPDC1 Wakeup pin configuration for LLWU_Pn 2 2 read-write WUPDC1_0 External input pin configured as interrupt 0 WUPDC1_1 External input pin configured as DMA request 0x1 WUPDC1_2 External input pin configured as trigger event 0x2 WUPDC10 Wakeup pin configuration for LLWU_Pn 20 2 read-write WUPDC10_0 External input pin configured as interrupt 0 WUPDC10_1 External input pin configured as DMA request 0x1 WUPDC10_2 External input pin configured as trigger event 0x2 WUPDC11 Wakeup pin configuration for LLWU_Pn 22 2 read-write WUPDC11_0 External input pin configured as interrupt 0 WUPDC11_1 External input pin configured as DMA request 0x1 WUPDC11_2 External input pin configured as trigger event 0x2 WUPDC12 Wakeup pin configuration for LLWU_Pn 24 2 read-write WUPDC12_0 External input pin configured as interrupt 0 WUPDC12_1 External input pin configured as DMA request 0x1 WUPDC12_2 External input pin configured as trigger event 0x2 WUPDC13 Wakeup pin configuration for LLWU_Pn 26 2 read-write WUPDC13_0 External input pin configured as interrupt 0 WUPDC13_1 External input pin configured as DMA request 0x1 WUPDC13_2 External input pin configured as trigger event 0x2 WUPDC14 Wakeup pin configuration for LLWU_Pn 28 2 read-write WUPDC14_0 External input pin configured as interrupt 0 WUPDC14_1 External input pin configured as DMA request 0x1 WUPDC14_2 External input pin configured as trigger event 0x2 WUPDC15 Wakeup pin configuration for LLWU_Pn 30 2 read-write WUPDC15_0 External input pin configured as interrupt 0 WUPDC15_1 External input pin configured as DMA request 0x1 WUPDC15_2 External input pin configured as trigger event 0x2 WUPDC2 Wakeup pin configuration for LLWU_Pn 4 2 read-write WUPDC2_0 External input pin configured as interrupt 0 WUPDC2_1 External input pin configured as DMA request 0x1 WUPDC2_2 External input pin configured as trigger event 0x2 WUPDC3 Wakeup pin configuration for LLWU_Pn 6 2 read-write WUPDC3_0 External input pin configured as interrupt 0 WUPDC3_1 External input pin configured as DMA request 0x1 WUPDC3_2 External input pin configured as trigger event 0x2 WUPDC4 Wakeup pin configuration for LLWU_Pn 8 2 read-write WUPDC4_0 External input pin configured as interrupt 0 WUPDC4_1 External input pin configured as DMA request 0x1 WUPDC4_2 External input pin configured as trigger event 0x2 WUPDC5 Wakeup pin configuration for LLWU_Pn 10 2 read-write WUPDC5_0 External input pin configured as interrupt 0 WUPDC5_1 External input pin configured as DMA request 0x1 WUPDC5_2 External input pin configured as trigger event 0x2 WUPDC6 Wakeup pin configuration for LLWU_Pn 12 2 read-write WUPDC6_0 External input pin configured as interrupt 0 WUPDC6_1 External input pin configured as DMA request 0x1 WUPDC6_2 External input pin configured as trigger event 0x2 WUPDC7 Wakeup pin configuration for LLWU_Pn 14 2 read-write WUPDC7_0 External input pin configured as interrupt 0 WUPDC7_1 External input pin configured as DMA request 0x1 WUPDC7_2 External input pin configured as trigger event 0x2 WUPDC8 Wakeup pin configuration for LLWU_Pn 16 2 read-write WUPDC8_0 External input pin configured as interrupt 0 WUPDC8_1 External input pin configured as DMA request 0x1 WUPDC8_2 External input pin configured as trigger event 0x2 WUPDC9 Wakeup pin configuration for LLWU_Pn 18 2 read-write WUPDC9_0 External input pin configured as interrupt 0 WUPDC9_1 External input pin configured as DMA request 0x1 WUPDC9_2 External input pin configured as trigger event 0x2 PDC2 Pin DMA/Trigger Configuration 2 register 0x3C 32 read-write n 0x0 0x0 Reserved27 Wakeup pin configuration for LLWU_Pn 22 2 read-only Reserved27_0 External input pin configured as interrupt 0 Reserved27_1 External input pin configured as DMA request 0x1 Reserved27_2 External input pin configured as trigger event 0x2 Reserved28 Wakeup pin configuration for LLWU_Pn 24 2 read-only Reserved28_0 External input pin configured as interrupt 0 Reserved28_1 External input pin configured as DMA request 0x1 Reserved28_2 External input pin configured as trigger event 0x2 WUPDC16 Wakeup pin configuration for LLWU_Pn 0 2 read-write WUPDC16_0 External input pin configured as interrupt 0 WUPDC16_1 External input pin configured as DMA request 0x1 WUPDC16_2 External input pin configured as trigger event 0x2 WUPDC17 Wakeup pin configuration for LLWU_Pn 2 2 read-write WUPDC17_0 External input pin configured as interrupt 0 WUPDC17_1 External input pin configured as DMA request 0x1 WUPDC17_2 External input pin configured as trigger event 0x2 WUPDC18 Wakeup pin configuration for LLWU_Pn 4 2 read-write WUPDC18_0 External input pin configured as interrupt 0 WUPDC18_1 External input pin configured as DMA request 0x1 WUPDC18_2 External input pin configured as trigger event 0x2 WUPDC19 Wakeup pin configuration for LLWU_Pn 6 2 read-write WUPDC19_0 External input pin configured as interrupt 0 WUPDC19_1 External input pin configured as DMA request 0x1 WUPDC19_2 External input pin configured as trigger event 0x2 WUPDC20 Wakeup pin configuration for LLWU_Pn 8 2 read-write WUPDC20_0 External input pin configured as interrupt 0 WUPDC20_1 External input pin configured as DMA request 0x1 WUPDC20_2 External input pin configured as trigger event 0x2 WUPDC21 Wakeup pin configuration for LLWU_Pn 10 2 read-write WUPDC21_0 External input pin configured as interrupt 0 WUPDC21_1 External input pin configured as DMA request 0x1 WUPDC21_2 External input pin configured as trigger event 0x2 WUPDC22 Wakeup pin configuration for LLWU_Pn 12 2 read-write WUPDC22_0 External input pin configured as interrupt 0 WUPDC22_1 External input pin configured as DMA request 0x1 WUPDC22_2 External input pin configured as trigger event 0x2 WUPDC23 Wakeup pin configuration for LLWU_Pn 14 2 read-write WUPDC23_0 External input pin configured as interrupt 0 WUPDC23_1 External input pin configured as DMA request 0x1 WUPDC23_2 External input pin configured as trigger event 0x2 WUPDC24 Wakeup pin configuration for LLWU_Pn 16 2 read-write WUPDC24_0 External input pin configured as interrupt 0 WUPDC24_1 External input pin configured as DMA request 0x1 WUPDC24_2 External input pin configured as trigger event 0x2 WUPDC25 Wakeup pin configuration for LLWU_Pn 18 2 read-write WUPDC25_0 External input pin configured as interrupt 0 WUPDC25_1 External input pin configured as DMA request 0x1 WUPDC25_2 External input pin configured as trigger event 0x2 WUPDC26 Wakeup pin configuration for LLWU_Pn 20 2 read-write WUPDC26_0 External input pin configured as interrupt 0 WUPDC26_1 External input pin configured as DMA request 0x1 WUPDC26_2 External input pin configured as trigger event 0x2 WUPDC29 Wakeup pin configuration for LLWU_Pn 26 2 read-write WUPDC29_0 External input pin configured as interrupt 0 WUPDC29_1 External input pin configured as DMA request 0x1 WUPDC29_2 External input pin configured as trigger event 0x2 WUPDC30 Wakeup pin configuration for LLWU_Pn 28 2 read-write WUPDC30_0 External input pin configured as interrupt 0 WUPDC30_1 External input pin configured as DMA request 0x1 WUPDC30_2 External input pin configured as trigger event 0x2 WUPDC31 Wakeup pin configuration for LLWU_Pn 30 2 read-write WUPDC31_0 External input pin configured as interrupt 0 WUPDC31_1 External input pin configured as DMA request 0x1 WUPDC31_2 External input pin configured as trigger event 0x2 PE1 Pin Enable 1 register 0x8 32 read-write n 0x0 0x0 WUPE0 Wakeup pin enable for LLWU_Pn 0 2 read-write WUPE0_0 External input pin disabled as wakeup input 0 WUPE0_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE0_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE0_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE1 Wakeup pin enable for LLWU_Pn 2 2 read-write WUPE1_0 External input pin disabled as wakeup input 0 WUPE1_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE1_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE1_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE10 Wakeup pin enable for LLWU_Pn 20 2 read-write WUPE10_0 External input pin disabled as wakeup input 0 WUPE10_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE10_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE10_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE11 Wakeup pin enable for LLWU_Pn 22 2 read-write WUPE11_0 External input pin disabled as wakeup input 0 WUPE11_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE11_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE11_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE12 Wakeup pin enable for LLWU_Pn 24 2 read-write WUPE12_0 External input pin disabled as wakeup input 0 WUPE12_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE12_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE12_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE13 Wakeup pin enable for LLWU_Pn 26 2 read-write WUPE13_0 External input pin disabled as wakeup input 0 WUPE13_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE13_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE13_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE14 Wakeup pin enable for LLWU_Pn 28 2 read-write WUPE14_0 External input pin disabled as wakeup input 0 WUPE14_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE14_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE14_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE15 Wakeup pin enable for LLWU_Pn 30 2 read-write WUPE15_0 External input pin disabled as wakeup input 0 WUPE15_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE15_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE15_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE2 Wakeup pin enable for LLWU_Pn 4 2 read-write WUPE2_0 External input pin disabled as wakeup input 0 WUPE2_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE2_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE2_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE3 Wakeup pin enable for LLWU_Pn 6 2 read-write WUPE3_0 External input pin disabled as wakeup input 0 WUPE3_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE3_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE3_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE4 Wakeup pin enable for LLWU_Pn 8 2 read-write WUPE4_0 External input pin disabled as wakeup input 0 WUPE4_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE4_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE4_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE5 Wakeup pin enable for LLWU_Pn 10 2 read-write WUPE5_0 External input pin disabled as wakeup input 0 WUPE5_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE5_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE5_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE6 Wakeup pin enable for LLWU_Pn 12 2 read-write WUPE6_0 External input pin disabled as wakeup input 0 WUPE6_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE6_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE6_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE7 Wakeup pin enable for LLWU_Pn 14 2 read-write WUPE7_0 External input pin disabled as wakeup input 0 WUPE7_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE7_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE7_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE8 Wakeup pin enable for LLWU_Pn 16 2 read-write WUPE8_0 External input pin disabled as wakeup input 0 WUPE8_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE8_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE8_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE9 Wakeup pin enable for LLWU_Pn 18 2 read-write WUPE9_0 External input pin disabled as wakeup input 0 WUPE9_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE9_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE9_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 PE2 Pin Enable 2 register 0xC 32 read-write n 0x0 0x0 Reserved27 Wakeup pin enable for LLWU_Pn 22 2 read-only Reserved27_0 External input pin disabled as wakeup input 0 Reserved27_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 Reserved27_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 Reserved27_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 Reserved28 Wakeup pin enable for LLWU_Pn 24 2 read-only Reserved28_0 External input pin disabled as wakeup input 0 Reserved28_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 Reserved28_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 Reserved28_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE16 Wakeup pin enable for LLWU_Pn 0 2 read-write WUPE16_0 External input pin disabled as wakeup input 0 WUPE16_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE16_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE16_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE17 Wakeup pin enable for LLWU_Pn 2 2 read-write WUPE17_0 External input pin disabled as wakeup input 0 WUPE17_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE17_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE17_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE18 Wakeup pin enable for LLWU_Pn 4 2 read-write WUPE18_0 External input pin disabled as wakeup input 0 WUPE18_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE18_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE18_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE19 Wakeup pin enable for LLWU_Pn 6 2 read-write WUPE19_0 External input pin disabled as wakeup input 0 WUPE19_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE19_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE19_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE20 Wakeup pin enable for LLWU_Pn 8 2 read-write WUPE20_0 External input pin disabled as wakeup input 0 WUPE20_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE20_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE20_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE21 Wakeup pin enable for LLWU_Pn 10 2 read-write WUPE21_0 External input pin disabled as wakeup input 0 WUPE21_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE21_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE21_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE22 Wakeup pin enable for LLWU_Pn 12 2 read-write WUPE22_0 External input pin disabled as wakeup input 0 WUPE22_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE22_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE22_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE23 Wakeup pin enable for LLWU_Pn 14 2 read-write WUPE23_0 External input pin disabled as wakeup input 0 WUPE23_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE23_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE23_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE24 Wakeup pin enable for LLWU_Pn 16 2 read-write WUPE24_0 External input pin disabled as wakeup input 0 WUPE24_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE24_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE24_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE25 Wakeup pin enable for LLWU_Pn 18 2 read-write WUPE25_0 External input pin disabled as wakeup input 0 WUPE25_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE25_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE25_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE26 Wakeup pin enable for LLWU_Pn 20 2 read-write WUPE26_0 External input pin disabled as wakeup input 0 WUPE26_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE26_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE26_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE29 Wakeup pin enable for LLWU_Pn 26 2 read-write WUPE29_0 External input pin disabled as wakeup input 0 WUPE29_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE29_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE29_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE30 Wakeup pin enable for LLWU_Pn 28 2 read-write WUPE30_0 External input pin disabled as wakeup input 0 WUPE30_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE30_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE30_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 WUPE31 Wakeup pin enable for LLWU_Pn 30 2 read-write WUPE31_0 External input pin disabled as wakeup input 0 WUPE31_1 External input pin enabled with rising edge detection when configured as interrupt/DMA request or high level detection when configured as trigger request 0x1 WUPE31_2 External input pin enabled with falling edge detection when configured as interrupt/DMA request or low level detection when configured as trigger request 0x2 WUPE31_3 External input pin enabled with any change detection when configured as interrupt/DMA request 0x3 PF Pin Flag register 0x20 32 read-write n 0x0 0x0 Reserved27 Wakeup flag for LLWU_Pn 27 1 read-only Reserved27_0 LLWU_Pn input was not a wakeup source 0 Reserved27_1 LLWU_Pn input was a wakeup source 0x1 Reserved28 Wakeup flag for LLWU_Pn 28 1 read-only Reserved28_0 LLWU_Pn input was not a wakeup source 0 Reserved28_1 LLWU_Pn input was a wakeup source 0x1 WUF0 Wakeup flag for LLWU_Pn 0 1 read-write oneToClear WUF0_0 LLWU_Pn input was not a wakeup source 0 WUF0_1 LLWU_Pn input was a wakeup source 0x1 WUF1 Wakeup flag for LLWU_Pn 1 1 read-write oneToClear WUF1_0 LLWU_Pn input was not a wakeup source 0 WUF1_1 LLWU_Pn input was a wakeup source 0x1 WUF10 Wakeup flag for LLWU_Pn 10 1 read-write oneToClear WUF10_0 LLWU_Pn input was not a wakeup source 0 WUF10_1 LLWU_Pn input was a wakeup source 0x1 WUF11 Wakeup flag for LLWU_Pn 11 1 read-write oneToClear WUF11_0 LLWU_Pn input was not a wakeup source 0 WUF11_1 LLWU_Pn input was a wakeup source 0x1 WUF12 Wakeup flag for LLWU_Pn 12 1 read-write oneToClear WUF12_0 LLWU_Pn input was not a wakeup source 0 WUF12_1 LLWU_Pn input was a wakeup source 0x1 WUF13 Wakeup flag for LLWU_Pn 13 1 read-write oneToClear WUF13_0 LLWU_Pn input was not a wakeup source 0 WUF13_1 LLWU_Pn input was a wakeup source 0x1 WUF14 Wakeup flag for LLWU_Pn 14 1 read-write oneToClear WUF14_0 LLWU_Pn input was not a wakeup source 0 WUF14_1 LLWU_Pn input was a wakeup source 0x1 WUF15 Wakeup flag for LLWU_Pn 15 1 read-write oneToClear WUF15_0 LLWU_Pn input was not a wakeup source 0 WUF15_1 LLWU_Pn input was a wakeup source 0x1 WUF16 Wakeup flag for LLWU_Pn 16 1 read-write oneToClear WUF16_0 LLWU_Pn input was not a wakeup source 0 WUF16_1 LLWU_Pn input was a wakeup source 0x1 WUF17 Wakeup flag for LLWU_Pn 17 1 read-write oneToClear WUF17_0 LLWU_Pn input was not a wakeup source 0 WUF17_1 LLWU_Pn input was a wakeup source 0x1 WUF18 Wakeup flag for LLWU_Pn 18 1 read-write oneToClear WUF18_0 LLWU_Pn input was not a wakeup source 0 WUF18_1 LLWU_Pn input was a wakeup source 0x1 WUF19 Wakeup flag for LLWU_Pn 19 1 read-write oneToClear WUF19_0 LLWU_Pn input was not a wakeup source 0 WUF19_1 LLWU_Pn input was a wakeup source 0x1 WUF2 Wakeup flag for LLWU_Pn 2 1 read-write oneToClear WUF2_0 LLWU_Pn input was not a wakeup source 0 WUF2_1 LLWU_Pn input was a wakeup source 0x1 WUF20 Wakeup flag for LLWU_Pn 20 1 read-write oneToClear WUF20_0 LLWU_Pn input was not a wakeup source 0 WUF20_1 LLWU_Pn input was a wakeup source 0x1 WUF21 Wakeup flag for LLWU_Pn 21 1 read-write oneToClear WUF21_0 LLWU_Pn input was not a wakeup source 0 WUF21_1 LLWU_Pn input was a wakeup source 0x1 WUF22 Wakeup flag for LLWU_Pn 22 1 read-write oneToClear WUF22_0 LLWU_Pn input was not a wakeup source 0 WUF22_1 LLWU_Pn input was a wakeup source 0x1 WUF23 Wakeup flag for LLWU_Pn 23 1 read-write oneToClear WUF23_0 LLWU_Pn input was not a wakeup source 0 WUF23_1 LLWU_Pn input was a wakeup source 0x1 WUF24 Wakeup flag for LLWU_Pn 24 1 read-write oneToClear WUF24_0 LLWU_Pn input was not a wakeup source 0 WUF24_1 LLWU_Pn input was a wakeup source 0x1 WUF25 Wakeup flag for LLWU_Pn 25 1 read-write oneToClear WUF25_0 LLWU_Pn input was not a wakeup source 0 WUF25_1 LLWU_Pn input was a wakeup source 0x1 WUF26 Wakeup flag for LLWU_Pn 26 1 read-write oneToClear WUF26_0 LLWU_Pn input was not a wakeup source 0 WUF26_1 LLWU_Pn input was a wakeup source 0x1 WUF29 Wakeup flag for LLWU_Pn 29 1 read-write oneToClear WUF29_0 LLWU_Pn input was not a wakeup source 0 WUF29_1 LLWU_Pn input was a wakeup source 0x1 WUF3 Wakeup flag for LLWU_Pn 3 1 read-write oneToClear WUF3_0 LLWU_Pn input was not a wakeup source 0 WUF3_1 LLWU_Pn input was a wakeup source 0x1 WUF30 Wakeup flag for LLWU_Pn 30 1 read-write oneToClear WUF30_0 LLWU_Pn input was not a wakeup source 0 WUF30_1 LLWU_Pn input was a wakeup source 0x1 WUF31 Wakeup flag for LLWU_Pn 31 1 read-write oneToClear WUF31_0 LLWU_Pn input was not a wakeup source 0 WUF31_1 LLWU_Pn input was a wakeup source 0x1 WUF4 Wakeup flag for LLWU_Pn 4 1 read-write oneToClear WUF4_0 LLWU_Pn input was not a wakeup source 0 WUF4_1 LLWU_Pn input was a wakeup source 0x1 WUF5 Wakeup flag for LLWU_Pn 5 1 read-write oneToClear WUF5_0 LLWU_Pn input was not a wakeup source 0 WUF5_1 LLWU_Pn input was a wakeup source 0x1 WUF6 Wakeup flag for LLWU_Pn 6 1 read-write oneToClear WUF6_0 LLWU_Pn input was not a wakeup source 0 WUF6_1 LLWU_Pn input was a wakeup source 0x1 WUF7 Wakeup flag for LLWU_Pn 7 1 read-write oneToClear WUF7_0 LLWU_Pn input was not a wakeup source 0 WUF7_1 LLWU_Pn input was a wakeup source 0x1 WUF8 Wakeup flag for LLWU_Pn 8 1 read-write oneToClear WUF8_0 LLWU_Pn input was not a wakeup source 0 WUF8_1 LLWU_Pn input was a wakeup source 0x1 WUF9 Wakeup flag for LLWU_Pn 9 1 read-write oneToClear WUF9_0 LLWU_Pn input was not a wakeup source 0 WUF9_1 LLWU_Pn input was a wakeup source 0x1 PMC Pin Mode Configuration register 0x50 32 read-write n 0x0 0x0 Reserved27 Wakeup pin mode for LLWU_Pn 27 1 read-only Reserved27_0 External input pin detection active only during LLS/VLLS mode 0 Reserved27_1 External input pin detection active during all power modes 0x1 Reserved28 Wakeup pin mode for LLWU_Pn 28 1 read-only Reserved28_0 External input pin detection active only during LLS/VLLS mode 0 Reserved28_1 External input pin detection active during all power modes 0x1 WUPMC0 Wakeup pin mode for LLWU_Pn 0 1 read-write WUPMC0_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC0_1 External input pin detection active during all power modes 0x1 WUPMC1 Wakeup pin mode for LLWU_Pn 1 1 read-write WUPMC1_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC1_1 External input pin detection active during all power modes 0x1 WUPMC10 Wakeup pin mode for LLWU_Pn 10 1 read-write WUPMC10_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC10_1 External input pin detection active during all power modes 0x1 WUPMC11 Wakeup pin mode for LLWU_Pn 11 1 read-write WUPMC11_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC11_1 External input pin detection active during all power modes 0x1 WUPMC12 Wakeup pin mode for LLWU_Pn 12 1 read-write WUPMC12_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC12_1 External input pin detection active during all power modes 0x1 WUPMC13 Wakeup pin mode for LLWU_Pn 13 1 read-write WUPMC13_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC13_1 External input pin detection active during all power modes 0x1 WUPMC14 Wakeup pin mode for LLWU_Pn 14 1 read-write WUPMC14_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC14_1 External input pin detection active during all power modes 0x1 WUPMC15 Wakeup pin mode for LLWU_Pn 15 1 read-write WUPMC15_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC15_1 External input pin detection active during all power modes 0x1 WUPMC16 Wakeup pin mode for LLWU_Pn 16 1 read-write WUPMC16_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC16_1 External input pin detection active during all power modes 0x1 WUPMC17 Wakeup pin mode for LLWU_Pn 17 1 read-write WUPMC17_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC17_1 External input pin detection active during all power modes 0x1 WUPMC18 Wakeup pin mode for LLWU_Pn 18 1 read-write WUPMC18_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC18_1 External input pin detection active during all power modes 0x1 WUPMC19 Wakeup pin mode for LLWU_Pn 19 1 read-write WUPMC19_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC19_1 External input pin detection active during all power modes 0x1 WUPMC2 Wakeup pin mode for LLWU_Pn 2 1 read-write WUPMC2_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC2_1 External input pin detection active during all power modes 0x1 WUPMC20 Wakeup pin mode for LLWU_Pn 20 1 read-write WUPMC20_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC20_1 External input pin detection active during all power modes 0x1 WUPMC21 Wakeup pin mode for LLWU_Pn 21 1 read-write WUPMC21_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC21_1 External input pin detection active during all power modes 0x1 WUPMC22 Wakeup pin mode for LLWU_Pn 22 1 read-write WUPMC22_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC22_1 External input pin detection active during all power modes 0x1 WUPMC23 Wakeup pin mode for LLWU_Pn 23 1 read-write WUPMC23_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC23_1 External input pin detection active during all power modes 0x1 WUPMC24 Wakeup pin mode for LLWU_Pn 24 1 read-write WUPMC24_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC24_1 External input pin detection active during all power modes 0x1 WUPMC25 Wakeup pin mode for LLWU_Pn 25 1 read-write WUPMC25_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC25_1 External input pin detection active during all power modes 0x1 WUPMC26 Wakeup pin mode for LLWU_Pn 26 1 read-write WUPMC26_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC26_1 External input pin detection active during all power modes 0x1 WUPMC29 Wakeup pin mode for LLWU_Pn 29 1 read-write WUPMC29_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC29_1 External input pin detection active during all power modes 0x1 WUPMC3 Wakeup pin mode for LLWU_Pn 3 1 read-write WUPMC3_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC3_1 External input pin detection active during all power modes 0x1 WUPMC30 Wakeup pin mode for LLWU_Pn 30 1 read-write WUPMC30_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC30_1 External input pin detection active during all power modes 0x1 WUPMC31 Wakeup pin mode for LLWU_Pn 31 1 read-write WUPMC31_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC31_1 External input pin detection active during all power modes 0x1 WUPMC4 Wakeup pin mode for LLWU_Pn 4 1 read-write WUPMC4_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC4_1 External input pin detection active during all power modes 0x1 WUPMC5 Wakeup pin mode for LLWU_Pn 5 1 read-write WUPMC5_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC5_1 External input pin detection active during all power modes 0x1 WUPMC6 Wakeup pin mode for LLWU_Pn 6 1 read-write WUPMC6_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC6_1 External input pin detection active during all power modes 0x1 WUPMC7 Wakeup pin mode for LLWU_Pn 7 1 read-write WUPMC7_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC7_1 External input pin detection active during all power modes 0x1 WUPMC8 Wakeup pin mode for LLWU_Pn 8 1 read-write WUPMC8_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC8_1 External input pin detection active during all power modes 0x1 WUPMC9 Wakeup pin mode for LLWU_Pn 9 1 read-write WUPMC9_0 External input pin detection active only during LLS/VLLS mode 0 WUPMC9_1 External input pin detection active during all power modes 0x1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only FEATURE_0 Standard features implemented 0 FEATURE_1 Support for DMA/Trigger generation from wakeup pins and filters enabled. Support for external pin/filter detection during all power modes enabled. 0x1 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPCMP0 LPCMP LPCMP0 0x0 0x0 0x24 registers n LPCMP0 53 CCR0 Comparator Control Register 0 0x8 32 read-write n 0x0 0x0 CMP_EN Comparator Module Enable 0 1 read-write CMP_EN_0 Analog Comparator is disabled. 0 CMP_EN_1 Analog Comparator is enabled. 0x1 CMP_STOP_EN Comparator Module STOP Mode Enable 1 1 read-write CMP_STOP_EN_0 Comparator is disabled in STOP modes regardless of CMP_EN. 0 CMP_STOP_EN_1 Comparator is enabled in STOP mode if CMP_EN is active 0x1 CCR1 Comparator Control Register 1 0xC 32 read-write n 0x0 0x0 COUT_INV Comparator invert 3 1 read-write COUT_INV_0 Does not invert the comparator output. 0 COUT_INV_1 Inverts the comparator output. 0x1 COUT_PEN Comparator Output Pin Enable 5 1 read-write COUT_PEN_0 no description available 0 COUT_PEN_1 no description available 0x1 COUT_SEL Comparator Output Select 4 1 read-write COUT_SEL_0 Set CMPO to equal COUT (filtered comparator output). 0 COUT_SEL_1 Set CMPO to equal COUTA (unfiltered comparator output). 0x1 DMA_EN DMA Enable 2 1 read-write DMA_EN_0 DMA is disabled. 0 DMA_EN_1 DMA is enabled. 0x1 FILT_CNT Filter Sample Count 16 3 read-write FILT_CNT_0 no description available 0 FILT_CNT_1 1 consecutive sample must agree (comparator output is simply sampled). 0x1 FILT_CNT_2 2 consecutive samples must agree. 0x2 FILT_CNT_3 3 consecutive samples must agree. 0x3 FILT_CNT_4 4 consecutive samples must agree. 0x4 FILT_CNT_5 5 consecutive samples must agree. 0x5 FILT_CNT_6 6 consecutive samples must agree. 0x6 FILT_CNT_7 7 consecutive samples must agree. 0x7 FILT_PER Filter Sample Period 24 8 read-write SAMPLE_EN Sample Enable 1 1 read-write SAMPLE_EN_0 Sampling mode is not selected. 0 SAMPLE_EN_1 Sampling mode is selected. 0x1 WINDOW_EN Windowing Enable 0 1 read-write WINDOW_EN_0 Windowing mode is not selected. 0 WINDOW_EN_1 Windowing mode is selected. 0x1 CCR2 Comparator Control Register 2 0x10 32 read-write n 0x0 0x0 CMP_HPMD CMP High Power Mode Select 0 1 read-write CMP_HPMD_0 Low speed comparison mode is selected.(when CMP_NPMD is 0) 0 CMP_HPMD_1 High speed comparison mode is selected.(when CMP_NPMD is 0) 0x1 CMP_NPMD CMP Nano Power Mode Select 1 1 read-write CMP_NPMD_0 Nano Power Comparator is not enabled (mode is determined by CMP_HPMD) 0 CMP_NPMD_1 Nano Power Comparator is enabled 0x1 HYSTCTR Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level 4 2 read-write HYSTCTR_0 The hard block output has level 0 hysteresis internally. 0 HYSTCTR_1 The hard block output has level 1 hysteresis internally. 0x1 HYSTCTR_2 The hard block output has level 2 hysteresis internally. 0x2 HYSTCTR_3 The hard block output has level 3 hysteresis internally. 0x3 MSEL Minus Input MUX Control 20 3 read-write MSEL_0 Input 0 0 MSEL_1 Input 1 0x1 MSEL_2 Input 2 0x2 MSEL_3 Input 3 0x3 MSEL_4 Input 4 0x4 MSEL_5 Input 5 0x5 MSEL_6 Input 6 0x6 MSEL_7 Internal DAC output 0x7 PSEL Plus Input MUX Control 16 3 read-write PSEL_0 Input 0 0 PSEL_1 Input 1 0x1 PSEL_2 Input 2 0x2 PSEL_3 Input 3 0x3 PSEL_4 Input 4 0x4 PSEL_5 Input 5 0x5 PSEL_6 Input 6 0x6 PSEL_7 Internal DAC output 0x7 CSR Comparator Status Register 0x20 32 read-write n 0x0 0x0 CFF Analog Comparator Flag Falling 1 1 read-write oneToClear CFF_0 A falling edge has not been detected on COUT. 0 CFF_1 A falling edge on COUT has occurred. 0x1 CFR Analog Comparator Flag Rising 0 1 read-write oneToClear CFR_0 A rising edge has not been detected on COUT. 0 CFR_1 A rising edge on COUT has occurred. 0x1 COUT Analog Comparator Output 8 1 read-only DCR DAC Control Register 0x18 32 read-write n 0x0 0x0 DAC_DATA DAC Output Voltage Select 16 6 read-write DAC_EN DAC Enable 0 1 read-write DAC_EN_0 DAC is disabled. 0 DAC_EN_1 DAC is enabled. 0x1 DAC_HPMD DAC High Power Mode Select 1 1 read-write DAC_HPMD_0 DAC high power mode is not enabled. 0 DAC_HPMD_1 DAC high power mode is enabled. 0x1 VRSEL Supply Voltage Reference Source Select 8 1 read-write VRSEL_0 vrefh_int is selected as resistor ladder network supply reference Vin. 0 VRSEL_1 vrefh_ext is selected as resistor ladder network supply reference Vin. 0x1 IER Interrupt Enable Register 0x1C 32 read-write n 0x0 0x0 CFF_IE Comparator Flag Falling Interrupt Enable 1 1 read-write CFF_IE_0 CFF interrupt is disabled. 0 CFF_IE_1 CFF interrupt is enabled. 0x1 CFR_IE Comparator Flag Rising Interrupt Enable 0 1 read-write CFR_IE_0 CFR interrupt is disabled. 0 CFR_IE_1 CFR interrupt is enabled. 0x1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 DAC_RES DAC resolution 0 4 read-only DAC_RES_0 4 bit DAC 0 DAC_RES_1 6 bit DAC 0x1 DAC_RES_2 8 bit DAC 0x2 DAC_RES_3 10 bit DAC 0x3 DAC_RES_4 12 bit DAC 0x4 DAC_RES_5 14 bit DAC 0x5 DAC_RES_6 16 bit DAC 0x6 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only FEATURE_1 Round robin feature 0x1 MAJOR Major Version Number. This read only field returns the major version number for the module specification. 24 8 read-only MINOR Minor Version Number. This read only field returns the minor version number for the module specification. 16 8 read-only LPCMP1 LPCMP LPCMP1 0x0 0x0 0x24 registers n LPCMP1 65 CCR0 Comparator Control Register 0 0x8 32 read-write n 0x0 0x0 CMP_EN Comparator Module Enable 0 1 read-write CMP_EN_0 Analog Comparator is disabled. 0 CMP_EN_1 Analog Comparator is enabled. 0x1 CMP_STOP_EN Comparator Module STOP Mode Enable 1 1 read-write CMP_STOP_EN_0 Comparator is disabled in STOP modes regardless of CMP_EN. 0 CMP_STOP_EN_1 Comparator is enabled in STOP mode if CMP_EN is active 0x1 CCR1 Comparator Control Register 1 0xC 32 read-write n 0x0 0x0 COUT_INV Comparator invert 3 1 read-write COUT_INV_0 Does not invert the comparator output. 0 COUT_INV_1 Inverts the comparator output. 0x1 COUT_PEN Comparator Output Pin Enable 5 1 read-write COUT_PEN_0 no description available 0 COUT_PEN_1 no description available 0x1 COUT_SEL Comparator Output Select 4 1 read-write COUT_SEL_0 Set CMPO to equal COUT (filtered comparator output). 0 COUT_SEL_1 Set CMPO to equal COUTA (unfiltered comparator output). 0x1 DMA_EN DMA Enable 2 1 read-write DMA_EN_0 DMA is disabled. 0 DMA_EN_1 DMA is enabled. 0x1 FILT_CNT Filter Sample Count 16 3 read-write FILT_CNT_0 no description available 0 FILT_CNT_1 1 consecutive sample must agree (comparator output is simply sampled). 0x1 FILT_CNT_2 2 consecutive samples must agree. 0x2 FILT_CNT_3 3 consecutive samples must agree. 0x3 FILT_CNT_4 4 consecutive samples must agree. 0x4 FILT_CNT_5 5 consecutive samples must agree. 0x5 FILT_CNT_6 6 consecutive samples must agree. 0x6 FILT_CNT_7 7 consecutive samples must agree. 0x7 FILT_PER Filter Sample Period 24 8 read-write SAMPLE_EN Sample Enable 1 1 read-write SAMPLE_EN_0 Sampling mode is not selected. 0 SAMPLE_EN_1 Sampling mode is selected. 0x1 WINDOW_EN Windowing Enable 0 1 read-write WINDOW_EN_0 Windowing mode is not selected. 0 WINDOW_EN_1 Windowing mode is selected. 0x1 CCR2 Comparator Control Register 2 0x10 32 read-write n 0x0 0x0 CMP_HPMD CMP High Power Mode Select 0 1 read-write CMP_HPMD_0 Low speed comparison mode is selected.(when CMP_NPMD is 0) 0 CMP_HPMD_1 High speed comparison mode is selected.(when CMP_NPMD is 0) 0x1 CMP_NPMD CMP Nano Power Mode Select 1 1 read-write CMP_NPMD_0 Nano Power Comparator is not enabled (mode is determined by CMP_HPMD) 0 CMP_NPMD_1 Nano Power Comparator is enabled 0x1 HYSTCTR Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level 4 2 read-write HYSTCTR_0 The hard block output has level 0 hysteresis internally. 0 HYSTCTR_1 The hard block output has level 1 hysteresis internally. 0x1 HYSTCTR_2 The hard block output has level 2 hysteresis internally. 0x2 HYSTCTR_3 The hard block output has level 3 hysteresis internally. 0x3 MSEL Minus Input MUX Control 20 3 read-write MSEL_0 Input 0 0 MSEL_1 Input 1 0x1 MSEL_2 Input 2 0x2 MSEL_3 Input 3 0x3 MSEL_4 Input 4 0x4 MSEL_5 Input 5 0x5 MSEL_6 Input 6 0x6 MSEL_7 Internal DAC output 0x7 PSEL Plus Input MUX Control 16 3 read-write PSEL_0 Input 0 0 PSEL_1 Input 1 0x1 PSEL_2 Input 2 0x2 PSEL_3 Input 3 0x3 PSEL_4 Input 4 0x4 PSEL_5 Input 5 0x5 PSEL_6 Input 6 0x6 PSEL_7 Internal DAC output 0x7 CSR Comparator Status Register 0x20 32 read-write n 0x0 0x0 CFF Analog Comparator Flag Falling 1 1 read-write oneToClear CFF_0 A falling edge has not been detected on COUT. 0 CFF_1 A falling edge on COUT has occurred. 0x1 CFR Analog Comparator Flag Rising 0 1 read-write oneToClear CFR_0 A rising edge has not been detected on COUT. 0 CFR_1 A rising edge on COUT has occurred. 0x1 COUT Analog Comparator Output 8 1 read-only DCR DAC Control Register 0x18 32 read-write n 0x0 0x0 DAC_DATA DAC Output Voltage Select 16 6 read-write DAC_EN DAC Enable 0 1 read-write DAC_EN_0 DAC is disabled. 0 DAC_EN_1 DAC is enabled. 0x1 DAC_HPMD DAC High Power Mode Select 1 1 read-write DAC_HPMD_0 DAC high power mode is not enabled. 0 DAC_HPMD_1 DAC high power mode is enabled. 0x1 VRSEL Supply Voltage Reference Source Select 8 1 read-write VRSEL_0 vrefh_int is selected as resistor ladder network supply reference Vin. 0 VRSEL_1 vrefh_ext is selected as resistor ladder network supply reference Vin. 0x1 IER Interrupt Enable Register 0x1C 32 read-write n 0x0 0x0 CFF_IE Comparator Flag Falling Interrupt Enable 1 1 read-write CFF_IE_0 CFF interrupt is disabled. 0 CFF_IE_1 CFF interrupt is enabled. 0x1 CFR_IE Comparator Flag Rising Interrupt Enable 0 1 read-write CFR_IE_0 CFR interrupt is disabled. 0 CFR_IE_1 CFR interrupt is enabled. 0x1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 DAC_RES DAC resolution 0 4 read-only DAC_RES_0 4 bit DAC 0 DAC_RES_1 6 bit DAC 0x1 DAC_RES_2 8 bit DAC 0x2 DAC_RES_3 10 bit DAC 0x3 DAC_RES_4 12 bit DAC 0x4 DAC_RES_5 14 bit DAC 0x5 DAC_RES_6 16 bit DAC 0x6 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only FEATURE_1 Round robin feature 0x1 MAJOR Major Version Number. This read only field returns the major version number for the module specification. 24 8 read-only MINOR Minor Version Number. This read only field returns the minor version number for the module specification. 16 8 read-only LPDAC0 LPDAC LPDAC0 0x0 0x0 0x2C registers n LPDAC0 54 DATA DAC Data Register 0x8 32 read-write n 0x0 0x0 DATA In FIFO mode or swing back mode, this is the FIFO data entry. In buffer mode, write to this field will push the data to analog without trigger support. This field is write only and always read zero. 0 12 write-only DER DAC DMA Enable Register 0x20 32 read-write n 0x0 0x0 EMPTY_DMAEN FIFO Empty DMA Enable 1 1 read-write EMPTY_DMAEN_0 FIFO Empty DMA request is disabled. 0 EMPTY_DMAEN_1 FIFO Empty DMA request is enabled. 0x1 WM_DMAEN FIFO Watermark DMA Enable 2 1 read-write WM_DMAEN_0 Watermark DMA request is disabled. 0 WM_DMAEN_1 Watermark DMA request is enabled. 0x1 FCR DAC FIFO Control Register 0x10 32 read-write n 0x0 0x0 WML Watermark Level 0 4 read-write FPR DAC FIFO Pointer Register 0x14 32 read-only n 0x0 0x0 FIFO_RPT FIFO Read Pointer 0 4 read-only FIFO_WPT FIFO Write Pointer 16 4 read-only FSR FIFO Status Register 0x18 32 read-write n 0x0 0x0 EMPTY FIFO Empty Flag 1 1 read-only EMPTY_0 FIFO is not empty 0 EMPTY_1 FIFO is empty 0x1 FULL FIFO Full Flag 0 1 read-only FULL_0 FIFO is not full 0 FULL_1 FIFO is full 0x1 OF FIFO Overflow Flag 6 1 read-write oneToClear OF_0 No overflow has occurred since the last time the flag was cleared. 0 OF_1 At least one FIFO overflow has occurred since the last time the flag was cleared. 0x1 SWBK Swing Back One Cycle Complete Flag 3 1 read-write oneToClear SWBK_0 No swing back cycle has completed since the last time the flag was cleared. 0 SWBK_1 At least one swing back cycle has occurred since the last time the flag was cleared. 0x1 UF FIFO Underflow Flag 7 1 read-write oneToClear UF_0 No underflow has occurred since the last time the flag was cleared. 0 UF_1 At least one trigger underflow has occurred since the last time the flag was cleared. 0x1 WM FIFO Watermark Status Flag 2 1 read-only WM_0 Data in FIFO is more than watermark level 0 WM_1 Data in FIFO is less than or equal to watermark level 0x1 GCR DAC Global Control Register 0xC 32 read-write n 0x0 0x0 DACEN DAC Enable 0 1 read-write DACEN_0 The DAC system is disabled. 0 DACEN_1 The DAC system is enabled. 0x1 DACRFS DAC Reference Select 1 1 read-write DACRFS_0 The DAC selects VREFH_INT as the reference voltage. 0 DACRFS_1 The DAC selects VREFH_EXT as the reference voltage. 0x1 FIFOEN FIFO Enable 3 1 read-write FIFOEN_0 FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes to buffer then goes to conversion. 0 FIFOEN_1 FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to conversion 0x1 LPEN Low Power Enable 2 1 read-write LPEN_0 High-Power mode 0 LPEN_1 Low-Power mode 0x1 SWMD Swing Back Mode 4 1 read-write SWMD_0 Swing back mode disable 0 SWMD_1 Swing back mode enable 0x1 TRGSEL DAC Trigger Select 5 1 read-write TRGSEL_0 The DAC hardware trigger is selected. 0 TRGSEL_1 The DAC software trigger is selected. 0x1 IER DAC Interrupt Enable Register 0x1C 32 read-write n 0x0 0x0 EMPTY_IE FIFO Empty Interrupt Enable 1 1 read-write EMPTY_IE_0 FIFO Empty interrupt is disabled. 0 EMPTY_IE_1 FIFO Empty interrupt is enabled. 0x1 FULL_IE FIFO Full Interrupt Enable 0 1 read-write FULL_IE_0 FIFO Full interrupt is disabled. 0 FULL_IE_1 FIFO Full interrupt is enabled. 0x1 OF_IE FIFO Overflow Interrupt Enable 6 1 read-write OF_IE_0 Overflow interrupt is disabled 0 OF_IE_1 Overflow interrupt is enabled. 0x1 SWBK_IE Swing back One Cycle Complete Interrupt Enable 3 1 read-write SWBK_IE_0 Swing back one time complete interrupt is disabled. 0 SWBK_IE_1 Swing back one time complete interrupt is enabled. 0x1 UF_IE FIFO Underflow Interrupt Enable 7 1 read-write UF_IE_0 Underflow interrupt is disabled. 0 UF_IE_1 Underflow interrupt is enabled. 0x1 WM_IE FIFO Watermark Interrupt Enable 2 1 read-write WM_IE_0 Watermark interrupt is disabled. 0 WM_IE_1 Watermark interrupt is enabled. 0x1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 FIFOSZ FIFO size 0 3 read-only FIFOSZ_1 FIFO depth is 4 0x1 FIFOSZ_2 FIFO depth is 8 0x2 FIFOSZ_3 FIFO depth is 16 0x3 FIFOSZ_4 FIFO depth is 32 0x4 FIFOSZ_5 FIFO depth is 64 0x5 FIFOSZ_6 FIFO depth is 128 0x6 FIFOSZ_7 FIFO depth is 256 0x7 RCR DAC Reset Control Register 0x24 32 read-write n 0x0 0x0 FIFORST FIFO Reset 1 1 read-write FIFORST_0 No effect 0 FIFORST_1 FIFO reset 0x1 SWRST Software Reset 0 1 read-write SWRST_0 No effect 0 SWRST_1 Software reset 0x1 TCR DAC Trigger Control Register 0x28 32 read-write n 0x0 0x0 SWTRG Software Trigger 0 1 write-only SWTRG_0 The DAC soft trigger is not valid. 0 SWTRG_1 The DAC soft trigger is valid. 0x1 VERID Version Identifier Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Identification Number 0 16 read-only MAJOR Major version number 24 8 read-only MINOR Minor version number 16 8 read-only LPI2C0 LPI2C LPI2C0 0x0 0x0 0x174 registers n LPI2C0 36 MCCR0 Master Clock Configuration Register 0 0x48 32 read-write n 0x0 0x0 CLKHI Clock High Period 8 6 read-write CLKLO Clock Low Period 0 6 read-write DATAVD Data Valid Delay 24 6 read-write SETHOLD Setup Hold Delay 16 6 read-write MCCR1 Master Clock Configuration Register 1 0x50 32 read-write n 0x0 0x0 CLKHI Clock High Period 8 6 read-write CLKLO Clock Low Period 0 6 read-write DATAVD Data Valid Delay 24 6 read-write SETHOLD Setup Hold Delay 16 6 read-write MCFGR0 Master Configuration Register 0 0x20 32 read-write n 0x0 0x0 CIRFIFO Circular FIFO Enable 8 1 read-write CIRFIFO_0 Circular FIFO is disabled 0 CIRFIFO_1 Circular FIFO is enabled 0x1 HREN Host Request Enable 0 1 read-write HREN_0 Host request input is disabled 0 HREN_1 Host request input is enabled 0x1 HRPOL Host Request Polarity 1 1 read-write HRPOL_0 Active low 0 HRPOL_1 Active high 0x1 HRSEL Host Request Select 2 1 read-write HRSEL_0 Host request input is pin HREQ 0 HRSEL_1 Host request input is input trigger 0x1 RDMO Receive Data Match Only 9 1 read-write RDMO_0 Received data is stored in the receive FIFO 0 RDMO_1 Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set 0x1 MCFGR1 Master Configuration Register 1 0x24 32 read-write n 0x0 0x0 AUTOSTOP Automatic STOP Generation 8 1 read-write AUTOSTOP_0 No effect 0 AUTOSTOP_1 STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy 0x1 IGNACK IGNACK 9 1 read-write IGNACK_0 LPI2C Master will receive ACK and NACK normally 0 IGNACK_1 LPI2C Master will treat a received NACK as if it (NACK) was an ACK 0x1 MATCFG Match Configuration 16 3 read-write MATCFG_0 Match is disabled 0 MATCFG_2 Match is enabled (1st data word equals MATCH0 OR MATCH1) 0x2 MATCFG_3 Match is enabled (any data word equals MATCH0 OR MATCH1) 0x3 MATCFG_4 Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) 0x4 MATCFG_5 Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) 0x5 MATCFG_6 Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) 0x6 MATCFG_7 Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) 0x7 PINCFG Pin Configuration 24 3 read-write PINCFG_0 2-pin open drain mode 0 PINCFG_1 2-pin output only mode (ultra-fast mode) 0x1 PINCFG_2 2-pin push-pull mode 0x2 PINCFG_3 4-pin push-pull mode 0x3 PINCFG_4 2-pin open drain mode with separate LPI2C slave 0x4 PINCFG_5 2-pin output only mode (ultra-fast mode) with separate LPI2C slave 0x5 PINCFG_6 2-pin push-pull mode with separate LPI2C slave 0x6 PINCFG_7 4-pin push-pull mode (inverted outputs) 0x7 PRESCALE Prescaler 0 3 read-write PRESCALE_0 Divide by 1 0 PRESCALE_1 Divide by 2 0x1 PRESCALE_2 Divide by 4 0x2 PRESCALE_3 Divide by 8 0x3 PRESCALE_4 Divide by 16 0x4 PRESCALE_5 Divide by 32 0x5 PRESCALE_6 Divide by 64 0x6 PRESCALE_7 Divide by 128 0x7 TIMECFG Timeout Configuration 10 1 read-write TIMECFG_0 Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout 0 TIMECFG_1 Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout 0x1 MCFGR2 Master Configuration Register 2 0x28 32 read-write n 0x0 0x0 BUSIDLE Bus Idle Timeout 0 12 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write MCFGR3 Master Configuration Register 3 0x2C 32 read-write n 0x0 0x0 PINLOW Pin Low Timeout 8 12 read-write MCR Master Control Register 0x10 32 read-write n 0x0 0x0 DBGEN Debug Enable 3 1 read-write DBGEN_0 Master is disabled in debug mode 0 DBGEN_1 Master is enabled in debug mode 0x1 DOZEN Doze mode enable 2 1 read-write DOZEN_0 Master is enabled in Doze mode 0 DOZEN_1 Master is disabled in Doze mode 0x1 MEN Master Enable 0 1 read-write MEN_0 Master logic is disabled 0 MEN_1 Master logic is enabled 0x1 RRF Reset Receive FIFO 9 1 write-only RRF_0 No effect 0 RRF_1 Receive FIFO is reset 0x1 RST Software Reset 1 1 read-write RST_0 Master logic is not reset 0 RST_1 Master logic is reset 0x1 RTF Reset Transmit FIFO 8 1 write-only RTF_0 No effect 0 RTF_1 Transmit FIFO is reset 0x1 MDER Master DMA Enable Register 0x1C 32 read-write n 0x0 0x0 RDDE Receive Data DMA Enable 1 1 read-write RDDE_0 DMA request is disabled 0 RDDE_1 DMA request is enabled 0x1 TDDE Transmit Data DMA Enable 0 1 read-write TDDE_0 DMA request is disabled 0 TDDE_1 DMA request is enabled 0x1 MDMR Master Data Match Register 0x40 32 read-write n 0x0 0x0 MATCH0 Match 0 Value 0 8 read-write MATCH1 Match 1 Value 16 8 read-write MFCR Master FIFO Control Register 0x58 32 read-write n 0x0 0x0 RXWATER Receive FIFO Watermark 16 2 read-write TXWATER Transmit FIFO Watermark 0 2 read-write MFSR Master FIFO Status Register 0x5C 32 read-only n 0x0 0x0 RXCOUNT Receive FIFO Count 16 3 read-only TXCOUNT Transmit FIFO Count 0 3 read-only MIER Master Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 ALIE Arbitration Lost Interrupt Enable 11 1 read-write ALIE_0 Disabled 0 ALIE_1 Enabled 0x1 DMIE Data Match Interrupt Enable 14 1 read-write DMIE_0 Disabled 0 DMIE_1 Enabled 0x1 EPIE End Packet Interrupt Enable 8 1 read-write EPIE_0 Disabled 0 EPIE_1 Enabled 0x1 FEIE FIFO Error Interrupt Enable 12 1 read-write FEIE_0 Enabled 0 FEIE_1 Disabled 0x1 NDIE NACK Detect Interrupt Enable 10 1 read-write NDIE_0 Disabled 0 NDIE_1 Enabled 0x1 PLTIE Pin Low Timeout Interrupt Enable 13 1 read-write PLTIE_0 Disabled 0 PLTIE_1 Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write RDIE_0 Disabled 0 RDIE_1 Enabled 0x1 SDIE STOP Detect Interrupt Enable 9 1 read-write SDIE_0 Disabled 0 SDIE_1 Enabled 0x1 TDIE Transmit Data Interrupt Enable 0 1 read-write TDIE_0 Disabled 0 TDIE_1 Enabled 0x1 MRDR Master Receive Data Register 0x70 32 read-only n 0x0 0x0 DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only RXEMPTY_0 Receive FIFO is not empty 0 RXEMPTY_1 Receive FIFO is empty 0x1 MSR Master Status Register 0x14 32 read-write n 0x0 0x0 ALF Arbitration Lost Flag 11 1 read-write oneToClear ALF_0 Master has not lost arbitration 0 ALF_1 Master has lost arbitration 0x1 BBF Bus Busy Flag 25 1 read-only BBF_0 I2C Bus is idle 0 BBF_1 I2C Bus is busy 0x1 DMF Data Match Flag 14 1 read-write oneToClear DMF_0 Have not received matching data 0 DMF_1 Have received matching data 0x1 EPF End Packet Flag 8 1 read-write oneToClear EPF_0 Master has not generated a STOP or Repeated START condition 0 EPF_1 Master has generated a STOP or Repeated START condition 0x1 FEF FIFO Error Flag 12 1 read-write oneToClear FEF_0 No error 0 FEF_1 Master sending or receiving data without a START condition 0x1 MBF Master Busy Flag 24 1 read-only MBF_0 I2C Master is idle 0 MBF_1 I2C Master is busy 0x1 NDF NACK Detect Flag 10 1 read-write oneToClear NDF_0 Unexpected NACK was not detected 0 NDF_1 Unexpected NACK was detected 0x1 PLTF Pin Low Timeout Flag 13 1 read-write oneToClear PLTF_0 Pin low timeout has not occurred or is disabled 0 PLTF_1 Pin low timeout has occurred 0x1 RDF Receive Data Flag 1 1 read-only RDF_0 Receive Data is not ready 0 RDF_1 Receive data is ready 0x1 SDF STOP Detect Flag 9 1 read-write oneToClear SDF_0 Master has not generated a STOP condition 0 SDF_1 Master has generated a STOP condition 0x1 TDF Transmit Data Flag 0 1 read-only TDF_0 Transmit data is not requested 0 TDF_1 Transmit data is requested 0x1 MTDR Master Transmit Data Register 0x60 32 read-write n 0x0 0x0 CMD Command Data 8 3 write-only CMD_0 Transmit DATA[7:0] 0 CMD_1 Receive (DATA[7:0] + 1) bytes 0x1 CMD_2 Generate STOP condition 0x2 CMD_3 Receive and discard (DATA[7:0] + 1) bytes 0x3 CMD_4 Generate (repeated) START and transmit address in DATA[7:0] 0x4 CMD_5 Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. 0x5 CMD_6 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode 0x6 CMD_7 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. 0x7 DATA Transmit Data 0 8 write-only PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 MRXFIFO Master Receive FIFO Size 8 4 read-only MTXFIFO Master Transmit FIFO Size 0 4 read-only SAMR Slave Address Match Register 0x140 32 read-write n 0x0 0x0 ADDR0 Address 0 Value 1 10 read-write ADDR1 Address 1 Value 17 10 read-write SASR Slave Address Status Register 0x150 32 read-only n 0x0 0x0 ANV Address Not Valid 14 1 read-only ANV_0 Received Address (RADDR) is valid 0 ANV_1 Received Address (RADDR) is not valid 0x1 RADDR Received Address 0 11 read-only SCFGR1 Slave Configuration Register 1 0x124 32 read-write n 0x0 0x0 ACKSTALL ACK SCL Stall 3 1 read-write ACKSTALL_0 Clock stretching is disabled 0 ACKSTALL_1 Clock stretching is enabled 0x1 ADDRCFG Address Configuration 16 3 read-write ADDRCFG_0 Address match 0 (7-bit) 0 ADDRCFG_1 Address match 0 (10-bit) 0x1 ADDRCFG_2 Address match 0 (7-bit) or Address match 1 (7-bit) 0x2 ADDRCFG_3 Address match 0 (10-bit) or Address match 1 (10-bit) 0x3 ADDRCFG_4 Address match 0 (7-bit) or Address match 1 (10-bit) 0x4 ADDRCFG_5 Address match 0 (10-bit) or Address match 1 (7-bit) 0x5 ADDRCFG_6 From Address match 0 (7-bit) to Address match 1 (7-bit) 0x6 ADDRCFG_7 From Address match 0 (10-bit) to Address match 1 (10-bit) 0x7 ADRSTALL Address SCL Stall 0 1 read-write ADRSTALL_0 Clock stretching is disabled 0 ADRSTALL_1 Clock stretching is enabled 0x1 GCEN General Call Enable 8 1 read-write GCEN_0 General Call address is disabled 0 GCEN_1 General Call address is enabled 0x1 HSMEN High Speed Mode Enable 13 1 read-write HSMEN_0 Disables detection of HS-mode master code 0 HSMEN_1 Enables detection of HS-mode master code 0x1 IGNACK Ignore NACK 12 1 read-write IGNACK_0 Slave will end transfer when NACK is detected 0 IGNACK_1 Slave will not end transfer when NACK detected 0x1 RXCFG Receive Data Configuration 11 1 read-write RXCFG_0 Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). 0 RXCFG_1 Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). 0x1 RXSTALL RX SCL Stall 1 1 read-write RXSTALL_0 Clock stretching is disabled 0 RXSTALL_1 Clock stretching is enabled 0x1 SAEN SMBus Alert Enable 9 1 read-write SAEN_0 Disables match on SMBus Alert 0 SAEN_1 Enables match on SMBus Alert 0x1 TXCFG Transmit Flag Configuration 10 1 read-write TXCFG_0 Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty 0 TXCFG_1 Transmit Data Flag will assert whenever the Transmit Data register is empty 0x1 TXDSTALL TX Data SCL Stall 2 1 read-write TXDSTALL_0 Clock stretching is disabled 0 TXDSTALL_1 Clock stretching is enabled 0x1 SCFGR2 Slave Configuration Register 2 0x128 32 read-write n 0x0 0x0 CLKHOLD Clock Hold Time 0 4 read-write DATAVD Data Valid Delay 8 6 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write SCR Slave Control Register 0x110 32 read-write n 0x0 0x0 FILTDZ Filter Doze Enable 5 1 read-write FILTDZ_0 Filter remains enabled in Doze mode 0 FILTDZ_1 Filter is disabled in Doze mode 0x1 FILTEN Filter Enable 4 1 read-write FILTEN_0 Disable digital filter and output delay counter for slave mode 0 FILTEN_1 Enable digital filter and output delay counter for slave mode 0x1 RRF Reset Receive FIFO 9 1 write-only RRF_0 No effect 0 RRF_1 Receive Data Register is now empty 0x1 RST Software Reset 1 1 read-write RST_0 Slave mode logic is not reset 0 RST_1 Slave mode logic is reset 0x1 RTF Reset Transmit FIFO 8 1 write-only RTF_0 No effect 0 RTF_1 Transmit Data Register is now empty 0x1 SEN Slave Enable 0 1 read-write SEN_0 I2C Slave mode is disabled 0 SEN_1 I2C Slave mode is enabled 0x1 SDER Slave DMA Enable Register 0x11C 32 read-write n 0x0 0x0 AVDE Address Valid DMA Enable 2 1 read-write AVDE_0 DMA request is disabled 0 AVDE_1 DMA request is enabled 0x1 RDDE Receive Data DMA Enable 1 1 read-write RDDE_0 DMA request is disabled 0 RDDE_1 DMA request is enabled 0x1 TDDE Transmit Data DMA Enable 0 1 read-write TDDE_0 DMA request is disabled 0 TDDE_1 DMA request is enabled 0x1 SIER Slave Interrupt Enable Register 0x118 32 read-write n 0x0 0x0 AM0IE Address Match 0 Interrupt Enable 12 1 read-write AM0IE_0 Enabled 0 AM0IE_1 Disabled 0x1 AM1F Address Match 1 Interrupt Enable 13 1 read-write AM1F_0 Disabled 0 AM1F_1 Enabled 0x1 AVIE Address Valid Interrupt Enable 2 1 read-write AVIE_0 Disabled 0 AVIE_1 Enabled 0x1 BEIE Bit Error Interrupt Enable 10 1 read-write BEIE_0 Disabled 0 BEIE_1 Enabled 0x1 FEIE FIFO Error Interrupt Enable 11 1 read-write FEIE_0 Disabled 0 FEIE_1 Enabled 0x1 GCIE General Call Interrupt Enable 14 1 read-write GCIE_0 Disabled 0 GCIE_1 Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write RDIE_0 Disabled 0 RDIE_1 Enabled 0x1 RSIE Repeated Start Interrupt Enable 8 1 read-write RSIE_0 Disabled 0 RSIE_1 Enabled 0x1 SARIE SMBus Alert Response Interrupt Enable 15 1 read-write SARIE_0 Disabled 0 SARIE_1 Enabled 0x1 SDIE STOP Detect Interrupt Enable 9 1 read-write SDIE_0 Disabled 0 SDIE_1 Enabled 0x1 TAIE Transmit ACK Interrupt Enable 3 1 read-write TAIE_0 Disabled 0 TAIE_1 Enabled 0x1 TDIE Transmit Data Interrupt Enable 0 1 read-write TDIE_0 Disabled 0 TDIE_1 Enabled 0x1 SRDR Slave Receive Data Register 0x170 32 read-only n 0x0 0x0 DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only RXEMPTY_0 The Receive Data Register is not empty 0 RXEMPTY_1 The Receive Data Register is empty 0x1 SOF Start Of Frame 15 1 read-only SOF_0 Indicates this is not the first data word since a (repeated) START or STOP condition 0 SOF_1 Indicates this is the first data word since a (repeated) START or STOP condition 0x1 SSR Slave Status Register 0x114 32 read-write n 0x0 0x0 AM0F Address Match 0 Flag 12 1 read-only AM0F_0 Have not received an ADDR0 matching address 0 AM0F_1 Have received an ADDR0 matching address 0x1 AM1F Address Match 1 Flag 13 1 read-only AM1F_0 Have not received an ADDR1 or ADDR0/ADDR1 range matching address 0 AM1F_1 Have received an ADDR1 or ADDR0/ADDR1 range matching address 0x1 AVF Address Valid Flag 2 1 read-only AVF_0 Address Status Register is not valid 0 AVF_1 Address Status Register is valid 0x1 BBF Bus Busy Flag 25 1 read-only BBF_0 I2C Bus is idle 0 BBF_1 I2C Bus is busy 0x1 BEF Bit Error Flag 10 1 read-write oneToClear BEF_0 Slave has not detected a bit error 0 BEF_1 Slave has detected a bit error 0x1 FEF FIFO Error Flag 11 1 read-write oneToClear FEF_0 FIFO underflow or overflow was not detected 0 FEF_1 FIFO underflow or overflow was detected 0x1 GCF General Call Flag 14 1 read-only GCF_0 Slave has not detected the General Call Address or the General Call Address is disabled 0 GCF_1 Slave has detected the General Call Address 0x1 RDF Receive Data Flag 1 1 read-only RDF_0 Receive data is not ready 0 RDF_1 Receive data is ready 0x1 RSF Repeated Start Flag 8 1 read-write oneToClear RSF_0 Slave has not detected a Repeated START condition 0 RSF_1 Slave has detected a Repeated START condition 0x1 SARF SMBus Alert Response Flag 15 1 read-only SARF_0 SMBus Alert Response is disabled or not detected 0 SARF_1 SMBus Alert Response is enabled and detected 0x1 SBF Slave Busy Flag 24 1 read-only SBF_0 I2C Slave is idle 0 SBF_1 I2C Slave is busy 0x1 SDF STOP Detect Flag 9 1 read-write oneToClear SDF_0 Slave has not detected a STOP condition 0 SDF_1 Slave has detected a STOP condition 0x1 TAF Transmit ACK Flag 3 1 read-only TAF_0 Transmit ACK/NACK is not required 0 TAF_1 Transmit ACK/NACK is required 0x1 TDF Transmit Data Flag 0 1 read-only TDF_0 Transmit data not requested 0 TDF_1 Transmit data is requested 0x1 STAR Slave Transmit ACK Register 0x154 32 read-write n 0x0 0x0 TXNACK Transmit NACK 0 1 read-write TXNACK_0 Write a Transmit ACK for each received word 0 TXNACK_1 Write a Transmit NACK for each received word 0x1 STDR Slave Transmit Data Register 0x160 32 read-write n 0x0 0x0 DATA Transmit Data 0 8 write-only VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only FEATURE_2 Master only, with standard feature set 0x2 FEATURE_3 Master and slave, with standard feature set 0x3 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPI2C1 LPI2C LPI2C1 0x0 0x0 0x174 registers n LPI2C1 37 MCCR0 Master Clock Configuration Register 0 0x48 32 read-write n 0x0 0x0 CLKHI Clock High Period 8 6 read-write CLKLO Clock Low Period 0 6 read-write DATAVD Data Valid Delay 24 6 read-write SETHOLD Setup Hold Delay 16 6 read-write MCCR1 Master Clock Configuration Register 1 0x50 32 read-write n 0x0 0x0 CLKHI Clock High Period 8 6 read-write CLKLO Clock Low Period 0 6 read-write DATAVD Data Valid Delay 24 6 read-write SETHOLD Setup Hold Delay 16 6 read-write MCFGR0 Master Configuration Register 0 0x20 32 read-write n 0x0 0x0 CIRFIFO Circular FIFO Enable 8 1 read-write CIRFIFO_0 Circular FIFO is disabled 0 CIRFIFO_1 Circular FIFO is enabled 0x1 HREN Host Request Enable 0 1 read-write HREN_0 Host request input is disabled 0 HREN_1 Host request input is enabled 0x1 HRPOL Host Request Polarity 1 1 read-write HRPOL_0 Active low 0 HRPOL_1 Active high 0x1 HRSEL Host Request Select 2 1 read-write HRSEL_0 Host request input is pin HREQ 0 HRSEL_1 Host request input is input trigger 0x1 RDMO Receive Data Match Only 9 1 read-write RDMO_0 Received data is stored in the receive FIFO 0 RDMO_1 Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set 0x1 MCFGR1 Master Configuration Register 1 0x24 32 read-write n 0x0 0x0 AUTOSTOP Automatic STOP Generation 8 1 read-write AUTOSTOP_0 No effect 0 AUTOSTOP_1 STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy 0x1 IGNACK IGNACK 9 1 read-write IGNACK_0 LPI2C Master will receive ACK and NACK normally 0 IGNACK_1 LPI2C Master will treat a received NACK as if it (NACK) was an ACK 0x1 MATCFG Match Configuration 16 3 read-write MATCFG_0 Match is disabled 0 MATCFG_2 Match is enabled (1st data word equals MATCH0 OR MATCH1) 0x2 MATCFG_3 Match is enabled (any data word equals MATCH0 OR MATCH1) 0x3 MATCFG_4 Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) 0x4 MATCFG_5 Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) 0x5 MATCFG_6 Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) 0x6 MATCFG_7 Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) 0x7 PINCFG Pin Configuration 24 3 read-write PINCFG_0 2-pin open drain mode 0 PINCFG_1 2-pin output only mode (ultra-fast mode) 0x1 PINCFG_2 2-pin push-pull mode 0x2 PINCFG_3 4-pin push-pull mode 0x3 PINCFG_4 2-pin open drain mode with separate LPI2C slave 0x4 PINCFG_5 2-pin output only mode (ultra-fast mode) with separate LPI2C slave 0x5 PINCFG_6 2-pin push-pull mode with separate LPI2C slave 0x6 PINCFG_7 4-pin push-pull mode (inverted outputs) 0x7 PRESCALE Prescaler 0 3 read-write PRESCALE_0 Divide by 1 0 PRESCALE_1 Divide by 2 0x1 PRESCALE_2 Divide by 4 0x2 PRESCALE_3 Divide by 8 0x3 PRESCALE_4 Divide by 16 0x4 PRESCALE_5 Divide by 32 0x5 PRESCALE_6 Divide by 64 0x6 PRESCALE_7 Divide by 128 0x7 TIMECFG Timeout Configuration 10 1 read-write TIMECFG_0 Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout 0 TIMECFG_1 Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout 0x1 MCFGR2 Master Configuration Register 2 0x28 32 read-write n 0x0 0x0 BUSIDLE Bus Idle Timeout 0 12 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write MCFGR3 Master Configuration Register 3 0x2C 32 read-write n 0x0 0x0 PINLOW Pin Low Timeout 8 12 read-write MCR Master Control Register 0x10 32 read-write n 0x0 0x0 DBGEN Debug Enable 3 1 read-write DBGEN_0 Master is disabled in debug mode 0 DBGEN_1 Master is enabled in debug mode 0x1 DOZEN Doze mode enable 2 1 read-write DOZEN_0 Master is enabled in Doze mode 0 DOZEN_1 Master is disabled in Doze mode 0x1 MEN Master Enable 0 1 read-write MEN_0 Master logic is disabled 0 MEN_1 Master logic is enabled 0x1 RRF Reset Receive FIFO 9 1 write-only RRF_0 No effect 0 RRF_1 Receive FIFO is reset 0x1 RST Software Reset 1 1 read-write RST_0 Master logic is not reset 0 RST_1 Master logic is reset 0x1 RTF Reset Transmit FIFO 8 1 write-only RTF_0 No effect 0 RTF_1 Transmit FIFO is reset 0x1 MDER Master DMA Enable Register 0x1C 32 read-write n 0x0 0x0 RDDE Receive Data DMA Enable 1 1 read-write RDDE_0 DMA request is disabled 0 RDDE_1 DMA request is enabled 0x1 TDDE Transmit Data DMA Enable 0 1 read-write TDDE_0 DMA request is disabled 0 TDDE_1 DMA request is enabled 0x1 MDMR Master Data Match Register 0x40 32 read-write n 0x0 0x0 MATCH0 Match 0 Value 0 8 read-write MATCH1 Match 1 Value 16 8 read-write MFCR Master FIFO Control Register 0x58 32 read-write n 0x0 0x0 RXWATER Receive FIFO Watermark 16 2 read-write TXWATER Transmit FIFO Watermark 0 2 read-write MFSR Master FIFO Status Register 0x5C 32 read-only n 0x0 0x0 RXCOUNT Receive FIFO Count 16 3 read-only TXCOUNT Transmit FIFO Count 0 3 read-only MIER Master Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 ALIE Arbitration Lost Interrupt Enable 11 1 read-write ALIE_0 Disabled 0 ALIE_1 Enabled 0x1 DMIE Data Match Interrupt Enable 14 1 read-write DMIE_0 Disabled 0 DMIE_1 Enabled 0x1 EPIE End Packet Interrupt Enable 8 1 read-write EPIE_0 Disabled 0 EPIE_1 Enabled 0x1 FEIE FIFO Error Interrupt Enable 12 1 read-write FEIE_0 Enabled 0 FEIE_1 Disabled 0x1 NDIE NACK Detect Interrupt Enable 10 1 read-write NDIE_0 Disabled 0 NDIE_1 Enabled 0x1 PLTIE Pin Low Timeout Interrupt Enable 13 1 read-write PLTIE_0 Disabled 0 PLTIE_1 Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write RDIE_0 Disabled 0 RDIE_1 Enabled 0x1 SDIE STOP Detect Interrupt Enable 9 1 read-write SDIE_0 Disabled 0 SDIE_1 Enabled 0x1 TDIE Transmit Data Interrupt Enable 0 1 read-write TDIE_0 Disabled 0 TDIE_1 Enabled 0x1 MRDR Master Receive Data Register 0x70 32 read-only n 0x0 0x0 DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only RXEMPTY_0 Receive FIFO is not empty 0 RXEMPTY_1 Receive FIFO is empty 0x1 MSR Master Status Register 0x14 32 read-write n 0x0 0x0 ALF Arbitration Lost Flag 11 1 read-write oneToClear ALF_0 Master has not lost arbitration 0 ALF_1 Master has lost arbitration 0x1 BBF Bus Busy Flag 25 1 read-only BBF_0 I2C Bus is idle 0 BBF_1 I2C Bus is busy 0x1 DMF Data Match Flag 14 1 read-write oneToClear DMF_0 Have not received matching data 0 DMF_1 Have received matching data 0x1 EPF End Packet Flag 8 1 read-write oneToClear EPF_0 Master has not generated a STOP or Repeated START condition 0 EPF_1 Master has generated a STOP or Repeated START condition 0x1 FEF FIFO Error Flag 12 1 read-write oneToClear FEF_0 No error 0 FEF_1 Master sending or receiving data without a START condition 0x1 MBF Master Busy Flag 24 1 read-only MBF_0 I2C Master is idle 0 MBF_1 I2C Master is busy 0x1 NDF NACK Detect Flag 10 1 read-write oneToClear NDF_0 Unexpected NACK was not detected 0 NDF_1 Unexpected NACK was detected 0x1 PLTF Pin Low Timeout Flag 13 1 read-write oneToClear PLTF_0 Pin low timeout has not occurred or is disabled 0 PLTF_1 Pin low timeout has occurred 0x1 RDF Receive Data Flag 1 1 read-only RDF_0 Receive Data is not ready 0 RDF_1 Receive data is ready 0x1 SDF STOP Detect Flag 9 1 read-write oneToClear SDF_0 Master has not generated a STOP condition 0 SDF_1 Master has generated a STOP condition 0x1 TDF Transmit Data Flag 0 1 read-only TDF_0 Transmit data is not requested 0 TDF_1 Transmit data is requested 0x1 MTDR Master Transmit Data Register 0x60 32 read-write n 0x0 0x0 CMD Command Data 8 3 write-only CMD_0 Transmit DATA[7:0] 0 CMD_1 Receive (DATA[7:0] + 1) bytes 0x1 CMD_2 Generate STOP condition 0x2 CMD_3 Receive and discard (DATA[7:0] + 1) bytes 0x3 CMD_4 Generate (repeated) START and transmit address in DATA[7:0] 0x4 CMD_5 Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. 0x5 CMD_6 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode 0x6 CMD_7 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. 0x7 DATA Transmit Data 0 8 write-only PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 MRXFIFO Master Receive FIFO Size 8 4 read-only MTXFIFO Master Transmit FIFO Size 0 4 read-only SAMR Slave Address Match Register 0x140 32 read-write n 0x0 0x0 ADDR0 Address 0 Value 1 10 read-write ADDR1 Address 1 Value 17 10 read-write SASR Slave Address Status Register 0x150 32 read-only n 0x0 0x0 ANV Address Not Valid 14 1 read-only ANV_0 Received Address (RADDR) is valid 0 ANV_1 Received Address (RADDR) is not valid 0x1 RADDR Received Address 0 11 read-only SCFGR1 Slave Configuration Register 1 0x124 32 read-write n 0x0 0x0 ACKSTALL ACK SCL Stall 3 1 read-write ACKSTALL_0 Clock stretching is disabled 0 ACKSTALL_1 Clock stretching is enabled 0x1 ADDRCFG Address Configuration 16 3 read-write ADDRCFG_0 Address match 0 (7-bit) 0 ADDRCFG_1 Address match 0 (10-bit) 0x1 ADDRCFG_2 Address match 0 (7-bit) or Address match 1 (7-bit) 0x2 ADDRCFG_3 Address match 0 (10-bit) or Address match 1 (10-bit) 0x3 ADDRCFG_4 Address match 0 (7-bit) or Address match 1 (10-bit) 0x4 ADDRCFG_5 Address match 0 (10-bit) or Address match 1 (7-bit) 0x5 ADDRCFG_6 From Address match 0 (7-bit) to Address match 1 (7-bit) 0x6 ADDRCFG_7 From Address match 0 (10-bit) to Address match 1 (10-bit) 0x7 ADRSTALL Address SCL Stall 0 1 read-write ADRSTALL_0 Clock stretching is disabled 0 ADRSTALL_1 Clock stretching is enabled 0x1 GCEN General Call Enable 8 1 read-write GCEN_0 General Call address is disabled 0 GCEN_1 General Call address is enabled 0x1 HSMEN High Speed Mode Enable 13 1 read-write HSMEN_0 Disables detection of HS-mode master code 0 HSMEN_1 Enables detection of HS-mode master code 0x1 IGNACK Ignore NACK 12 1 read-write IGNACK_0 Slave will end transfer when NACK is detected 0 IGNACK_1 Slave will not end transfer when NACK detected 0x1 RXCFG Receive Data Configuration 11 1 read-write RXCFG_0 Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). 0 RXCFG_1 Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). 0x1 RXSTALL RX SCL Stall 1 1 read-write RXSTALL_0 Clock stretching is disabled 0 RXSTALL_1 Clock stretching is enabled 0x1 SAEN SMBus Alert Enable 9 1 read-write SAEN_0 Disables match on SMBus Alert 0 SAEN_1 Enables match on SMBus Alert 0x1 TXCFG Transmit Flag Configuration 10 1 read-write TXCFG_0 Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty 0 TXCFG_1 Transmit Data Flag will assert whenever the Transmit Data register is empty 0x1 TXDSTALL TX Data SCL Stall 2 1 read-write TXDSTALL_0 Clock stretching is disabled 0 TXDSTALL_1 Clock stretching is enabled 0x1 SCFGR2 Slave Configuration Register 2 0x128 32 read-write n 0x0 0x0 CLKHOLD Clock Hold Time 0 4 read-write DATAVD Data Valid Delay 8 6 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write SCR Slave Control Register 0x110 32 read-write n 0x0 0x0 FILTDZ Filter Doze Enable 5 1 read-write FILTDZ_0 Filter remains enabled in Doze mode 0 FILTDZ_1 Filter is disabled in Doze mode 0x1 FILTEN Filter Enable 4 1 read-write FILTEN_0 Disable digital filter and output delay counter for slave mode 0 FILTEN_1 Enable digital filter and output delay counter for slave mode 0x1 RRF Reset Receive FIFO 9 1 write-only RRF_0 No effect 0 RRF_1 Receive Data Register is now empty 0x1 RST Software Reset 1 1 read-write RST_0 Slave mode logic is not reset 0 RST_1 Slave mode logic is reset 0x1 RTF Reset Transmit FIFO 8 1 write-only RTF_0 No effect 0 RTF_1 Transmit Data Register is now empty 0x1 SEN Slave Enable 0 1 read-write SEN_0 I2C Slave mode is disabled 0 SEN_1 I2C Slave mode is enabled 0x1 SDER Slave DMA Enable Register 0x11C 32 read-write n 0x0 0x0 AVDE Address Valid DMA Enable 2 1 read-write AVDE_0 DMA request is disabled 0 AVDE_1 DMA request is enabled 0x1 RDDE Receive Data DMA Enable 1 1 read-write RDDE_0 DMA request is disabled 0 RDDE_1 DMA request is enabled 0x1 TDDE Transmit Data DMA Enable 0 1 read-write TDDE_0 DMA request is disabled 0 TDDE_1 DMA request is enabled 0x1 SIER Slave Interrupt Enable Register 0x118 32 read-write n 0x0 0x0 AM0IE Address Match 0 Interrupt Enable 12 1 read-write AM0IE_0 Enabled 0 AM0IE_1 Disabled 0x1 AM1F Address Match 1 Interrupt Enable 13 1 read-write AM1F_0 Disabled 0 AM1F_1 Enabled 0x1 AVIE Address Valid Interrupt Enable 2 1 read-write AVIE_0 Disabled 0 AVIE_1 Enabled 0x1 BEIE Bit Error Interrupt Enable 10 1 read-write BEIE_0 Disabled 0 BEIE_1 Enabled 0x1 FEIE FIFO Error Interrupt Enable 11 1 read-write FEIE_0 Disabled 0 FEIE_1 Enabled 0x1 GCIE General Call Interrupt Enable 14 1 read-write GCIE_0 Disabled 0 GCIE_1 Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write RDIE_0 Disabled 0 RDIE_1 Enabled 0x1 RSIE Repeated Start Interrupt Enable 8 1 read-write RSIE_0 Disabled 0 RSIE_1 Enabled 0x1 SARIE SMBus Alert Response Interrupt Enable 15 1 read-write SARIE_0 Disabled 0 SARIE_1 Enabled 0x1 SDIE STOP Detect Interrupt Enable 9 1 read-write SDIE_0 Disabled 0 SDIE_1 Enabled 0x1 TAIE Transmit ACK Interrupt Enable 3 1 read-write TAIE_0 Disabled 0 TAIE_1 Enabled 0x1 TDIE Transmit Data Interrupt Enable 0 1 read-write TDIE_0 Disabled 0 TDIE_1 Enabled 0x1 SRDR Slave Receive Data Register 0x170 32 read-only n 0x0 0x0 DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only RXEMPTY_0 The Receive Data Register is not empty 0 RXEMPTY_1 The Receive Data Register is empty 0x1 SOF Start Of Frame 15 1 read-only SOF_0 Indicates this is not the first data word since a (repeated) START or STOP condition 0 SOF_1 Indicates this is the first data word since a (repeated) START or STOP condition 0x1 SSR Slave Status Register 0x114 32 read-write n 0x0 0x0 AM0F Address Match 0 Flag 12 1 read-only AM0F_0 Have not received an ADDR0 matching address 0 AM0F_1 Have received an ADDR0 matching address 0x1 AM1F Address Match 1 Flag 13 1 read-only AM1F_0 Have not received an ADDR1 or ADDR0/ADDR1 range matching address 0 AM1F_1 Have received an ADDR1 or ADDR0/ADDR1 range matching address 0x1 AVF Address Valid Flag 2 1 read-only AVF_0 Address Status Register is not valid 0 AVF_1 Address Status Register is valid 0x1 BBF Bus Busy Flag 25 1 read-only BBF_0 I2C Bus is idle 0 BBF_1 I2C Bus is busy 0x1 BEF Bit Error Flag 10 1 read-write oneToClear BEF_0 Slave has not detected a bit error 0 BEF_1 Slave has detected a bit error 0x1 FEF FIFO Error Flag 11 1 read-write oneToClear FEF_0 FIFO underflow or overflow was not detected 0 FEF_1 FIFO underflow or overflow was detected 0x1 GCF General Call Flag 14 1 read-only GCF_0 Slave has not detected the General Call Address or the General Call Address is disabled 0 GCF_1 Slave has detected the General Call Address 0x1 RDF Receive Data Flag 1 1 read-only RDF_0 Receive data is not ready 0 RDF_1 Receive data is ready 0x1 RSF Repeated Start Flag 8 1 read-write oneToClear RSF_0 Slave has not detected a Repeated START condition 0 RSF_1 Slave has detected a Repeated START condition 0x1 SARF SMBus Alert Response Flag 15 1 read-only SARF_0 SMBus Alert Response is disabled or not detected 0 SARF_1 SMBus Alert Response is enabled and detected 0x1 SBF Slave Busy Flag 24 1 read-only SBF_0 I2C Slave is idle 0 SBF_1 I2C Slave is busy 0x1 SDF STOP Detect Flag 9 1 read-write oneToClear SDF_0 Slave has not detected a STOP condition 0 SDF_1 Slave has detected a STOP condition 0x1 TAF Transmit ACK Flag 3 1 read-only TAF_0 Transmit ACK/NACK is not required 0 TAF_1 Transmit ACK/NACK is required 0x1 TDF Transmit Data Flag 0 1 read-only TDF_0 Transmit data not requested 0 TDF_1 Transmit data is requested 0x1 STAR Slave Transmit ACK Register 0x154 32 read-write n 0x0 0x0 TXNACK Transmit NACK 0 1 read-write TXNACK_0 Write a Transmit ACK for each received word 0 TXNACK_1 Write a Transmit NACK for each received word 0x1 STDR Slave Transmit Data Register 0x160 32 read-write n 0x0 0x0 DATA Transmit Data 0 8 write-only VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only FEATURE_2 Master only, with standard feature set 0x2 FEATURE_3 Master and slave, with standard feature set 0x3 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPI2C2 LPI2C LPI2C2 0x0 0x0 0x174 registers n LPI2C2 38 MCCR0 Master Clock Configuration Register 0 0x48 32 read-write n 0x0 0x0 CLKHI Clock High Period 8 6 read-write CLKLO Clock Low Period 0 6 read-write DATAVD Data Valid Delay 24 6 read-write SETHOLD Setup Hold Delay 16 6 read-write MCCR1 Master Clock Configuration Register 1 0x50 32 read-write n 0x0 0x0 CLKHI Clock High Period 8 6 read-write CLKLO Clock Low Period 0 6 read-write DATAVD Data Valid Delay 24 6 read-write SETHOLD Setup Hold Delay 16 6 read-write MCFGR0 Master Configuration Register 0 0x20 32 read-write n 0x0 0x0 CIRFIFO Circular FIFO Enable 8 1 read-write CIRFIFO_0 Circular FIFO is disabled 0 CIRFIFO_1 Circular FIFO is enabled 0x1 HREN Host Request Enable 0 1 read-write HREN_0 Host request input is disabled 0 HREN_1 Host request input is enabled 0x1 HRPOL Host Request Polarity 1 1 read-write HRPOL_0 Active low 0 HRPOL_1 Active high 0x1 HRSEL Host Request Select 2 1 read-write HRSEL_0 Host request input is pin HREQ 0 HRSEL_1 Host request input is input trigger 0x1 RDMO Receive Data Match Only 9 1 read-write RDMO_0 Received data is stored in the receive FIFO 0 RDMO_1 Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set 0x1 MCFGR1 Master Configuration Register 1 0x24 32 read-write n 0x0 0x0 AUTOSTOP Automatic STOP Generation 8 1 read-write AUTOSTOP_0 No effect 0 AUTOSTOP_1 STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy 0x1 IGNACK IGNACK 9 1 read-write IGNACK_0 LPI2C Master will receive ACK and NACK normally 0 IGNACK_1 LPI2C Master will treat a received NACK as if it (NACK) was an ACK 0x1 MATCFG Match Configuration 16 3 read-write MATCFG_0 Match is disabled 0 MATCFG_2 Match is enabled (1st data word equals MATCH0 OR MATCH1) 0x2 MATCFG_3 Match is enabled (any data word equals MATCH0 OR MATCH1) 0x3 MATCFG_4 Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) 0x4 MATCFG_5 Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) 0x5 MATCFG_6 Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) 0x6 MATCFG_7 Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) 0x7 PINCFG Pin Configuration 24 3 read-write PINCFG_0 2-pin open drain mode 0 PINCFG_1 2-pin output only mode (ultra-fast mode) 0x1 PINCFG_2 2-pin push-pull mode 0x2 PINCFG_3 4-pin push-pull mode 0x3 PINCFG_4 2-pin open drain mode with separate LPI2C slave 0x4 PINCFG_5 2-pin output only mode (ultra-fast mode) with separate LPI2C slave 0x5 PINCFG_6 2-pin push-pull mode with separate LPI2C slave 0x6 PINCFG_7 4-pin push-pull mode (inverted outputs) 0x7 PRESCALE Prescaler 0 3 read-write PRESCALE_0 Divide by 1 0 PRESCALE_1 Divide by 2 0x1 PRESCALE_2 Divide by 4 0x2 PRESCALE_3 Divide by 8 0x3 PRESCALE_4 Divide by 16 0x4 PRESCALE_5 Divide by 32 0x5 PRESCALE_6 Divide by 64 0x6 PRESCALE_7 Divide by 128 0x7 TIMECFG Timeout Configuration 10 1 read-write TIMECFG_0 Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout 0 TIMECFG_1 Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout 0x1 MCFGR2 Master Configuration Register 2 0x28 32 read-write n 0x0 0x0 BUSIDLE Bus Idle Timeout 0 12 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write MCFGR3 Master Configuration Register 3 0x2C 32 read-write n 0x0 0x0 PINLOW Pin Low Timeout 8 12 read-write MCR Master Control Register 0x10 32 read-write n 0x0 0x0 DBGEN Debug Enable 3 1 read-write DBGEN_0 Master is disabled in debug mode 0 DBGEN_1 Master is enabled in debug mode 0x1 DOZEN Doze mode enable 2 1 read-write DOZEN_0 Master is enabled in Doze mode 0 DOZEN_1 Master is disabled in Doze mode 0x1 MEN Master Enable 0 1 read-write MEN_0 Master logic is disabled 0 MEN_1 Master logic is enabled 0x1 RRF Reset Receive FIFO 9 1 write-only RRF_0 No effect 0 RRF_1 Receive FIFO is reset 0x1 RST Software Reset 1 1 read-write RST_0 Master logic is not reset 0 RST_1 Master logic is reset 0x1 RTF Reset Transmit FIFO 8 1 write-only RTF_0 No effect 0 RTF_1 Transmit FIFO is reset 0x1 MDER Master DMA Enable Register 0x1C 32 read-write n 0x0 0x0 RDDE Receive Data DMA Enable 1 1 read-write RDDE_0 DMA request is disabled 0 RDDE_1 DMA request is enabled 0x1 TDDE Transmit Data DMA Enable 0 1 read-write TDDE_0 DMA request is disabled 0 TDDE_1 DMA request is enabled 0x1 MDMR Master Data Match Register 0x40 32 read-write n 0x0 0x0 MATCH0 Match 0 Value 0 8 read-write MATCH1 Match 1 Value 16 8 read-write MFCR Master FIFO Control Register 0x58 32 read-write n 0x0 0x0 RXWATER Receive FIFO Watermark 16 2 read-write TXWATER Transmit FIFO Watermark 0 2 read-write MFSR Master FIFO Status Register 0x5C 32 read-only n 0x0 0x0 RXCOUNT Receive FIFO Count 16 3 read-only TXCOUNT Transmit FIFO Count 0 3 read-only MIER Master Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 ALIE Arbitration Lost Interrupt Enable 11 1 read-write ALIE_0 Disabled 0 ALIE_1 Enabled 0x1 DMIE Data Match Interrupt Enable 14 1 read-write DMIE_0 Disabled 0 DMIE_1 Enabled 0x1 EPIE End Packet Interrupt Enable 8 1 read-write EPIE_0 Disabled 0 EPIE_1 Enabled 0x1 FEIE FIFO Error Interrupt Enable 12 1 read-write FEIE_0 Enabled 0 FEIE_1 Disabled 0x1 NDIE NACK Detect Interrupt Enable 10 1 read-write NDIE_0 Disabled 0 NDIE_1 Enabled 0x1 PLTIE Pin Low Timeout Interrupt Enable 13 1 read-write PLTIE_0 Disabled 0 PLTIE_1 Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write RDIE_0 Disabled 0 RDIE_1 Enabled 0x1 SDIE STOP Detect Interrupt Enable 9 1 read-write SDIE_0 Disabled 0 SDIE_1 Enabled 0x1 TDIE Transmit Data Interrupt Enable 0 1 read-write TDIE_0 Disabled 0 TDIE_1 Enabled 0x1 MRDR Master Receive Data Register 0x70 32 read-only n 0x0 0x0 DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only RXEMPTY_0 Receive FIFO is not empty 0 RXEMPTY_1 Receive FIFO is empty 0x1 MSR Master Status Register 0x14 32 read-write n 0x0 0x0 ALF Arbitration Lost Flag 11 1 read-write oneToClear ALF_0 Master has not lost arbitration 0 ALF_1 Master has lost arbitration 0x1 BBF Bus Busy Flag 25 1 read-only BBF_0 I2C Bus is idle 0 BBF_1 I2C Bus is busy 0x1 DMF Data Match Flag 14 1 read-write oneToClear DMF_0 Have not received matching data 0 DMF_1 Have received matching data 0x1 EPF End Packet Flag 8 1 read-write oneToClear EPF_0 Master has not generated a STOP or Repeated START condition 0 EPF_1 Master has generated a STOP or Repeated START condition 0x1 FEF FIFO Error Flag 12 1 read-write oneToClear FEF_0 No error 0 FEF_1 Master sending or receiving data without a START condition 0x1 MBF Master Busy Flag 24 1 read-only MBF_0 I2C Master is idle 0 MBF_1 I2C Master is busy 0x1 NDF NACK Detect Flag 10 1 read-write oneToClear NDF_0 Unexpected NACK was not detected 0 NDF_1 Unexpected NACK was detected 0x1 PLTF Pin Low Timeout Flag 13 1 read-write oneToClear PLTF_0 Pin low timeout has not occurred or is disabled 0 PLTF_1 Pin low timeout has occurred 0x1 RDF Receive Data Flag 1 1 read-only RDF_0 Receive Data is not ready 0 RDF_1 Receive data is ready 0x1 SDF STOP Detect Flag 9 1 read-write oneToClear SDF_0 Master has not generated a STOP condition 0 SDF_1 Master has generated a STOP condition 0x1 TDF Transmit Data Flag 0 1 read-only TDF_0 Transmit data is not requested 0 TDF_1 Transmit data is requested 0x1 MTDR Master Transmit Data Register 0x60 32 read-write n 0x0 0x0 CMD Command Data 8 3 write-only CMD_0 Transmit DATA[7:0] 0 CMD_1 Receive (DATA[7:0] + 1) bytes 0x1 CMD_2 Generate STOP condition 0x2 CMD_3 Receive and discard (DATA[7:0] + 1) bytes 0x3 CMD_4 Generate (repeated) START and transmit address in DATA[7:0] 0x4 CMD_5 Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. 0x5 CMD_6 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode 0x6 CMD_7 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. 0x7 DATA Transmit Data 0 8 write-only PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 MRXFIFO Master Receive FIFO Size 8 4 read-only MTXFIFO Master Transmit FIFO Size 0 4 read-only SAMR Slave Address Match Register 0x140 32 read-write n 0x0 0x0 ADDR0 Address 0 Value 1 10 read-write ADDR1 Address 1 Value 17 10 read-write SASR Slave Address Status Register 0x150 32 read-only n 0x0 0x0 ANV Address Not Valid 14 1 read-only ANV_0 Received Address (RADDR) is valid 0 ANV_1 Received Address (RADDR) is not valid 0x1 RADDR Received Address 0 11 read-only SCFGR1 Slave Configuration Register 1 0x124 32 read-write n 0x0 0x0 ACKSTALL ACK SCL Stall 3 1 read-write ACKSTALL_0 Clock stretching is disabled 0 ACKSTALL_1 Clock stretching is enabled 0x1 ADDRCFG Address Configuration 16 3 read-write ADDRCFG_0 Address match 0 (7-bit) 0 ADDRCFG_1 Address match 0 (10-bit) 0x1 ADDRCFG_2 Address match 0 (7-bit) or Address match 1 (7-bit) 0x2 ADDRCFG_3 Address match 0 (10-bit) or Address match 1 (10-bit) 0x3 ADDRCFG_4 Address match 0 (7-bit) or Address match 1 (10-bit) 0x4 ADDRCFG_5 Address match 0 (10-bit) or Address match 1 (7-bit) 0x5 ADDRCFG_6 From Address match 0 (7-bit) to Address match 1 (7-bit) 0x6 ADDRCFG_7 From Address match 0 (10-bit) to Address match 1 (10-bit) 0x7 ADRSTALL Address SCL Stall 0 1 read-write ADRSTALL_0 Clock stretching is disabled 0 ADRSTALL_1 Clock stretching is enabled 0x1 GCEN General Call Enable 8 1 read-write GCEN_0 General Call address is disabled 0 GCEN_1 General Call address is enabled 0x1 HSMEN High Speed Mode Enable 13 1 read-write HSMEN_0 Disables detection of HS-mode master code 0 HSMEN_1 Enables detection of HS-mode master code 0x1 IGNACK Ignore NACK 12 1 read-write IGNACK_0 Slave will end transfer when NACK is detected 0 IGNACK_1 Slave will not end transfer when NACK detected 0x1 RXCFG Receive Data Configuration 11 1 read-write RXCFG_0 Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). 0 RXCFG_1 Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). 0x1 RXSTALL RX SCL Stall 1 1 read-write RXSTALL_0 Clock stretching is disabled 0 RXSTALL_1 Clock stretching is enabled 0x1 SAEN SMBus Alert Enable 9 1 read-write SAEN_0 Disables match on SMBus Alert 0 SAEN_1 Enables match on SMBus Alert 0x1 TXCFG Transmit Flag Configuration 10 1 read-write TXCFG_0 Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty 0 TXCFG_1 Transmit Data Flag will assert whenever the Transmit Data register is empty 0x1 TXDSTALL TX Data SCL Stall 2 1 read-write TXDSTALL_0 Clock stretching is disabled 0 TXDSTALL_1 Clock stretching is enabled 0x1 SCFGR2 Slave Configuration Register 2 0x128 32 read-write n 0x0 0x0 CLKHOLD Clock Hold Time 0 4 read-write DATAVD Data Valid Delay 8 6 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write SCR Slave Control Register 0x110 32 read-write n 0x0 0x0 FILTDZ Filter Doze Enable 5 1 read-write FILTDZ_0 Filter remains enabled in Doze mode 0 FILTDZ_1 Filter is disabled in Doze mode 0x1 FILTEN Filter Enable 4 1 read-write FILTEN_0 Disable digital filter and output delay counter for slave mode 0 FILTEN_1 Enable digital filter and output delay counter for slave mode 0x1 RRF Reset Receive FIFO 9 1 write-only RRF_0 No effect 0 RRF_1 Receive Data Register is now empty 0x1 RST Software Reset 1 1 read-write RST_0 Slave mode logic is not reset 0 RST_1 Slave mode logic is reset 0x1 RTF Reset Transmit FIFO 8 1 write-only RTF_0 No effect 0 RTF_1 Transmit Data Register is now empty 0x1 SEN Slave Enable 0 1 read-write SEN_0 I2C Slave mode is disabled 0 SEN_1 I2C Slave mode is enabled 0x1 SDER Slave DMA Enable Register 0x11C 32 read-write n 0x0 0x0 AVDE Address Valid DMA Enable 2 1 read-write AVDE_0 DMA request is disabled 0 AVDE_1 DMA request is enabled 0x1 RDDE Receive Data DMA Enable 1 1 read-write RDDE_0 DMA request is disabled 0 RDDE_1 DMA request is enabled 0x1 TDDE Transmit Data DMA Enable 0 1 read-write TDDE_0 DMA request is disabled 0 TDDE_1 DMA request is enabled 0x1 SIER Slave Interrupt Enable Register 0x118 32 read-write n 0x0 0x0 AM0IE Address Match 0 Interrupt Enable 12 1 read-write AM0IE_0 Enabled 0 AM0IE_1 Disabled 0x1 AM1F Address Match 1 Interrupt Enable 13 1 read-write AM1F_0 Disabled 0 AM1F_1 Enabled 0x1 AVIE Address Valid Interrupt Enable 2 1 read-write AVIE_0 Disabled 0 AVIE_1 Enabled 0x1 BEIE Bit Error Interrupt Enable 10 1 read-write BEIE_0 Disabled 0 BEIE_1 Enabled 0x1 FEIE FIFO Error Interrupt Enable 11 1 read-write FEIE_0 Disabled 0 FEIE_1 Enabled 0x1 GCIE General Call Interrupt Enable 14 1 read-write GCIE_0 Disabled 0 GCIE_1 Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write RDIE_0 Disabled 0 RDIE_1 Enabled 0x1 RSIE Repeated Start Interrupt Enable 8 1 read-write RSIE_0 Disabled 0 RSIE_1 Enabled 0x1 SARIE SMBus Alert Response Interrupt Enable 15 1 read-write SARIE_0 Disabled 0 SARIE_1 Enabled 0x1 SDIE STOP Detect Interrupt Enable 9 1 read-write SDIE_0 Disabled 0 SDIE_1 Enabled 0x1 TAIE Transmit ACK Interrupt Enable 3 1 read-write TAIE_0 Disabled 0 TAIE_1 Enabled 0x1 TDIE Transmit Data Interrupt Enable 0 1 read-write TDIE_0 Disabled 0 TDIE_1 Enabled 0x1 SRDR Slave Receive Data Register 0x170 32 read-only n 0x0 0x0 DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only RXEMPTY_0 The Receive Data Register is not empty 0 RXEMPTY_1 The Receive Data Register is empty 0x1 SOF Start Of Frame 15 1 read-only SOF_0 Indicates this is not the first data word since a (repeated) START or STOP condition 0 SOF_1 Indicates this is the first data word since a (repeated) START or STOP condition 0x1 SSR Slave Status Register 0x114 32 read-write n 0x0 0x0 AM0F Address Match 0 Flag 12 1 read-only AM0F_0 Have not received an ADDR0 matching address 0 AM0F_1 Have received an ADDR0 matching address 0x1 AM1F Address Match 1 Flag 13 1 read-only AM1F_0 Have not received an ADDR1 or ADDR0/ADDR1 range matching address 0 AM1F_1 Have received an ADDR1 or ADDR0/ADDR1 range matching address 0x1 AVF Address Valid Flag 2 1 read-only AVF_0 Address Status Register is not valid 0 AVF_1 Address Status Register is valid 0x1 BBF Bus Busy Flag 25 1 read-only BBF_0 I2C Bus is idle 0 BBF_1 I2C Bus is busy 0x1 BEF Bit Error Flag 10 1 read-write oneToClear BEF_0 Slave has not detected a bit error 0 BEF_1 Slave has detected a bit error 0x1 FEF FIFO Error Flag 11 1 read-write oneToClear FEF_0 FIFO underflow or overflow was not detected 0 FEF_1 FIFO underflow or overflow was detected 0x1 GCF General Call Flag 14 1 read-only GCF_0 Slave has not detected the General Call Address or the General Call Address is disabled 0 GCF_1 Slave has detected the General Call Address 0x1 RDF Receive Data Flag 1 1 read-only RDF_0 Receive data is not ready 0 RDF_1 Receive data is ready 0x1 RSF Repeated Start Flag 8 1 read-write oneToClear RSF_0 Slave has not detected a Repeated START condition 0 RSF_1 Slave has detected a Repeated START condition 0x1 SARF SMBus Alert Response Flag 15 1 read-only SARF_0 SMBus Alert Response is disabled or not detected 0 SARF_1 SMBus Alert Response is enabled and detected 0x1 SBF Slave Busy Flag 24 1 read-only SBF_0 I2C Slave is idle 0 SBF_1 I2C Slave is busy 0x1 SDF STOP Detect Flag 9 1 read-write oneToClear SDF_0 Slave has not detected a STOP condition 0 SDF_1 Slave has detected a STOP condition 0x1 TAF Transmit ACK Flag 3 1 read-only TAF_0 Transmit ACK/NACK is not required 0 TAF_1 Transmit ACK/NACK is required 0x1 TDF Transmit Data Flag 0 1 read-only TDF_0 Transmit data not requested 0 TDF_1 Transmit data is requested 0x1 STAR Slave Transmit ACK Register 0x154 32 read-write n 0x0 0x0 TXNACK Transmit NACK 0 1 read-write TXNACK_0 Write a Transmit ACK for each received word 0 TXNACK_1 Write a Transmit NACK for each received word 0x1 STDR Slave Transmit Data Register 0x160 32 read-write n 0x0 0x0 DATA Transmit Data 0 8 write-only VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only FEATURE_2 Master only, with standard feature set 0x2 FEATURE_3 Master and slave, with standard feature set 0x3 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPI2C3 LPI2C LPI2C3 0x0 0x0 0x174 registers n LPI2C3 61 MCCR0 Master Clock Configuration Register 0 0x48 32 read-write n 0x0 0x0 CLKHI Clock High Period 8 6 read-write CLKLO Clock Low Period 0 6 read-write DATAVD Data Valid Delay 24 6 read-write SETHOLD Setup Hold Delay 16 6 read-write MCCR1 Master Clock Configuration Register 1 0x50 32 read-write n 0x0 0x0 CLKHI Clock High Period 8 6 read-write CLKLO Clock Low Period 0 6 read-write DATAVD Data Valid Delay 24 6 read-write SETHOLD Setup Hold Delay 16 6 read-write MCFGR0 Master Configuration Register 0 0x20 32 read-write n 0x0 0x0 CIRFIFO Circular FIFO Enable 8 1 read-write CIRFIFO_0 Circular FIFO is disabled 0 CIRFIFO_1 Circular FIFO is enabled 0x1 HREN Host Request Enable 0 1 read-write HREN_0 Host request input is disabled 0 HREN_1 Host request input is enabled 0x1 HRPOL Host Request Polarity 1 1 read-write HRPOL_0 Active low 0 HRPOL_1 Active high 0x1 HRSEL Host Request Select 2 1 read-write HRSEL_0 Host request input is pin HREQ 0 HRSEL_1 Host request input is input trigger 0x1 RDMO Receive Data Match Only 9 1 read-write RDMO_0 Received data is stored in the receive FIFO 0 RDMO_1 Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set 0x1 MCFGR1 Master Configuration Register 1 0x24 32 read-write n 0x0 0x0 AUTOSTOP Automatic STOP Generation 8 1 read-write AUTOSTOP_0 No effect 0 AUTOSTOP_1 STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy 0x1 IGNACK IGNACK 9 1 read-write IGNACK_0 LPI2C Master will receive ACK and NACK normally 0 IGNACK_1 LPI2C Master will treat a received NACK as if it (NACK) was an ACK 0x1 MATCFG Match Configuration 16 3 read-write MATCFG_0 Match is disabled 0 MATCFG_2 Match is enabled (1st data word equals MATCH0 OR MATCH1) 0x2 MATCFG_3 Match is enabled (any data word equals MATCH0 OR MATCH1) 0x3 MATCFG_4 Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) 0x4 MATCFG_5 Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) 0x5 MATCFG_6 Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) 0x6 MATCFG_7 Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) 0x7 PINCFG Pin Configuration 24 3 read-write PINCFG_0 2-pin open drain mode 0 PINCFG_1 2-pin output only mode (ultra-fast mode) 0x1 PINCFG_2 2-pin push-pull mode 0x2 PINCFG_3 4-pin push-pull mode 0x3 PINCFG_4 2-pin open drain mode with separate LPI2C slave 0x4 PINCFG_5 2-pin output only mode (ultra-fast mode) with separate LPI2C slave 0x5 PINCFG_6 2-pin push-pull mode with separate LPI2C slave 0x6 PINCFG_7 4-pin push-pull mode (inverted outputs) 0x7 PRESCALE Prescaler 0 3 read-write PRESCALE_0 Divide by 1 0 PRESCALE_1 Divide by 2 0x1 PRESCALE_2 Divide by 4 0x2 PRESCALE_3 Divide by 8 0x3 PRESCALE_4 Divide by 16 0x4 PRESCALE_5 Divide by 32 0x5 PRESCALE_6 Divide by 64 0x6 PRESCALE_7 Divide by 128 0x7 TIMECFG Timeout Configuration 10 1 read-write TIMECFG_0 Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout 0 TIMECFG_1 Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout 0x1 MCFGR2 Master Configuration Register 2 0x28 32 read-write n 0x0 0x0 BUSIDLE Bus Idle Timeout 0 12 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write MCFGR3 Master Configuration Register 3 0x2C 32 read-write n 0x0 0x0 PINLOW Pin Low Timeout 8 12 read-write MCR Master Control Register 0x10 32 read-write n 0x0 0x0 DBGEN Debug Enable 3 1 read-write DBGEN_0 Master is disabled in debug mode 0 DBGEN_1 Master is enabled in debug mode 0x1 DOZEN Doze mode enable 2 1 read-write DOZEN_0 Master is enabled in Doze mode 0 DOZEN_1 Master is disabled in Doze mode 0x1 MEN Master Enable 0 1 read-write MEN_0 Master logic is disabled 0 MEN_1 Master logic is enabled 0x1 RRF Reset Receive FIFO 9 1 write-only RRF_0 No effect 0 RRF_1 Receive FIFO is reset 0x1 RST Software Reset 1 1 read-write RST_0 Master logic is not reset 0 RST_1 Master logic is reset 0x1 RTF Reset Transmit FIFO 8 1 write-only RTF_0 No effect 0 RTF_1 Transmit FIFO is reset 0x1 MDER Master DMA Enable Register 0x1C 32 read-write n 0x0 0x0 RDDE Receive Data DMA Enable 1 1 read-write RDDE_0 DMA request is disabled 0 RDDE_1 DMA request is enabled 0x1 TDDE Transmit Data DMA Enable 0 1 read-write TDDE_0 DMA request is disabled 0 TDDE_1 DMA request is enabled 0x1 MDMR Master Data Match Register 0x40 32 read-write n 0x0 0x0 MATCH0 Match 0 Value 0 8 read-write MATCH1 Match 1 Value 16 8 read-write MFCR Master FIFO Control Register 0x58 32 read-write n 0x0 0x0 RXWATER Receive FIFO Watermark 16 2 read-write TXWATER Transmit FIFO Watermark 0 2 read-write MFSR Master FIFO Status Register 0x5C 32 read-only n 0x0 0x0 RXCOUNT Receive FIFO Count 16 3 read-only TXCOUNT Transmit FIFO Count 0 3 read-only MIER Master Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 ALIE Arbitration Lost Interrupt Enable 11 1 read-write ALIE_0 Disabled 0 ALIE_1 Enabled 0x1 DMIE Data Match Interrupt Enable 14 1 read-write DMIE_0 Disabled 0 DMIE_1 Enabled 0x1 EPIE End Packet Interrupt Enable 8 1 read-write EPIE_0 Disabled 0 EPIE_1 Enabled 0x1 FEIE FIFO Error Interrupt Enable 12 1 read-write FEIE_0 Enabled 0 FEIE_1 Disabled 0x1 NDIE NACK Detect Interrupt Enable 10 1 read-write NDIE_0 Disabled 0 NDIE_1 Enabled 0x1 PLTIE Pin Low Timeout Interrupt Enable 13 1 read-write PLTIE_0 Disabled 0 PLTIE_1 Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write RDIE_0 Disabled 0 RDIE_1 Enabled 0x1 SDIE STOP Detect Interrupt Enable 9 1 read-write SDIE_0 Disabled 0 SDIE_1 Enabled 0x1 TDIE Transmit Data Interrupt Enable 0 1 read-write TDIE_0 Disabled 0 TDIE_1 Enabled 0x1 MRDR Master Receive Data Register 0x70 32 read-only n 0x0 0x0 DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only RXEMPTY_0 Receive FIFO is not empty 0 RXEMPTY_1 Receive FIFO is empty 0x1 MSR Master Status Register 0x14 32 read-write n 0x0 0x0 ALF Arbitration Lost Flag 11 1 read-write oneToClear ALF_0 Master has not lost arbitration 0 ALF_1 Master has lost arbitration 0x1 BBF Bus Busy Flag 25 1 read-only BBF_0 I2C Bus is idle 0 BBF_1 I2C Bus is busy 0x1 DMF Data Match Flag 14 1 read-write oneToClear DMF_0 Have not received matching data 0 DMF_1 Have received matching data 0x1 EPF End Packet Flag 8 1 read-write oneToClear EPF_0 Master has not generated a STOP or Repeated START condition 0 EPF_1 Master has generated a STOP or Repeated START condition 0x1 FEF FIFO Error Flag 12 1 read-write oneToClear FEF_0 No error 0 FEF_1 Master sending or receiving data without a START condition 0x1 MBF Master Busy Flag 24 1 read-only MBF_0 I2C Master is idle 0 MBF_1 I2C Master is busy 0x1 NDF NACK Detect Flag 10 1 read-write oneToClear NDF_0 Unexpected NACK was not detected 0 NDF_1 Unexpected NACK was detected 0x1 PLTF Pin Low Timeout Flag 13 1 read-write oneToClear PLTF_0 Pin low timeout has not occurred or is disabled 0 PLTF_1 Pin low timeout has occurred 0x1 RDF Receive Data Flag 1 1 read-only RDF_0 Receive Data is not ready 0 RDF_1 Receive data is ready 0x1 SDF STOP Detect Flag 9 1 read-write oneToClear SDF_0 Master has not generated a STOP condition 0 SDF_1 Master has generated a STOP condition 0x1 TDF Transmit Data Flag 0 1 read-only TDF_0 Transmit data is not requested 0 TDF_1 Transmit data is requested 0x1 MTDR Master Transmit Data Register 0x60 32 read-write n 0x0 0x0 CMD Command Data 8 3 write-only CMD_0 Transmit DATA[7:0] 0 CMD_1 Receive (DATA[7:0] + 1) bytes 0x1 CMD_2 Generate STOP condition 0x2 CMD_3 Receive and discard (DATA[7:0] + 1) bytes 0x3 CMD_4 Generate (repeated) START and transmit address in DATA[7:0] 0x4 CMD_5 Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned. 0x5 CMD_6 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode 0x6 CMD_7 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. 0x7 DATA Transmit Data 0 8 write-only PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 MRXFIFO Master Receive FIFO Size 8 4 read-only MTXFIFO Master Transmit FIFO Size 0 4 read-only SAMR Slave Address Match Register 0x140 32 read-write n 0x0 0x0 ADDR0 Address 0 Value 1 10 read-write ADDR1 Address 1 Value 17 10 read-write SASR Slave Address Status Register 0x150 32 read-only n 0x0 0x0 ANV Address Not Valid 14 1 read-only ANV_0 Received Address (RADDR) is valid 0 ANV_1 Received Address (RADDR) is not valid 0x1 RADDR Received Address 0 11 read-only SCFGR1 Slave Configuration Register 1 0x124 32 read-write n 0x0 0x0 ACKSTALL ACK SCL Stall 3 1 read-write ACKSTALL_0 Clock stretching is disabled 0 ACKSTALL_1 Clock stretching is enabled 0x1 ADDRCFG Address Configuration 16 3 read-write ADDRCFG_0 Address match 0 (7-bit) 0 ADDRCFG_1 Address match 0 (10-bit) 0x1 ADDRCFG_2 Address match 0 (7-bit) or Address match 1 (7-bit) 0x2 ADDRCFG_3 Address match 0 (10-bit) or Address match 1 (10-bit) 0x3 ADDRCFG_4 Address match 0 (7-bit) or Address match 1 (10-bit) 0x4 ADDRCFG_5 Address match 0 (10-bit) or Address match 1 (7-bit) 0x5 ADDRCFG_6 From Address match 0 (7-bit) to Address match 1 (7-bit) 0x6 ADDRCFG_7 From Address match 0 (10-bit) to Address match 1 (10-bit) 0x7 ADRSTALL Address SCL Stall 0 1 read-write ADRSTALL_0 Clock stretching is disabled 0 ADRSTALL_1 Clock stretching is enabled 0x1 GCEN General Call Enable 8 1 read-write GCEN_0 General Call address is disabled 0 GCEN_1 General Call address is enabled 0x1 HSMEN High Speed Mode Enable 13 1 read-write HSMEN_0 Disables detection of HS-mode master code 0 HSMEN_1 Enables detection of HS-mode master code 0x1 IGNACK Ignore NACK 12 1 read-write IGNACK_0 Slave will end transfer when NACK is detected 0 IGNACK_1 Slave will not end transfer when NACK detected 0x1 RXCFG Receive Data Configuration 11 1 read-write RXCFG_0 Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). 0 RXCFG_1 Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). 0x1 RXSTALL RX SCL Stall 1 1 read-write RXSTALL_0 Clock stretching is disabled 0 RXSTALL_1 Clock stretching is enabled 0x1 SAEN SMBus Alert Enable 9 1 read-write SAEN_0 Disables match on SMBus Alert 0 SAEN_1 Enables match on SMBus Alert 0x1 TXCFG Transmit Flag Configuration 10 1 read-write TXCFG_0 Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty 0 TXCFG_1 Transmit Data Flag will assert whenever the Transmit Data register is empty 0x1 TXDSTALL TX Data SCL Stall 2 1 read-write TXDSTALL_0 Clock stretching is disabled 0 TXDSTALL_1 Clock stretching is enabled 0x1 SCFGR2 Slave Configuration Register 2 0x128 32 read-write n 0x0 0x0 CLKHOLD Clock Hold Time 0 4 read-write DATAVD Data Valid Delay 8 6 read-write FILTSCL Glitch Filter SCL 16 4 read-write FILTSDA Glitch Filter SDA 24 4 read-write SCR Slave Control Register 0x110 32 read-write n 0x0 0x0 FILTDZ Filter Doze Enable 5 1 read-write FILTDZ_0 Filter remains enabled in Doze mode 0 FILTDZ_1 Filter is disabled in Doze mode 0x1 FILTEN Filter Enable 4 1 read-write FILTEN_0 Disable digital filter and output delay counter for slave mode 0 FILTEN_1 Enable digital filter and output delay counter for slave mode 0x1 RRF Reset Receive FIFO 9 1 write-only RRF_0 No effect 0 RRF_1 Receive Data Register is now empty 0x1 RST Software Reset 1 1 read-write RST_0 Slave mode logic is not reset 0 RST_1 Slave mode logic is reset 0x1 RTF Reset Transmit FIFO 8 1 write-only RTF_0 No effect 0 RTF_1 Transmit Data Register is now empty 0x1 SEN Slave Enable 0 1 read-write SEN_0 I2C Slave mode is disabled 0 SEN_1 I2C Slave mode is enabled 0x1 SDER Slave DMA Enable Register 0x11C 32 read-write n 0x0 0x0 AVDE Address Valid DMA Enable 2 1 read-write AVDE_0 DMA request is disabled 0 AVDE_1 DMA request is enabled 0x1 RDDE Receive Data DMA Enable 1 1 read-write RDDE_0 DMA request is disabled 0 RDDE_1 DMA request is enabled 0x1 TDDE Transmit Data DMA Enable 0 1 read-write TDDE_0 DMA request is disabled 0 TDDE_1 DMA request is enabled 0x1 SIER Slave Interrupt Enable Register 0x118 32 read-write n 0x0 0x0 AM0IE Address Match 0 Interrupt Enable 12 1 read-write AM0IE_0 Enabled 0 AM0IE_1 Disabled 0x1 AM1F Address Match 1 Interrupt Enable 13 1 read-write AM1F_0 Disabled 0 AM1F_1 Enabled 0x1 AVIE Address Valid Interrupt Enable 2 1 read-write AVIE_0 Disabled 0 AVIE_1 Enabled 0x1 BEIE Bit Error Interrupt Enable 10 1 read-write BEIE_0 Disabled 0 BEIE_1 Enabled 0x1 FEIE FIFO Error Interrupt Enable 11 1 read-write FEIE_0 Disabled 0 FEIE_1 Enabled 0x1 GCIE General Call Interrupt Enable 14 1 read-write GCIE_0 Disabled 0 GCIE_1 Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write RDIE_0 Disabled 0 RDIE_1 Enabled 0x1 RSIE Repeated Start Interrupt Enable 8 1 read-write RSIE_0 Disabled 0 RSIE_1 Enabled 0x1 SARIE SMBus Alert Response Interrupt Enable 15 1 read-write SARIE_0 Disabled 0 SARIE_1 Enabled 0x1 SDIE STOP Detect Interrupt Enable 9 1 read-write SDIE_0 Disabled 0 SDIE_1 Enabled 0x1 TAIE Transmit ACK Interrupt Enable 3 1 read-write TAIE_0 Disabled 0 TAIE_1 Enabled 0x1 TDIE Transmit Data Interrupt Enable 0 1 read-write TDIE_0 Disabled 0 TDIE_1 Enabled 0x1 SRDR Slave Receive Data Register 0x170 32 read-only n 0x0 0x0 DATA Receive Data 0 8 read-only RXEMPTY RX Empty 14 1 read-only RXEMPTY_0 The Receive Data Register is not empty 0 RXEMPTY_1 The Receive Data Register is empty 0x1 SOF Start Of Frame 15 1 read-only SOF_0 Indicates this is not the first data word since a (repeated) START or STOP condition 0 SOF_1 Indicates this is the first data word since a (repeated) START or STOP condition 0x1 SSR Slave Status Register 0x114 32 read-write n 0x0 0x0 AM0F Address Match 0 Flag 12 1 read-only AM0F_0 Have not received an ADDR0 matching address 0 AM0F_1 Have received an ADDR0 matching address 0x1 AM1F Address Match 1 Flag 13 1 read-only AM1F_0 Have not received an ADDR1 or ADDR0/ADDR1 range matching address 0 AM1F_1 Have received an ADDR1 or ADDR0/ADDR1 range matching address 0x1 AVF Address Valid Flag 2 1 read-only AVF_0 Address Status Register is not valid 0 AVF_1 Address Status Register is valid 0x1 BBF Bus Busy Flag 25 1 read-only BBF_0 I2C Bus is idle 0 BBF_1 I2C Bus is busy 0x1 BEF Bit Error Flag 10 1 read-write oneToClear BEF_0 Slave has not detected a bit error 0 BEF_1 Slave has detected a bit error 0x1 FEF FIFO Error Flag 11 1 read-write oneToClear FEF_0 FIFO underflow or overflow was not detected 0 FEF_1 FIFO underflow or overflow was detected 0x1 GCF General Call Flag 14 1 read-only GCF_0 Slave has not detected the General Call Address or the General Call Address is disabled 0 GCF_1 Slave has detected the General Call Address 0x1 RDF Receive Data Flag 1 1 read-only RDF_0 Receive data is not ready 0 RDF_1 Receive data is ready 0x1 RSF Repeated Start Flag 8 1 read-write oneToClear RSF_0 Slave has not detected a Repeated START condition 0 RSF_1 Slave has detected a Repeated START condition 0x1 SARF SMBus Alert Response Flag 15 1 read-only SARF_0 SMBus Alert Response is disabled or not detected 0 SARF_1 SMBus Alert Response is enabled and detected 0x1 SBF Slave Busy Flag 24 1 read-only SBF_0 I2C Slave is idle 0 SBF_1 I2C Slave is busy 0x1 SDF STOP Detect Flag 9 1 read-write oneToClear SDF_0 Slave has not detected a STOP condition 0 SDF_1 Slave has detected a STOP condition 0x1 TAF Transmit ACK Flag 3 1 read-only TAF_0 Transmit ACK/NACK is not required 0 TAF_1 Transmit ACK/NACK is required 0x1 TDF Transmit Data Flag 0 1 read-only TDF_0 Transmit data not requested 0 TDF_1 Transmit data is requested 0x1 STAR Slave Transmit ACK Register 0x154 32 read-write n 0x0 0x0 TXNACK Transmit NACK 0 1 read-write TXNACK_0 Write a Transmit ACK for each received word 0 TXNACK_1 Write a Transmit NACK for each received word 0x1 STDR Slave Transmit Data Register 0x160 32 read-write n 0x0 0x0 DATA Transmit Data 0 8 write-only VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only FEATURE_2 Master only, with standard feature set 0x2 FEATURE_3 Master and slave, with standard feature set 0x3 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPIT0 LPIT LPIT0 0x0 0x0 0x5C registers n LPIT0 27 CHANNEL[0]-CVAL Current Timer Value 0x24 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only CHANNEL[0]-TCTRL Timer Control Register 0x28 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write CHAIN_0 Channel Chaining is disabled. The channel timer runs independently. 0 CHAIN_1 Channel Chaining is enabled. The timer decrements on the previous channel's timeout. 0x1 MODE Timer Operation Mode 2 2 read-write MODE_0 32-bit Periodic Counter 0 MODE_1 Dual 16-bit Periodic Counter 0x1 MODE_2 32-bit Trigger Accumulator 0x2 MODE_3 32-bit Trigger Input Capture 0x3 TRG_SEL Trigger Select 24 4 read-write TRG_SEL_0 Timer channel 0 - 3 trigger source is selected 0 TRG_SEL_1 Timer channel 0 - 3 trigger source is selected 0x1 TRG_SEL_2 Timer channel 0 - 3 trigger source is selected 0x2 TRG_SEL_3 Timer channel 0 - 3 trigger source is selected 0x3 TRG_SRC Trigger Source 23 1 read-write TRG_SRC_0 Selects external triggers 0 TRG_SRC_1 Selects internal triggers 0x1 TROT Timer Reload On Trigger 18 1 read-write TROT_0 Timer will not reload on the selected trigger 0 TROT_1 Timer will reload on the selected trigger 0x1 TSOI Timer Stop On Interrupt 17 1 read-write TSOI_0 The channel timer does not stop after timeout 0 TSOI_1 The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. 0x1 TSOT Timer Start On Trigger 16 1 read-write TSOT_0 Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI)) 0 TSOT_1 Timer starts to decrement when a rising edge on a selected trigger is detected 0x1 T_EN Timer Enable 0 1 read-write T_EN_0 Timer Channel is disabled 0 T_EN_1 Timer Channel is enabled 0x1 CHANNEL[0]-TVAL Timer Value Register 0x20 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write TMR_VAL_0 Invalid load value in compare mode 0 TMR_VAL_1 Invalid load value in compare mode 0x1 TMR_VAL_2 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x2 TMR_VAL_3 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x3 TMR_VAL_4 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x4 TMR_VAL_5 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x5 TMR_VAL_6 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x6 TMR_VAL_7 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x7 TMR_VAL_8 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x8 TMR_VAL_9 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x9 CHANNEL[1]-CHANNEL[0]-CVAL Current Timer Value 0x54 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only CHANNEL[1]-CHANNEL[0]-TCTRL Timer Control Register 0x58 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write CHAIN_0 Channel Chaining is disabled. The channel timer runs independently. 0 CHAIN_1 Channel Chaining is enabled. The timer decrements on the previous channel's timeout. 0x1 MODE Timer Operation Mode 2 2 read-write MODE_0 32-bit Periodic Counter 0 MODE_1 Dual 16-bit Periodic Counter 0x1 MODE_2 32-bit Trigger Accumulator 0x2 MODE_3 32-bit Trigger Input Capture 0x3 TRG_SEL Trigger Select 24 4 read-write TRG_SEL_0 Timer channel 0 - 3 trigger source is selected 0 TRG_SEL_1 Timer channel 0 - 3 trigger source is selected 0x1 TRG_SEL_2 Timer channel 0 - 3 trigger source is selected 0x2 TRG_SEL_3 Timer channel 0 - 3 trigger source is selected 0x3 TRG_SRC Trigger Source 23 1 read-write TRG_SRC_0 Selects external triggers 0 TRG_SRC_1 Selects internal triggers 0x1 TROT Timer Reload On Trigger 18 1 read-write TROT_0 Timer will not reload on the selected trigger 0 TROT_1 Timer will reload on the selected trigger 0x1 TSOI Timer Stop On Interrupt 17 1 read-write TSOI_0 The channel timer does not stop after timeout 0 TSOI_1 The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. 0x1 TSOT Timer Start On Trigger 16 1 read-write TSOT_0 Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI)) 0 TSOT_1 Timer starts to decrement when a rising edge on a selected trigger is detected 0x1 T_EN Timer Enable 0 1 read-write T_EN_0 Timer Channel is disabled 0 T_EN_1 Timer Channel is enabled 0x1 CHANNEL[1]-CHANNEL[0]-TVAL Timer Value Register 0x50 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write TMR_VAL_0 Invalid load value in compare mode 0 TMR_VAL_1 Invalid load value in compare mode 0x1 TMR_VAL_2 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x2 TMR_VAL_3 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x3 TMR_VAL_4 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x4 TMR_VAL_5 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x5 TMR_VAL_6 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x6 TMR_VAL_7 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x7 TMR_VAL_8 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x8 TMR_VAL_9 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x9 CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CVAL Current Timer Value 0x94 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-TCTRL Timer Control Register 0x98 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write CHAIN_0 Channel Chaining is disabled. The channel timer runs independently. 0 CHAIN_1 Channel Chaining is enabled. The timer decrements on the previous channel's timeout. 0x1 MODE Timer Operation Mode 2 2 read-write MODE_0 32-bit Periodic Counter 0 MODE_1 Dual 16-bit Periodic Counter 0x1 MODE_2 32-bit Trigger Accumulator 0x2 MODE_3 32-bit Trigger Input Capture 0x3 TRG_SEL Trigger Select 24 4 read-write TRG_SEL_0 Timer channel 0 - 3 trigger source is selected 0 TRG_SEL_1 Timer channel 0 - 3 trigger source is selected 0x1 TRG_SEL_2 Timer channel 0 - 3 trigger source is selected 0x2 TRG_SEL_3 Timer channel 0 - 3 trigger source is selected 0x3 TRG_SRC Trigger Source 23 1 read-write TRG_SRC_0 Selects external triggers 0 TRG_SRC_1 Selects internal triggers 0x1 TROT Timer Reload On Trigger 18 1 read-write TROT_0 Timer will not reload on the selected trigger 0 TROT_1 Timer will reload on the selected trigger 0x1 TSOI Timer Stop On Interrupt 17 1 read-write TSOI_0 The channel timer does not stop after timeout 0 TSOI_1 The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. 0x1 TSOT Timer Start On Trigger 16 1 read-write TSOT_0 Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI)) 0 TSOT_1 Timer starts to decrement when a rising edge on a selected trigger is detected 0x1 T_EN Timer Enable 0 1 read-write T_EN_0 Timer Channel is disabled 0 T_EN_1 Timer Channel is enabled 0x1 CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-TVAL Timer Value Register 0x90 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write TMR_VAL_0 Invalid load value in compare mode 0 TMR_VAL_1 Invalid load value in compare mode 0x1 TMR_VAL_2 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x2 TMR_VAL_3 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x3 TMR_VAL_4 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x4 TMR_VAL_5 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x5 TMR_VAL_6 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x6 TMR_VAL_7 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x7 TMR_VAL_8 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x8 TMR_VAL_9 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x9 CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CVAL Current Timer Value 0xE4 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-TCTRL Timer Control Register 0xE8 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write CHAIN_0 Channel Chaining is disabled. The channel timer runs independently. 0 CHAIN_1 Channel Chaining is enabled. The timer decrements on the previous channel's timeout. 0x1 MODE Timer Operation Mode 2 2 read-write MODE_0 32-bit Periodic Counter 0 MODE_1 Dual 16-bit Periodic Counter 0x1 MODE_2 32-bit Trigger Accumulator 0x2 MODE_3 32-bit Trigger Input Capture 0x3 TRG_SEL Trigger Select 24 4 read-write TRG_SEL_0 Timer channel 0 - 3 trigger source is selected 0 TRG_SEL_1 Timer channel 0 - 3 trigger source is selected 0x1 TRG_SEL_2 Timer channel 0 - 3 trigger source is selected 0x2 TRG_SEL_3 Timer channel 0 - 3 trigger source is selected 0x3 TRG_SRC Trigger Source 23 1 read-write TRG_SRC_0 Selects external triggers 0 TRG_SRC_1 Selects internal triggers 0x1 TROT Timer Reload On Trigger 18 1 read-write TROT_0 Timer will not reload on the selected trigger 0 TROT_1 Timer will reload on the selected trigger 0x1 TSOI Timer Stop On Interrupt 17 1 read-write TSOI_0 The channel timer does not stop after timeout 0 TSOI_1 The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. 0x1 TSOT Timer Start On Trigger 16 1 read-write TSOT_0 Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI)) 0 TSOT_1 Timer starts to decrement when a rising edge on a selected trigger is detected 0x1 T_EN Timer Enable 0 1 read-write T_EN_0 Timer Channel is disabled 0 T_EN_1 Timer Channel is enabled 0x1 CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-TVAL Timer Value Register 0xE0 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write TMR_VAL_0 Invalid load value in compare mode 0 TMR_VAL_1 Invalid load value in compare mode 0x1 TMR_VAL_2 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x2 TMR_VAL_3 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x3 TMR_VAL_4 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x4 TMR_VAL_5 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x5 TMR_VAL_6 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x6 TMR_VAL_7 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x7 TMR_VAL_8 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x8 TMR_VAL_9 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x9 CLRTEN Clear Timer Enable Register 0x18 32 read-write n 0x0 0x0 CLR_T_EN_0 Clear Timer 0 Enable 0 1 write-only CLR_T_EN_0_0 No action 0 CLR_T_EN_0_1 Clear the Timer Enable bit (TCTRL0[T_EN]) for Timer Channel 0 0x1 CLR_T_EN_1 Clear Timer 1 Enable 1 1 write-only CLR_T_EN_1_0 No Action 0 CLR_T_EN_1_1 Clear the Timer Enable bit (TCTRL1[T_EN]) for Timer Channel 1 0x1 CLR_T_EN_2 Clear Timer 2 Enable 2 1 write-only CLR_T_EN_2_0 No Action 0 CLR_T_EN_2_1 Clear the Timer Enable bit (TCTRL2[T_EN]) for Timer Channel 2 0x1 CLR_T_EN_3 Clear Timer 3 Enable 3 1 write-only CLR_T_EN_3_0 No Action 0 CLR_T_EN_3_1 Clear the Timer Enable bit (TCTRL3[T_EN]) for Timer Channel 3 0x1 CVAL Current Timer Value 0x4 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only MCR Module Control Register 0x8 32 read-write n 0x0 0x0 DBG_EN Debug Enable Bit 3 1 read-write DBG_EN_0 Stop timer channels in Debug mode 0 DBG_EN_1 Allow timer channels to continue to run in Debug mode 0x1 DOZE_EN DOZE Mode Enable Bit 2 1 read-write DOZE_EN_0 Stop timer channels in DOZE mode 0 DOZE_EN_1 Allow timer channels to continue to run in DOZE mode 0x1 M_CEN Module Clock Enable 0 1 read-write M_CEN_0 Disable peripheral clock to timers 0 M_CEN_1 Enable peripheral clock to timers 0x1 SW_RST Software Reset Bit 1 1 read-write SW_RST_0 Timer channels and registers are not reset 0 SW_RST_1 Reset timer channels and registers 0x1 MIER Module Interrupt Enable Register 0x10 32 read-write n 0x0 0x0 TIE0 Channel 0 Timer Interrupt Enable 0 1 read-write TIE0_0 Disabled 0 TIE0_1 Enabled 0x1 TIE1 Channel 1 Timer Interrupt Enable 1 1 read-write TIE1_0 Disabled 0 TIE1_1 Enabled 0x1 TIE2 Channel 2 Timer Interrupt Enable 2 1 read-write TIE2_0 Disabled 0 TIE2_1 Enabled 0x1 TIE3 Channel 3 Timer Interrupt Enable 3 1 read-write TIE3_0 Disabled 0 TIE3_1 Enabled 0x1 MSR Module Status Register 0xC 32 read-write n 0x0 0x0 TIF0 Channel 0 Timer Interrupt Flag 0 1 read-write oneToClear TIF0_0 Timer has not timed out 0 TIF0_1 Timeout has occurred (timer has timed out) 0x1 TIF1 Channel 1 Timer Interrupt Flag 1 1 read-write oneToClear TIF1_0 Timer has not timed out 0 TIF1_1 Timeout has occurred (timer has timed out) 0x1 TIF2 Channel 2 Timer Interrupt Flag 2 1 read-write oneToClear TIF2_0 Timer has not timed out 0 TIF2_1 Timeout has occurred (timer has timed out) 0x1 TIF3 Channel 3 Timer Interrupt Flag 3 1 read-write oneToClear TIF3_0 Timer has not timed out 0 TIF3_1 Timeout has occurred (timer has timed out) 0x1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 CHANNEL Number of Timer Channels 0 8 read-only EXT_TRIG Number of External Trigger Inputs 8 8 read-only SETTEN Set Timer Enable Register 0x14 32 read-write n 0x0 0x0 SET_T_EN_0 Set Timer 0 Enable 0 1 read-write SET_T_EN_0_0 No effect 0 SET_T_EN_0_1 Enables Timer Channel 0 0x1 SET_T_EN_1 Set Timer 1 Enable 1 1 read-write SET_T_EN_1_0 No Effect 0 SET_T_EN_1_1 Enables Timer Channel 1 0x1 SET_T_EN_2 Set Timer 2 Enable 2 1 read-write SET_T_EN_2_0 No Effect 0 SET_T_EN_2_1 Enables Timer Channel 2 0x1 SET_T_EN_3 Set Timer 3 Enable 3 1 read-write SET_T_EN_3_0 No effect 0 SET_T_EN_3_1 Enables Timer Channel 3 0x1 TCTRL Timer Control Register 0x8 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write CHAIN_0 Channel Chaining is disabled. The channel timer runs independently. 0 CHAIN_1 Channel Chaining is enabled. The timer decrements on the previous channel's timeout. 0x1 MODE Timer Operation Mode 2 2 read-write MODE_0 32-bit Periodic Counter 0 MODE_1 Dual 16-bit Periodic Counter 0x1 MODE_2 32-bit Trigger Accumulator 0x2 MODE_3 32-bit Trigger Input Capture 0x3 TRG_SEL Trigger Select 24 4 read-write TRG_SEL_0 Timer channel 0 - 3 trigger source is selected 0 TRG_SEL_1 Timer channel 0 - 3 trigger source is selected 0x1 TRG_SEL_2 Timer channel 0 - 3 trigger source is selected 0x2 TRG_SEL_3 Timer channel 0 - 3 trigger source is selected 0x3 TRG_SRC Trigger Source 23 1 read-write TRG_SRC_0 Selects external triggers 0 TRG_SRC_1 Selects internal triggers 0x1 TROT Timer Reload On Trigger 18 1 read-write TROT_0 Timer will not reload on the selected trigger 0 TROT_1 Timer will reload on the selected trigger 0x1 TSOI Timer Stop On Interrupt 17 1 read-write TSOI_0 The channel timer does not stop after timeout 0 TSOI_1 The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. 0x1 TSOT Timer Start On Trigger 16 1 read-write TSOT_0 Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI)) 0 TSOT_1 Timer starts to decrement when a rising edge on a selected trigger is detected 0x1 T_EN Timer Enable 0 1 read-write T_EN_0 Timer Channel is disabled 0 T_EN_1 Timer Channel is enabled 0x1 TVAL Timer Value Register 0x0 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write TMR_VAL_0 Invalid load value in compare mode 0 TMR_VAL_1 Invalid load value in compare mode 0x1 TMR_VAL_2 In compare mode: the value to be loaded in capture mode, the value of the timer 0x2 TMR_VAL_3 In compare mode: the value to be loaded in capture mode, the value of the timer 0x3 TMR_VAL_4 In compare mode: the value to be loaded in capture mode, the value of the timer 0x4 TMR_VAL_5 In compare mode: the value to be loaded in capture mode, the value of the timer 0x5 TMR_VAL_6 In compare mode: the value to be loaded in capture mode, the value of the timer 0x6 TMR_VAL_7 In compare mode: the value to be loaded in capture mode, the value of the timer 0x7 TMR_VAL_8 In compare mode: the value to be loaded in capture mode, the value of the timer 0x8 TMR_VAL_9 In compare mode: the value to be loaded in capture mode, the value of the timer 0x9 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Number 0 16 read-only MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPIT1 LPIT LPIT1 0x0 0x0 0x5C registers n LPIT1 58 CHANNEL[0]-CVAL Current Timer Value 0x24 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only CHANNEL[0]-TCTRL Timer Control Register 0x28 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write CHAIN_0 Channel Chaining is disabled. The channel timer runs independently. 0 CHAIN_1 Channel Chaining is enabled. The timer decrements on the previous channel's timeout. 0x1 MODE Timer Operation Mode 2 2 read-write MODE_0 32-bit Periodic Counter 0 MODE_1 Dual 16-bit Periodic Counter 0x1 MODE_2 32-bit Trigger Accumulator 0x2 MODE_3 32-bit Trigger Input Capture 0x3 TRG_SEL Trigger Select 24 4 read-write TRG_SEL_0 Timer channel 0 - 3 trigger source is selected 0 TRG_SEL_1 Timer channel 0 - 3 trigger source is selected 0x1 TRG_SEL_2 Timer channel 0 - 3 trigger source is selected 0x2 TRG_SEL_3 Timer channel 0 - 3 trigger source is selected 0x3 TRG_SRC Trigger Source 23 1 read-write TRG_SRC_0 Selects external triggers 0 TRG_SRC_1 Selects internal triggers 0x1 TROT Timer Reload On Trigger 18 1 read-write TROT_0 Timer will not reload on the selected trigger 0 TROT_1 Timer will reload on the selected trigger 0x1 TSOI Timer Stop On Interrupt 17 1 read-write TSOI_0 The channel timer does not stop after timeout 0 TSOI_1 The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. 0x1 TSOT Timer Start On Trigger 16 1 read-write TSOT_0 Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI)) 0 TSOT_1 Timer starts to decrement when a rising edge on a selected trigger is detected 0x1 T_EN Timer Enable 0 1 read-write T_EN_0 Timer Channel is disabled 0 T_EN_1 Timer Channel is enabled 0x1 CHANNEL[0]-TVAL Timer Value Register 0x20 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write TMR_VAL_0 Invalid load value in compare mode 0 TMR_VAL_1 Invalid load value in compare mode 0x1 TMR_VAL_2 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x2 TMR_VAL_3 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x3 TMR_VAL_4 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x4 TMR_VAL_5 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x5 TMR_VAL_6 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x6 TMR_VAL_7 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x7 TMR_VAL_8 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x8 TMR_VAL_9 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x9 CHANNEL[1]-CHANNEL[0]-CVAL Current Timer Value 0x54 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only CHANNEL[1]-CHANNEL[0]-TCTRL Timer Control Register 0x58 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write CHAIN_0 Channel Chaining is disabled. The channel timer runs independently. 0 CHAIN_1 Channel Chaining is enabled. The timer decrements on the previous channel's timeout. 0x1 MODE Timer Operation Mode 2 2 read-write MODE_0 32-bit Periodic Counter 0 MODE_1 Dual 16-bit Periodic Counter 0x1 MODE_2 32-bit Trigger Accumulator 0x2 MODE_3 32-bit Trigger Input Capture 0x3 TRG_SEL Trigger Select 24 4 read-write TRG_SEL_0 Timer channel 0 - 3 trigger source is selected 0 TRG_SEL_1 Timer channel 0 - 3 trigger source is selected 0x1 TRG_SEL_2 Timer channel 0 - 3 trigger source is selected 0x2 TRG_SEL_3 Timer channel 0 - 3 trigger source is selected 0x3 TRG_SRC Trigger Source 23 1 read-write TRG_SRC_0 Selects external triggers 0 TRG_SRC_1 Selects internal triggers 0x1 TROT Timer Reload On Trigger 18 1 read-write TROT_0 Timer will not reload on the selected trigger 0 TROT_1 Timer will reload on the selected trigger 0x1 TSOI Timer Stop On Interrupt 17 1 read-write TSOI_0 The channel timer does not stop after timeout 0 TSOI_1 The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. 0x1 TSOT Timer Start On Trigger 16 1 read-write TSOT_0 Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI)) 0 TSOT_1 Timer starts to decrement when a rising edge on a selected trigger is detected 0x1 T_EN Timer Enable 0 1 read-write T_EN_0 Timer Channel is disabled 0 T_EN_1 Timer Channel is enabled 0x1 CHANNEL[1]-CHANNEL[0]-TVAL Timer Value Register 0x50 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write TMR_VAL_0 Invalid load value in compare mode 0 TMR_VAL_1 Invalid load value in compare mode 0x1 TMR_VAL_2 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x2 TMR_VAL_3 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x3 TMR_VAL_4 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x4 TMR_VAL_5 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x5 TMR_VAL_6 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x6 TMR_VAL_7 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x7 TMR_VAL_8 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x8 TMR_VAL_9 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x9 CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CVAL Current Timer Value 0x94 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-TCTRL Timer Control Register 0x98 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write CHAIN_0 Channel Chaining is disabled. The channel timer runs independently. 0 CHAIN_1 Channel Chaining is enabled. The timer decrements on the previous channel's timeout. 0x1 MODE Timer Operation Mode 2 2 read-write MODE_0 32-bit Periodic Counter 0 MODE_1 Dual 16-bit Periodic Counter 0x1 MODE_2 32-bit Trigger Accumulator 0x2 MODE_3 32-bit Trigger Input Capture 0x3 TRG_SEL Trigger Select 24 4 read-write TRG_SEL_0 Timer channel 0 - 3 trigger source is selected 0 TRG_SEL_1 Timer channel 0 - 3 trigger source is selected 0x1 TRG_SEL_2 Timer channel 0 - 3 trigger source is selected 0x2 TRG_SEL_3 Timer channel 0 - 3 trigger source is selected 0x3 TRG_SRC Trigger Source 23 1 read-write TRG_SRC_0 Selects external triggers 0 TRG_SRC_1 Selects internal triggers 0x1 TROT Timer Reload On Trigger 18 1 read-write TROT_0 Timer will not reload on the selected trigger 0 TROT_1 Timer will reload on the selected trigger 0x1 TSOI Timer Stop On Interrupt 17 1 read-write TSOI_0 The channel timer does not stop after timeout 0 TSOI_1 The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. 0x1 TSOT Timer Start On Trigger 16 1 read-write TSOT_0 Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI)) 0 TSOT_1 Timer starts to decrement when a rising edge on a selected trigger is detected 0x1 T_EN Timer Enable 0 1 read-write T_EN_0 Timer Channel is disabled 0 T_EN_1 Timer Channel is enabled 0x1 CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-TVAL Timer Value Register 0x90 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write TMR_VAL_0 Invalid load value in compare mode 0 TMR_VAL_1 Invalid load value in compare mode 0x1 TMR_VAL_2 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x2 TMR_VAL_3 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x3 TMR_VAL_4 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x4 TMR_VAL_5 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x5 TMR_VAL_6 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x6 TMR_VAL_7 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x7 TMR_VAL_8 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x8 TMR_VAL_9 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x9 CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CVAL Current Timer Value 0xE4 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-TCTRL Timer Control Register 0xE8 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write CHAIN_0 Channel Chaining is disabled. The channel timer runs independently. 0 CHAIN_1 Channel Chaining is enabled. The timer decrements on the previous channel's timeout. 0x1 MODE Timer Operation Mode 2 2 read-write MODE_0 32-bit Periodic Counter 0 MODE_1 Dual 16-bit Periodic Counter 0x1 MODE_2 32-bit Trigger Accumulator 0x2 MODE_3 32-bit Trigger Input Capture 0x3 TRG_SEL Trigger Select 24 4 read-write TRG_SEL_0 Timer channel 0 - 3 trigger source is selected 0 TRG_SEL_1 Timer channel 0 - 3 trigger source is selected 0x1 TRG_SEL_2 Timer channel 0 - 3 trigger source is selected 0x2 TRG_SEL_3 Timer channel 0 - 3 trigger source is selected 0x3 TRG_SRC Trigger Source 23 1 read-write TRG_SRC_0 Selects external triggers 0 TRG_SRC_1 Selects internal triggers 0x1 TROT Timer Reload On Trigger 18 1 read-write TROT_0 Timer will not reload on the selected trigger 0 TROT_1 Timer will reload on the selected trigger 0x1 TSOI Timer Stop On Interrupt 17 1 read-write TSOI_0 The channel timer does not stop after timeout 0 TSOI_1 The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. 0x1 TSOT Timer Start On Trigger 16 1 read-write TSOT_0 Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI)) 0 TSOT_1 Timer starts to decrement when a rising edge on a selected trigger is detected 0x1 T_EN Timer Enable 0 1 read-write T_EN_0 Timer Channel is disabled 0 T_EN_1 Timer Channel is enabled 0x1 CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-TVAL Timer Value Register 0xE0 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write TMR_VAL_0 Invalid load value in compare mode 0 TMR_VAL_1 Invalid load value in compare mode 0x1 TMR_VAL_2 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x2 TMR_VAL_3 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x3 TMR_VAL_4 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x4 TMR_VAL_5 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x5 TMR_VAL_6 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x6 TMR_VAL_7 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x7 TMR_VAL_8 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x8 TMR_VAL_9 In compare mode: the value to be loaded; in capture mode, the value of the timer 0x9 CLRTEN Clear Timer Enable Register 0x18 32 read-write n 0x0 0x0 CLR_T_EN_0 Clear Timer 0 Enable 0 1 write-only CLR_T_EN_0_0 No action 0 CLR_T_EN_0_1 Clear the Timer Enable bit (TCTRL0[T_EN]) for Timer Channel 0 0x1 CLR_T_EN_1 Clear Timer 1 Enable 1 1 write-only CLR_T_EN_1_0 No Action 0 CLR_T_EN_1_1 Clear the Timer Enable bit (TCTRL1[T_EN]) for Timer Channel 1 0x1 CLR_T_EN_2 Clear Timer 2 Enable 2 1 write-only CLR_T_EN_2_0 No Action 0 CLR_T_EN_2_1 Clear the Timer Enable bit (TCTRL2[T_EN]) for Timer Channel 2 0x1 CLR_T_EN_3 Clear Timer 3 Enable 3 1 write-only CLR_T_EN_3_0 No Action 0 CLR_T_EN_3_1 Clear the Timer Enable bit (TCTRL3[T_EN]) for Timer Channel 3 0x1 CVAL Current Timer Value 0x4 32 read-only n 0x0 0x0 TMR_CUR_VAL Current Timer Value 0 32 read-only MCR Module Control Register 0x8 32 read-write n 0x0 0x0 DBG_EN Debug Enable Bit 3 1 read-write DBG_EN_0 Stop timer channels in Debug mode 0 DBG_EN_1 Allow timer channels to continue to run in Debug mode 0x1 DOZE_EN DOZE Mode Enable Bit 2 1 read-write DOZE_EN_0 Stop timer channels in DOZE mode 0 DOZE_EN_1 Allow timer channels to continue to run in DOZE mode 0x1 M_CEN Module Clock Enable 0 1 read-write M_CEN_0 Disable peripheral clock to timers 0 M_CEN_1 Enable peripheral clock to timers 0x1 SW_RST Software Reset Bit 1 1 read-write SW_RST_0 Timer channels and registers are not reset 0 SW_RST_1 Reset timer channels and registers 0x1 MIER Module Interrupt Enable Register 0x10 32 read-write n 0x0 0x0 TIE0 Channel 0 Timer Interrupt Enable 0 1 read-write TIE0_0 Disabled 0 TIE0_1 Enabled 0x1 TIE1 Channel 1 Timer Interrupt Enable 1 1 read-write TIE1_0 Disabled 0 TIE1_1 Enabled 0x1 TIE2 Channel 2 Timer Interrupt Enable 2 1 read-write TIE2_0 Disabled 0 TIE2_1 Enabled 0x1 TIE3 Channel 3 Timer Interrupt Enable 3 1 read-write TIE3_0 Disabled 0 TIE3_1 Enabled 0x1 MSR Module Status Register 0xC 32 read-write n 0x0 0x0 TIF0 Channel 0 Timer Interrupt Flag 0 1 read-write oneToClear TIF0_0 Timer has not timed out 0 TIF0_1 Timeout has occurred (timer has timed out) 0x1 TIF1 Channel 1 Timer Interrupt Flag 1 1 read-write oneToClear TIF1_0 Timer has not timed out 0 TIF1_1 Timeout has occurred (timer has timed out) 0x1 TIF2 Channel 2 Timer Interrupt Flag 2 1 read-write oneToClear TIF2_0 Timer has not timed out 0 TIF2_1 Timeout has occurred (timer has timed out) 0x1 TIF3 Channel 3 Timer Interrupt Flag 3 1 read-write oneToClear TIF3_0 Timer has not timed out 0 TIF3_1 Timeout has occurred (timer has timed out) 0x1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 CHANNEL Number of Timer Channels 0 8 read-only EXT_TRIG Number of External Trigger Inputs 8 8 read-only SETTEN Set Timer Enable Register 0x14 32 read-write n 0x0 0x0 SET_T_EN_0 Set Timer 0 Enable 0 1 read-write SET_T_EN_0_0 No effect 0 SET_T_EN_0_1 Enables Timer Channel 0 0x1 SET_T_EN_1 Set Timer 1 Enable 1 1 read-write SET_T_EN_1_0 No Effect 0 SET_T_EN_1_1 Enables Timer Channel 1 0x1 SET_T_EN_2 Set Timer 2 Enable 2 1 read-write SET_T_EN_2_0 No Effect 0 SET_T_EN_2_1 Enables Timer Channel 2 0x1 SET_T_EN_3 Set Timer 3 Enable 3 1 read-write SET_T_EN_3_0 No effect 0 SET_T_EN_3_1 Enables Timer Channel 3 0x1 TCTRL Timer Control Register 0x8 32 read-write n 0x0 0x0 CHAIN Chain Channel 1 1 read-write CHAIN_0 Channel Chaining is disabled. The channel timer runs independently. 0 CHAIN_1 Channel Chaining is enabled. The timer decrements on the previous channel's timeout. 0x1 MODE Timer Operation Mode 2 2 read-write MODE_0 32-bit Periodic Counter 0 MODE_1 Dual 16-bit Periodic Counter 0x1 MODE_2 32-bit Trigger Accumulator 0x2 MODE_3 32-bit Trigger Input Capture 0x3 TRG_SEL Trigger Select 24 4 read-write TRG_SEL_0 Timer channel 0 - 3 trigger source is selected 0 TRG_SEL_1 Timer channel 0 - 3 trigger source is selected 0x1 TRG_SEL_2 Timer channel 0 - 3 trigger source is selected 0x2 TRG_SEL_3 Timer channel 0 - 3 trigger source is selected 0x3 TRG_SRC Trigger Source 23 1 read-write TRG_SRC_0 Selects external triggers 0 TRG_SRC_1 Selects internal triggers 0x1 TROT Timer Reload On Trigger 18 1 read-write TROT_0 Timer will not reload on the selected trigger 0 TROT_1 Timer will reload on the selected trigger 0x1 TSOI Timer Stop On Interrupt 17 1 read-write TSOI_0 The channel timer does not stop after timeout 0 TSOI_1 The channel timer will stop after a timeout, and the channel timer will restart based on Timer Start On Trigger bit (TSOT). When TSOT = 0, the channel timer will restart after a rising edge on the Timer Enable bit (T_EN) is detected (which means that the timer channel is disabled and then enabled). When TSOT = 1, the channel timer will restart after a rising edge on the selected trigger is detected. 0x1 TSOT Timer Start On Trigger 16 1 read-write TSOT_0 Timer starts to decrement immediately based on the restart condition (controlled by the Timer Stop On Interrupt bit (TSOI)) 0 TSOT_1 Timer starts to decrement when a rising edge on a selected trigger is detected 0x1 T_EN Timer Enable 0 1 read-write T_EN_0 Timer Channel is disabled 0 T_EN_1 Timer Channel is enabled 0x1 TVAL Timer Value Register 0x0 32 read-write n 0x0 0x0 TMR_VAL Timer Value 0 32 read-write TMR_VAL_0 Invalid load value in compare mode 0 TMR_VAL_1 Invalid load value in compare mode 0x1 TMR_VAL_2 In compare mode: the value to be loaded in capture mode, the value of the timer 0x2 TMR_VAL_3 In compare mode: the value to be loaded in capture mode, the value of the timer 0x3 TMR_VAL_4 In compare mode: the value to be loaded in capture mode, the value of the timer 0x4 TMR_VAL_5 In compare mode: the value to be loaded in capture mode, the value of the timer 0x5 TMR_VAL_6 In compare mode: the value to be loaded in capture mode, the value of the timer 0x6 TMR_VAL_7 In compare mode: the value to be loaded in capture mode, the value of the timer 0x7 TMR_VAL_8 In compare mode: the value to be loaded in capture mode, the value of the timer 0x8 TMR_VAL_9 In compare mode: the value to be loaded in capture mode, the value of the timer 0x9 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Number 0 16 read-only MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPSPI0 LPSPI LPSPI0 0x0 0x0 0x78 registers n LPSPI0 41 CCR Clock Configuration Register 0x40 32 read-write n 0x0 0x0 DBT Delay Between Transfers 8 8 read-write PCSSCK PCS-to-SCK Delay 16 8 read-write SCKDIV SCK Divider 0 8 read-write SCKPCS SCK-to-PCS Delay 24 8 read-write CFGR0 Configuration Register 0 0x20 32 read-write n 0x0 0x0 CIRFIFO Circular FIFO Enable 8 1 read-write CIRFIFO_0 Circular FIFO is disabled 0 CIRFIFO_1 Circular FIFO is enabled 0x1 HREN Host Request Enable 0 1 read-write HREN_0 Host request is disabled 0 HREN_1 Host request is enabled 0x1 HRPOL Host Request Polarity 1 1 read-write HRPOL_0 Active low 0 HRPOL_1 Active high 0x1 HRSEL Host Request Select 2 1 read-write HRSEL_0 Host request input is the LPSPI_HREQ pin 0 HRSEL_1 Host request input is the input trigger 0x1 RDMO Receive Data Match Only 9 1 read-write RDMO_0 Received data is stored in the receive FIFO as in normal operations 0 RDMO_1 Received data is discarded unless the Data Match Flag (DMF) is set 0x1 CFGR1 Configuration Register 1 0x24 32 read-write n 0x0 0x0 AUTOPCS Automatic PCS 2 1 read-write AUTOPCS_0 Automatic PCS generation is disabled 0 AUTOPCS_1 Automatic PCS generation is enabled 0x1 MASTER Master Mode 0 1 read-write MASTER_0 Slave mode 0 MASTER_1 Master mode 0x1 MATCFG Match Configuration 16 3 read-write MATCFG_0 Match is disabled 0 MATCFG_2 010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) 0x2 MATCFG_3 011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) 0x3 MATCFG_4 100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] 0x4 MATCFG_5 101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] 0x5 MATCFG_6 110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] 0x6 MATCFG_7 111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] 0x7 NOSTALL No Stall 3 1 read-write NOSTALL_0 Transfers will stall when the transmit FIFO is empty or the receive FIFO is full 0 NOSTALL_1 Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur 0x1 OUTCFG Output Config 26 1 read-write OUTCFG_0 Output data retains last value when chip select is negated 0 OUTCFG_1 Output data is tristated when chip select is negated 0x1 PCSCFG Peripheral Chip Select Configuration 27 1 read-write PCSCFG_0 PCS[3:2] are enabled 0 PCSCFG_1 PCS[3:2] are disabled 0x1 PCSPOL Peripheral Chip Select Polarity 8 4 read-write PCSPOL_0 The Peripheral Chip Select pin PCSx is active low 0 PCSPOL_1 The Peripheral Chip Select pin PCSx is active high 0x1 PINCFG Pin Configuration 24 2 read-write PINCFG_0 SIN is used for input data and SOUT is used for output data 0 PINCFG_1 SIN is used for both input and output data 0x1 PINCFG_2 SOUT is used for both input and output data 0x2 PINCFG_3 SOUT is used for input data and SIN is used for output data 0x3 SAMPLE Sample Point 1 1 read-write SAMPLE_0 Input data is sampled on SCK edge 0 SAMPLE_1 Input data is sampled on delayed SCK edge 0x1 CR Control Register 0x10 32 read-write n 0x0 0x0 DBGEN Debug Enable 3 1 read-write DBGEN_0 Module is disabled in debug mode 0 DBGEN_1 Module is enabled in debug mode 0x1 DOZEN Doze mode enable 2 1 read-write DOZEN_0 Module is enabled in Doze mode 0 DOZEN_1 Module is disabled in Doze mode 0x1 MEN Module Enable 0 1 read-write MEN_0 Module is disabled 0 MEN_1 Module is enabled 0x1 RRF Reset Receive FIFO 9 1 write-only RRF_0 No effect 0 RRF_1 Receive FIFO is reset 0x1 RST Software Reset 1 1 read-write RST_0 Master logic is not reset 0 RST_1 Master logic is reset 0x1 RTF Reset Transmit FIFO 8 1 write-only RTF_0 No effect 0 RTF_1 Transmit FIFO is reset 0x1 DER DMA Enable Register 0x1C 32 read-write n 0x0 0x0 RDDE Receive Data DMA Enable 1 1 read-write RDDE_0 DMA request is disabled 0 RDDE_1 DMA request is enabled 0x1 TDDE Transmit Data DMA Enable 0 1 read-write TDDE_0 DMA request is disabled 0 TDDE_1 DMA request is enabled 0x1 DMR0 Data Match Register 0 0x30 32 read-write n 0x0 0x0 MATCH0 Match 0 Value 0 32 read-write DMR1 Data Match Register 1 0x34 32 read-write n 0x0 0x0 MATCH1 Match 1 Value 0 32 read-write FCR FIFO Control Register 0x58 32 read-write n 0x0 0x0 RXWATER Receive FIFO Watermark 16 2 read-write TXWATER Transmit FIFO Watermark 0 2 read-write FSR FIFO Status Register 0x5C 32 read-only n 0x0 0x0 RXCOUNT Receive FIFO Count 16 3 read-only TXCOUNT Transmit FIFO Count 0 3 read-only IER Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 DMIE Data Match Interrupt Enable 13 1 read-write DMIE_0 Disabled 0 DMIE_1 Enabled 0x1 FCIE Frame Complete Interrupt Enable 9 1 read-write FCIE_0 Disabled 0 FCIE_1 Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write RDIE_0 Disabled 0 RDIE_1 Enabled 0x1 REIE Receive Error Interrupt Enable 12 1 read-write REIE_0 Disabled 0 REIE_1 Enabled 0x1 TCIE Transfer Complete Interrupt Enable 10 1 read-write TCIE_0 Disabled 0 TCIE_1 Enabled 0x1 TDIE Transmit Data Interrupt Enable 0 1 read-write TDIE_0 Disabled 0 TDIE_1 Enabled 0x1 TEIE Transmit Error Interrupt Enable 11 1 read-write TEIE_0 Disabled 0 TEIE_1 Enabled 0x1 WCIE Word Complete Interrupt Enable 8 1 read-write WCIE_0 Disabled 0 WCIE_1 Enabled 0x1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 RXFIFO Receive FIFO Size 8 8 read-only TXFIFO Transmit FIFO Size 0 8 read-only RDR Receive Data Register 0x74 32 read-only n 0x0 0x0 DATA Receive Data 0 32 read-only RSR Receive Status Register 0x70 32 read-only n 0x0 0x0 RXEMPTY RX FIFO Empty 1 1 read-only RXEMPTY_0 RX FIFO is not empty 0 RXEMPTY_1 RX FIFO is empty 0x1 SOF Start Of Frame 0 1 read-only SOF_0 Subsequent data word received after LPSPI_PCS assertion 0 SOF_1 First data word received after LPSPI_PCS assertion 0x1 SR Status Register 0x14 32 read-write n 0x0 0x0 DMF Data Match Flag 13 1 read-write oneToClear DMF_0 Have not received matching data 0 DMF_1 Have received matching data 0x1 FCF Frame Complete Flag 9 1 read-write oneToClear FCF_0 Frame transfer has not completed 0 FCF_1 Frame transfer has completed 0x1 MBF Module Busy Flag 24 1 read-only MBF_0 LPSPI is idle 0 MBF_1 LPSPI is busy 0x1 RDF Receive Data Flag 1 1 read-only RDF_0 Receive Data is not ready 0 RDF_1 Receive data is ready 0x1 REF Receive Error Flag 12 1 read-write oneToClear REF_0 Receive FIFO has not overflowed 0 REF_1 Receive FIFO has overflowed 0x1 TCF Transfer Complete Flag 10 1 read-write oneToClear TCF_0 All transfers have not completed 0 TCF_1 All transfers have completed 0x1 TDF Transmit Data Flag 0 1 read-only TDF_0 Transmit data not requested 0 TDF_1 Transmit data is requested 0x1 TEF Transmit Error Flag 11 1 read-write oneToClear TEF_0 Transmit FIFO underrun has not occurred 0 TEF_1 Transmit FIFO underrun has occurred 0x1 WCF Word Complete Flag 8 1 read-write oneToClear WCF_0 Transfer of a received word has not yet completed 0 WCF_1 Transfer of a received word has completed 0x1 TCR Transmit Command Register 0x60 32 read-write n 0x0 0x0 BYSW Byte Swap 22 1 read-write BYSW_0 Byte swap is disabled 0 BYSW_1 Byte swap is enabled 0x1 CONT Continuous Transfer 21 1 read-write CONT_0 Continuous transfer is disabled 0 CONT_1 Continuous transfer is enabled 0x1 CONTC Continuing Command 20 1 read-write CONTC_0 Command word for start of new transfer 0 CONTC_1 Command word for continuing transfer 0x1 CPHA Clock Phase 30 1 read-write CPHA_0 Data is captured on the leading edge of SCK and changed on the following edge of SCK 0 CPHA_1 Data is changed on the leading edge of SCK and captured on the following edge of SCK 0x1 CPOL Clock Polarity 31 1 read-write CPOL_0 The inactive state value of SCK is low 0 CPOL_1 The inactive state value of SCK is high 0x1 FRAMESZ Frame Size 0 12 read-write LSBF LSB First 23 1 read-write LSBF_0 Data is transferred MSB first 0 LSBF_1 Data is transferred LSB first 0x1 PCS Peripheral Chip Select 24 2 read-write PCS_0 Transfer using LPSPI_PCS[0] 0 PCS_1 Transfer using LPSPI_PCS[1] 0x1 PCS_2 Transfer using LPSPI_PCS[2] 0x2 PCS_3 Transfer using LPSPI_PCS[3] 0x3 PRESCALE Prescaler Value 27 3 read-write PRESCALE_0 Divide by 1 0 PRESCALE_1 Divide by 2 0x1 PRESCALE_2 Divide by 4 0x2 PRESCALE_3 Divide by 8 0x3 PRESCALE_4 Divide by 16 0x4 PRESCALE_5 Divide by 32 0x5 PRESCALE_6 Divide by 64 0x6 PRESCALE_7 Divide by 128 0x7 RXMSK Receive Data Mask 19 1 read-write RXMSK_0 Normal transfer 0 RXMSK_1 Receive data is masked 0x1 TXMSK Transmit Data Mask 18 1 read-write TXMSK_0 Normal transfer 0 TXMSK_1 Mask transmit data 0x1 WIDTH Transfer Width 16 2 read-write WIDTH_0 1 bit transfer 0 WIDTH_1 2 bit transfer 0x1 WIDTH_2 4 bit transfer 0x2 TDR Transmit Data Register 0x64 32 write-only n 0x0 0x0 DATA Transmit Data 0 32 write-only VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Module Identification Number 0 16 read-only FEATURE_4 Standard feature set supporting a 32-bit shift register. 0x4 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPSPI1 LPSPI LPSPI1 0x0 0x0 0x78 registers n LPSPI1 42 CCR Clock Configuration Register 0x40 32 read-write n 0x0 0x0 DBT Delay Between Transfers 8 8 read-write PCSSCK PCS-to-SCK Delay 16 8 read-write SCKDIV SCK Divider 0 8 read-write SCKPCS SCK-to-PCS Delay 24 8 read-write CFGR0 Configuration Register 0 0x20 32 read-write n 0x0 0x0 CIRFIFO Circular FIFO Enable 8 1 read-write CIRFIFO_0 Circular FIFO is disabled 0 CIRFIFO_1 Circular FIFO is enabled 0x1 HREN Host Request Enable 0 1 read-write HREN_0 Host request is disabled 0 HREN_1 Host request is enabled 0x1 HRPOL Host Request Polarity 1 1 read-write HRPOL_0 Active low 0 HRPOL_1 Active high 0x1 HRSEL Host Request Select 2 1 read-write HRSEL_0 Host request input is the LPSPI_HREQ pin 0 HRSEL_1 Host request input is the input trigger 0x1 RDMO Receive Data Match Only 9 1 read-write RDMO_0 Received data is stored in the receive FIFO as in normal operations 0 RDMO_1 Received data is discarded unless the Data Match Flag (DMF) is set 0x1 CFGR1 Configuration Register 1 0x24 32 read-write n 0x0 0x0 AUTOPCS Automatic PCS 2 1 read-write AUTOPCS_0 Automatic PCS generation is disabled 0 AUTOPCS_1 Automatic PCS generation is enabled 0x1 MASTER Master Mode 0 1 read-write MASTER_0 Slave mode 0 MASTER_1 Master mode 0x1 MATCFG Match Configuration 16 3 read-write MATCFG_0 Match is disabled 0 MATCFG_2 010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) 0x2 MATCFG_3 011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) 0x3 MATCFG_4 100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] 0x4 MATCFG_5 101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] 0x5 MATCFG_6 110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] 0x6 MATCFG_7 111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] 0x7 NOSTALL No Stall 3 1 read-write NOSTALL_0 Transfers will stall when the transmit FIFO is empty or the receive FIFO is full 0 NOSTALL_1 Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur 0x1 OUTCFG Output Config 26 1 read-write OUTCFG_0 Output data retains last value when chip select is negated 0 OUTCFG_1 Output data is tristated when chip select is negated 0x1 PCSCFG Peripheral Chip Select Configuration 27 1 read-write PCSCFG_0 PCS[3:2] are enabled 0 PCSCFG_1 PCS[3:2] are disabled 0x1 PCSPOL Peripheral Chip Select Polarity 8 4 read-write PCSPOL_0 The Peripheral Chip Select pin PCSx is active low 0 PCSPOL_1 The Peripheral Chip Select pin PCSx is active high 0x1 PINCFG Pin Configuration 24 2 read-write PINCFG_0 SIN is used for input data and SOUT is used for output data 0 PINCFG_1 SIN is used for both input and output data 0x1 PINCFG_2 SOUT is used for both input and output data 0x2 PINCFG_3 SOUT is used for input data and SIN is used for output data 0x3 SAMPLE Sample Point 1 1 read-write SAMPLE_0 Input data is sampled on SCK edge 0 SAMPLE_1 Input data is sampled on delayed SCK edge 0x1 CR Control Register 0x10 32 read-write n 0x0 0x0 DBGEN Debug Enable 3 1 read-write DBGEN_0 Module is disabled in debug mode 0 DBGEN_1 Module is enabled in debug mode 0x1 DOZEN Doze mode enable 2 1 read-write DOZEN_0 Module is enabled in Doze mode 0 DOZEN_1 Module is disabled in Doze mode 0x1 MEN Module Enable 0 1 read-write MEN_0 Module is disabled 0 MEN_1 Module is enabled 0x1 RRF Reset Receive FIFO 9 1 write-only RRF_0 No effect 0 RRF_1 Receive FIFO is reset 0x1 RST Software Reset 1 1 read-write RST_0 Master logic is not reset 0 RST_1 Master logic is reset 0x1 RTF Reset Transmit FIFO 8 1 write-only RTF_0 No effect 0 RTF_1 Transmit FIFO is reset 0x1 DER DMA Enable Register 0x1C 32 read-write n 0x0 0x0 RDDE Receive Data DMA Enable 1 1 read-write RDDE_0 DMA request is disabled 0 RDDE_1 DMA request is enabled 0x1 TDDE Transmit Data DMA Enable 0 1 read-write TDDE_0 DMA request is disabled 0 TDDE_1 DMA request is enabled 0x1 DMR0 Data Match Register 0 0x30 32 read-write n 0x0 0x0 MATCH0 Match 0 Value 0 32 read-write DMR1 Data Match Register 1 0x34 32 read-write n 0x0 0x0 MATCH1 Match 1 Value 0 32 read-write FCR FIFO Control Register 0x58 32 read-write n 0x0 0x0 RXWATER Receive FIFO Watermark 16 2 read-write TXWATER Transmit FIFO Watermark 0 2 read-write FSR FIFO Status Register 0x5C 32 read-only n 0x0 0x0 RXCOUNT Receive FIFO Count 16 3 read-only TXCOUNT Transmit FIFO Count 0 3 read-only IER Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 DMIE Data Match Interrupt Enable 13 1 read-write DMIE_0 Disabled 0 DMIE_1 Enabled 0x1 FCIE Frame Complete Interrupt Enable 9 1 read-write FCIE_0 Disabled 0 FCIE_1 Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write RDIE_0 Disabled 0 RDIE_1 Enabled 0x1 REIE Receive Error Interrupt Enable 12 1 read-write REIE_0 Disabled 0 REIE_1 Enabled 0x1 TCIE Transfer Complete Interrupt Enable 10 1 read-write TCIE_0 Disabled 0 TCIE_1 Enabled 0x1 TDIE Transmit Data Interrupt Enable 0 1 read-write TDIE_0 Disabled 0 TDIE_1 Enabled 0x1 TEIE Transmit Error Interrupt Enable 11 1 read-write TEIE_0 Disabled 0 TEIE_1 Enabled 0x1 WCIE Word Complete Interrupt Enable 8 1 read-write WCIE_0 Disabled 0 WCIE_1 Enabled 0x1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 RXFIFO Receive FIFO Size 8 8 read-only TXFIFO Transmit FIFO Size 0 8 read-only RDR Receive Data Register 0x74 32 read-only n 0x0 0x0 DATA Receive Data 0 32 read-only RSR Receive Status Register 0x70 32 read-only n 0x0 0x0 RXEMPTY RX FIFO Empty 1 1 read-only RXEMPTY_0 RX FIFO is not empty 0 RXEMPTY_1 RX FIFO is empty 0x1 SOF Start Of Frame 0 1 read-only SOF_0 Subsequent data word received after LPSPI_PCS assertion 0 SOF_1 First data word received after LPSPI_PCS assertion 0x1 SR Status Register 0x14 32 read-write n 0x0 0x0 DMF Data Match Flag 13 1 read-write oneToClear DMF_0 Have not received matching data 0 DMF_1 Have received matching data 0x1 FCF Frame Complete Flag 9 1 read-write oneToClear FCF_0 Frame transfer has not completed 0 FCF_1 Frame transfer has completed 0x1 MBF Module Busy Flag 24 1 read-only MBF_0 LPSPI is idle 0 MBF_1 LPSPI is busy 0x1 RDF Receive Data Flag 1 1 read-only RDF_0 Receive Data is not ready 0 RDF_1 Receive data is ready 0x1 REF Receive Error Flag 12 1 read-write oneToClear REF_0 Receive FIFO has not overflowed 0 REF_1 Receive FIFO has overflowed 0x1 TCF Transfer Complete Flag 10 1 read-write oneToClear TCF_0 All transfers have not completed 0 TCF_1 All transfers have completed 0x1 TDF Transmit Data Flag 0 1 read-only TDF_0 Transmit data not requested 0 TDF_1 Transmit data is requested 0x1 TEF Transmit Error Flag 11 1 read-write oneToClear TEF_0 Transmit FIFO underrun has not occurred 0 TEF_1 Transmit FIFO underrun has occurred 0x1 WCF Word Complete Flag 8 1 read-write oneToClear WCF_0 Transfer of a received word has not yet completed 0 WCF_1 Transfer of a received word has completed 0x1 TCR Transmit Command Register 0x60 32 read-write n 0x0 0x0 BYSW Byte Swap 22 1 read-write BYSW_0 Byte swap is disabled 0 BYSW_1 Byte swap is enabled 0x1 CONT Continuous Transfer 21 1 read-write CONT_0 Continuous transfer is disabled 0 CONT_1 Continuous transfer is enabled 0x1 CONTC Continuing Command 20 1 read-write CONTC_0 Command word for start of new transfer 0 CONTC_1 Command word for continuing transfer 0x1 CPHA Clock Phase 30 1 read-write CPHA_0 Data is captured on the leading edge of SCK and changed on the following edge of SCK 0 CPHA_1 Data is changed on the leading edge of SCK and captured on the following edge of SCK 0x1 CPOL Clock Polarity 31 1 read-write CPOL_0 The inactive state value of SCK is low 0 CPOL_1 The inactive state value of SCK is high 0x1 FRAMESZ Frame Size 0 12 read-write LSBF LSB First 23 1 read-write LSBF_0 Data is transferred MSB first 0 LSBF_1 Data is transferred LSB first 0x1 PCS Peripheral Chip Select 24 2 read-write PCS_0 Transfer using LPSPI_PCS[0] 0 PCS_1 Transfer using LPSPI_PCS[1] 0x1 PCS_2 Transfer using LPSPI_PCS[2] 0x2 PCS_3 Transfer using LPSPI_PCS[3] 0x3 PRESCALE Prescaler Value 27 3 read-write PRESCALE_0 Divide by 1 0 PRESCALE_1 Divide by 2 0x1 PRESCALE_2 Divide by 4 0x2 PRESCALE_3 Divide by 8 0x3 PRESCALE_4 Divide by 16 0x4 PRESCALE_5 Divide by 32 0x5 PRESCALE_6 Divide by 64 0x6 PRESCALE_7 Divide by 128 0x7 RXMSK Receive Data Mask 19 1 read-write RXMSK_0 Normal transfer 0 RXMSK_1 Receive data is masked 0x1 TXMSK Transmit Data Mask 18 1 read-write TXMSK_0 Normal transfer 0 TXMSK_1 Mask transmit data 0x1 WIDTH Transfer Width 16 2 read-write WIDTH_0 1 bit transfer 0 WIDTH_1 2 bit transfer 0x1 WIDTH_2 4 bit transfer 0x2 TDR Transmit Data Register 0x64 32 write-only n 0x0 0x0 DATA Transmit Data 0 32 write-only VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Module Identification Number 0 16 read-only FEATURE_4 Standard feature set supporting a 32-bit shift register. 0x4 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPSPI2 LPSPI LPSPI2 0x0 0x0 0x78 registers n LPSPI2 43 CCR Clock Configuration Register 0x40 32 read-write n 0x0 0x0 DBT Delay Between Transfers 8 8 read-write PCSSCK PCS-to-SCK Delay 16 8 read-write SCKDIV SCK Divider 0 8 read-write SCKPCS SCK-to-PCS Delay 24 8 read-write CFGR0 Configuration Register 0 0x20 32 read-write n 0x0 0x0 CIRFIFO Circular FIFO Enable 8 1 read-write CIRFIFO_0 Circular FIFO is disabled 0 CIRFIFO_1 Circular FIFO is enabled 0x1 HREN Host Request Enable 0 1 read-write HREN_0 Host request is disabled 0 HREN_1 Host request is enabled 0x1 HRPOL Host Request Polarity 1 1 read-write HRPOL_0 Active low 0 HRPOL_1 Active high 0x1 HRSEL Host Request Select 2 1 read-write HRSEL_0 Host request input is the LPSPI_HREQ pin 0 HRSEL_1 Host request input is the input trigger 0x1 RDMO Receive Data Match Only 9 1 read-write RDMO_0 Received data is stored in the receive FIFO as in normal operations 0 RDMO_1 Received data is discarded unless the Data Match Flag (DMF) is set 0x1 CFGR1 Configuration Register 1 0x24 32 read-write n 0x0 0x0 AUTOPCS Automatic PCS 2 1 read-write AUTOPCS_0 Automatic PCS generation is disabled 0 AUTOPCS_1 Automatic PCS generation is enabled 0x1 MASTER Master Mode 0 1 read-write MASTER_0 Slave mode 0 MASTER_1 Master mode 0x1 MATCFG Match Configuration 16 3 read-write MATCFG_0 Match is disabled 0 MATCFG_2 010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) 0x2 MATCFG_3 011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) 0x3 MATCFG_4 100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] 0x4 MATCFG_5 101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] 0x5 MATCFG_6 110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] 0x6 MATCFG_7 111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] 0x7 NOSTALL No Stall 3 1 read-write NOSTALL_0 Transfers will stall when the transmit FIFO is empty or the receive FIFO is full 0 NOSTALL_1 Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur 0x1 OUTCFG Output Config 26 1 read-write OUTCFG_0 Output data retains last value when chip select is negated 0 OUTCFG_1 Output data is tristated when chip select is negated 0x1 PCSCFG Peripheral Chip Select Configuration 27 1 read-write PCSCFG_0 PCS[3:2] are enabled 0 PCSCFG_1 PCS[3:2] are disabled 0x1 PCSPOL Peripheral Chip Select Polarity 8 4 read-write PCSPOL_0 The Peripheral Chip Select pin PCSx is active low 0 PCSPOL_1 The Peripheral Chip Select pin PCSx is active high 0x1 PINCFG Pin Configuration 24 2 read-write PINCFG_0 SIN is used for input data and SOUT is used for output data 0 PINCFG_1 SIN is used for both input and output data 0x1 PINCFG_2 SOUT is used for both input and output data 0x2 PINCFG_3 SOUT is used for input data and SIN is used for output data 0x3 SAMPLE Sample Point 1 1 read-write SAMPLE_0 Input data is sampled on SCK edge 0 SAMPLE_1 Input data is sampled on delayed SCK edge 0x1 CR Control Register 0x10 32 read-write n 0x0 0x0 DBGEN Debug Enable 3 1 read-write DBGEN_0 Module is disabled in debug mode 0 DBGEN_1 Module is enabled in debug mode 0x1 DOZEN Doze mode enable 2 1 read-write DOZEN_0 Module is enabled in Doze mode 0 DOZEN_1 Module is disabled in Doze mode 0x1 MEN Module Enable 0 1 read-write MEN_0 Module is disabled 0 MEN_1 Module is enabled 0x1 RRF Reset Receive FIFO 9 1 write-only RRF_0 No effect 0 RRF_1 Receive FIFO is reset 0x1 RST Software Reset 1 1 read-write RST_0 Master logic is not reset 0 RST_1 Master logic is reset 0x1 RTF Reset Transmit FIFO 8 1 write-only RTF_0 No effect 0 RTF_1 Transmit FIFO is reset 0x1 DER DMA Enable Register 0x1C 32 read-write n 0x0 0x0 RDDE Receive Data DMA Enable 1 1 read-write RDDE_0 DMA request is disabled 0 RDDE_1 DMA request is enabled 0x1 TDDE Transmit Data DMA Enable 0 1 read-write TDDE_0 DMA request is disabled 0 TDDE_1 DMA request is enabled 0x1 DMR0 Data Match Register 0 0x30 32 read-write n 0x0 0x0 MATCH0 Match 0 Value 0 32 read-write DMR1 Data Match Register 1 0x34 32 read-write n 0x0 0x0 MATCH1 Match 1 Value 0 32 read-write FCR FIFO Control Register 0x58 32 read-write n 0x0 0x0 RXWATER Receive FIFO Watermark 16 2 read-write TXWATER Transmit FIFO Watermark 0 2 read-write FSR FIFO Status Register 0x5C 32 read-only n 0x0 0x0 RXCOUNT Receive FIFO Count 16 3 read-only TXCOUNT Transmit FIFO Count 0 3 read-only IER Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 DMIE Data Match Interrupt Enable 13 1 read-write DMIE_0 Disabled 0 DMIE_1 Enabled 0x1 FCIE Frame Complete Interrupt Enable 9 1 read-write FCIE_0 Disabled 0 FCIE_1 Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write RDIE_0 Disabled 0 RDIE_1 Enabled 0x1 REIE Receive Error Interrupt Enable 12 1 read-write REIE_0 Disabled 0 REIE_1 Enabled 0x1 TCIE Transfer Complete Interrupt Enable 10 1 read-write TCIE_0 Disabled 0 TCIE_1 Enabled 0x1 TDIE Transmit Data Interrupt Enable 0 1 read-write TDIE_0 Disabled 0 TDIE_1 Enabled 0x1 TEIE Transmit Error Interrupt Enable 11 1 read-write TEIE_0 Disabled 0 TEIE_1 Enabled 0x1 WCIE Word Complete Interrupt Enable 8 1 read-write WCIE_0 Disabled 0 WCIE_1 Enabled 0x1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 RXFIFO Receive FIFO Size 8 8 read-only TXFIFO Transmit FIFO Size 0 8 read-only RDR Receive Data Register 0x74 32 read-only n 0x0 0x0 DATA Receive Data 0 32 read-only RSR Receive Status Register 0x70 32 read-only n 0x0 0x0 RXEMPTY RX FIFO Empty 1 1 read-only RXEMPTY_0 RX FIFO is not empty 0 RXEMPTY_1 RX FIFO is empty 0x1 SOF Start Of Frame 0 1 read-only SOF_0 Subsequent data word received after LPSPI_PCS assertion 0 SOF_1 First data word received after LPSPI_PCS assertion 0x1 SR Status Register 0x14 32 read-write n 0x0 0x0 DMF Data Match Flag 13 1 read-write oneToClear DMF_0 Have not received matching data 0 DMF_1 Have received matching data 0x1 FCF Frame Complete Flag 9 1 read-write oneToClear FCF_0 Frame transfer has not completed 0 FCF_1 Frame transfer has completed 0x1 MBF Module Busy Flag 24 1 read-only MBF_0 LPSPI is idle 0 MBF_1 LPSPI is busy 0x1 RDF Receive Data Flag 1 1 read-only RDF_0 Receive Data is not ready 0 RDF_1 Receive data is ready 0x1 REF Receive Error Flag 12 1 read-write oneToClear REF_0 Receive FIFO has not overflowed 0 REF_1 Receive FIFO has overflowed 0x1 TCF Transfer Complete Flag 10 1 read-write oneToClear TCF_0 All transfers have not completed 0 TCF_1 All transfers have completed 0x1 TDF Transmit Data Flag 0 1 read-only TDF_0 Transmit data not requested 0 TDF_1 Transmit data is requested 0x1 TEF Transmit Error Flag 11 1 read-write oneToClear TEF_0 Transmit FIFO underrun has not occurred 0 TEF_1 Transmit FIFO underrun has occurred 0x1 WCF Word Complete Flag 8 1 read-write oneToClear WCF_0 Transfer of a received word has not yet completed 0 WCF_1 Transfer of a received word has completed 0x1 TCR Transmit Command Register 0x60 32 read-write n 0x0 0x0 BYSW Byte Swap 22 1 read-write BYSW_0 Byte swap is disabled 0 BYSW_1 Byte swap is enabled 0x1 CONT Continuous Transfer 21 1 read-write CONT_0 Continuous transfer is disabled 0 CONT_1 Continuous transfer is enabled 0x1 CONTC Continuing Command 20 1 read-write CONTC_0 Command word for start of new transfer 0 CONTC_1 Command word for continuing transfer 0x1 CPHA Clock Phase 30 1 read-write CPHA_0 Data is captured on the leading edge of SCK and changed on the following edge of SCK 0 CPHA_1 Data is changed on the leading edge of SCK and captured on the following edge of SCK 0x1 CPOL Clock Polarity 31 1 read-write CPOL_0 The inactive state value of SCK is low 0 CPOL_1 The inactive state value of SCK is high 0x1 FRAMESZ Frame Size 0 12 read-write LSBF LSB First 23 1 read-write LSBF_0 Data is transferred MSB first 0 LSBF_1 Data is transferred LSB first 0x1 PCS Peripheral Chip Select 24 2 read-write PCS_0 Transfer using LPSPI_PCS[0] 0 PCS_1 Transfer using LPSPI_PCS[1] 0x1 PCS_2 Transfer using LPSPI_PCS[2] 0x2 PCS_3 Transfer using LPSPI_PCS[3] 0x3 PRESCALE Prescaler Value 27 3 read-write PRESCALE_0 Divide by 1 0 PRESCALE_1 Divide by 2 0x1 PRESCALE_2 Divide by 4 0x2 PRESCALE_3 Divide by 8 0x3 PRESCALE_4 Divide by 16 0x4 PRESCALE_5 Divide by 32 0x5 PRESCALE_6 Divide by 64 0x6 PRESCALE_7 Divide by 128 0x7 RXMSK Receive Data Mask 19 1 read-write RXMSK_0 Normal transfer 0 RXMSK_1 Receive data is masked 0x1 TXMSK Transmit Data Mask 18 1 read-write TXMSK_0 Normal transfer 0 TXMSK_1 Mask transmit data 0x1 WIDTH Transfer Width 16 2 read-write WIDTH_0 1 bit transfer 0 WIDTH_1 2 bit transfer 0x1 WIDTH_2 4 bit transfer 0x2 TDR Transmit Data Register 0x64 32 write-only n 0x0 0x0 DATA Transmit Data 0 32 write-only VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Module Identification Number 0 16 read-only FEATURE_4 Standard feature set supporting a 32-bit shift register. 0x4 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPSPI3 LPSPI LPSPI3 0x0 0x0 0x78 registers n LPSPI3 62 CCR Clock Configuration Register 0x40 32 read-write n 0x0 0x0 DBT Delay Between Transfers 8 8 read-write PCSSCK PCS-to-SCK Delay 16 8 read-write SCKDIV SCK Divider 0 8 read-write SCKPCS SCK-to-PCS Delay 24 8 read-write CFGR0 Configuration Register 0 0x20 32 read-write n 0x0 0x0 CIRFIFO Circular FIFO Enable 8 1 read-write CIRFIFO_0 Circular FIFO is disabled 0 CIRFIFO_1 Circular FIFO is enabled 0x1 HREN Host Request Enable 0 1 read-write HREN_0 Host request is disabled 0 HREN_1 Host request is enabled 0x1 HRPOL Host Request Polarity 1 1 read-write HRPOL_0 Active low 0 HRPOL_1 Active high 0x1 HRSEL Host Request Select 2 1 read-write HRSEL_0 Host request input is the LPSPI_HREQ pin 0 HRSEL_1 Host request input is the input trigger 0x1 RDMO Receive Data Match Only 9 1 read-write RDMO_0 Received data is stored in the receive FIFO as in normal operations 0 RDMO_1 Received data is discarded unless the Data Match Flag (DMF) is set 0x1 CFGR1 Configuration Register 1 0x24 32 read-write n 0x0 0x0 AUTOPCS Automatic PCS 2 1 read-write AUTOPCS_0 Automatic PCS generation is disabled 0 AUTOPCS_1 Automatic PCS generation is enabled 0x1 MASTER Master Mode 0 1 read-write MASTER_0 Slave mode 0 MASTER_1 Master mode 0x1 MATCFG Match Configuration 16 3 read-write MATCFG_0 Match is disabled 0 MATCFG_2 010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) 0x2 MATCFG_3 011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) 0x3 MATCFG_4 100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st data word = MATCH0) * (2nd data word = MATCH1)] 0x4 MATCFG_5 101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., [(any data word = MATCH0) * (next data word = MATCH1)] 0x5 MATCFG_6 110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] 0x6 MATCFG_7 111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] 0x7 NOSTALL No Stall 3 1 read-write NOSTALL_0 Transfers will stall when the transmit FIFO is empty or the receive FIFO is full 0 NOSTALL_1 Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur 0x1 OUTCFG Output Config 26 1 read-write OUTCFG_0 Output data retains last value when chip select is negated 0 OUTCFG_1 Output data is tristated when chip select is negated 0x1 PCSCFG Peripheral Chip Select Configuration 27 1 read-write PCSCFG_0 PCS[3:2] are enabled 0 PCSCFG_1 PCS[3:2] are disabled 0x1 PCSPOL Peripheral Chip Select Polarity 8 4 read-write PCSPOL_0 The Peripheral Chip Select pin PCSx is active low 0 PCSPOL_1 The Peripheral Chip Select pin PCSx is active high 0x1 PINCFG Pin Configuration 24 2 read-write PINCFG_0 SIN is used for input data and SOUT is used for output data 0 PINCFG_1 SIN is used for both input and output data 0x1 PINCFG_2 SOUT is used for both input and output data 0x2 PINCFG_3 SOUT is used for input data and SIN is used for output data 0x3 SAMPLE Sample Point 1 1 read-write SAMPLE_0 Input data is sampled on SCK edge 0 SAMPLE_1 Input data is sampled on delayed SCK edge 0x1 CR Control Register 0x10 32 read-write n 0x0 0x0 DBGEN Debug Enable 3 1 read-write DBGEN_0 Module is disabled in debug mode 0 DBGEN_1 Module is enabled in debug mode 0x1 DOZEN Doze mode enable 2 1 read-write DOZEN_0 Module is enabled in Doze mode 0 DOZEN_1 Module is disabled in Doze mode 0x1 MEN Module Enable 0 1 read-write MEN_0 Module is disabled 0 MEN_1 Module is enabled 0x1 RRF Reset Receive FIFO 9 1 write-only RRF_0 No effect 0 RRF_1 Receive FIFO is reset 0x1 RST Software Reset 1 1 read-write RST_0 Master logic is not reset 0 RST_1 Master logic is reset 0x1 RTF Reset Transmit FIFO 8 1 write-only RTF_0 No effect 0 RTF_1 Transmit FIFO is reset 0x1 DER DMA Enable Register 0x1C 32 read-write n 0x0 0x0 RDDE Receive Data DMA Enable 1 1 read-write RDDE_0 DMA request is disabled 0 RDDE_1 DMA request is enabled 0x1 TDDE Transmit Data DMA Enable 0 1 read-write TDDE_0 DMA request is disabled 0 TDDE_1 DMA request is enabled 0x1 DMR0 Data Match Register 0 0x30 32 read-write n 0x0 0x0 MATCH0 Match 0 Value 0 32 read-write DMR1 Data Match Register 1 0x34 32 read-write n 0x0 0x0 MATCH1 Match 1 Value 0 32 read-write FCR FIFO Control Register 0x58 32 read-write n 0x0 0x0 RXWATER Receive FIFO Watermark 16 2 read-write TXWATER Transmit FIFO Watermark 0 2 read-write FSR FIFO Status Register 0x5C 32 read-only n 0x0 0x0 RXCOUNT Receive FIFO Count 16 3 read-only TXCOUNT Transmit FIFO Count 0 3 read-only IER Interrupt Enable Register 0x18 32 read-write n 0x0 0x0 DMIE Data Match Interrupt Enable 13 1 read-write DMIE_0 Disabled 0 DMIE_1 Enabled 0x1 FCIE Frame Complete Interrupt Enable 9 1 read-write FCIE_0 Disabled 0 FCIE_1 Enabled 0x1 RDIE Receive Data Interrupt Enable 1 1 read-write RDIE_0 Disabled 0 RDIE_1 Enabled 0x1 REIE Receive Error Interrupt Enable 12 1 read-write REIE_0 Disabled 0 REIE_1 Enabled 0x1 TCIE Transfer Complete Interrupt Enable 10 1 read-write TCIE_0 Disabled 0 TCIE_1 Enabled 0x1 TDIE Transmit Data Interrupt Enable 0 1 read-write TDIE_0 Disabled 0 TDIE_1 Enabled 0x1 TEIE Transmit Error Interrupt Enable 11 1 read-write TEIE_0 Disabled 0 TEIE_1 Enabled 0x1 WCIE Word Complete Interrupt Enable 8 1 read-write WCIE_0 Disabled 0 WCIE_1 Enabled 0x1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 RXFIFO Receive FIFO Size 8 8 read-only TXFIFO Transmit FIFO Size 0 8 read-only RDR Receive Data Register 0x74 32 read-only n 0x0 0x0 DATA Receive Data 0 32 read-only RSR Receive Status Register 0x70 32 read-only n 0x0 0x0 RXEMPTY RX FIFO Empty 1 1 read-only RXEMPTY_0 RX FIFO is not empty 0 RXEMPTY_1 RX FIFO is empty 0x1 SOF Start Of Frame 0 1 read-only SOF_0 Subsequent data word received after LPSPI_PCS assertion 0 SOF_1 First data word received after LPSPI_PCS assertion 0x1 SR Status Register 0x14 32 read-write n 0x0 0x0 DMF Data Match Flag 13 1 read-write oneToClear DMF_0 Have not received matching data 0 DMF_1 Have received matching data 0x1 FCF Frame Complete Flag 9 1 read-write oneToClear FCF_0 Frame transfer has not completed 0 FCF_1 Frame transfer has completed 0x1 MBF Module Busy Flag 24 1 read-only MBF_0 LPSPI is idle 0 MBF_1 LPSPI is busy 0x1 RDF Receive Data Flag 1 1 read-only RDF_0 Receive Data is not ready 0 RDF_1 Receive data is ready 0x1 REF Receive Error Flag 12 1 read-write oneToClear REF_0 Receive FIFO has not overflowed 0 REF_1 Receive FIFO has overflowed 0x1 TCF Transfer Complete Flag 10 1 read-write oneToClear TCF_0 All transfers have not completed 0 TCF_1 All transfers have completed 0x1 TDF Transmit Data Flag 0 1 read-only TDF_0 Transmit data not requested 0 TDF_1 Transmit data is requested 0x1 TEF Transmit Error Flag 11 1 read-write oneToClear TEF_0 Transmit FIFO underrun has not occurred 0 TEF_1 Transmit FIFO underrun has occurred 0x1 WCF Word Complete Flag 8 1 read-write oneToClear WCF_0 Transfer of a received word has not yet completed 0 WCF_1 Transfer of a received word has completed 0x1 TCR Transmit Command Register 0x60 32 read-write n 0x0 0x0 BYSW Byte Swap 22 1 read-write BYSW_0 Byte swap is disabled 0 BYSW_1 Byte swap is enabled 0x1 CONT Continuous Transfer 21 1 read-write CONT_0 Continuous transfer is disabled 0 CONT_1 Continuous transfer is enabled 0x1 CONTC Continuing Command 20 1 read-write CONTC_0 Command word for start of new transfer 0 CONTC_1 Command word for continuing transfer 0x1 CPHA Clock Phase 30 1 read-write CPHA_0 Data is captured on the leading edge of SCK and changed on the following edge of SCK 0 CPHA_1 Data is changed on the leading edge of SCK and captured on the following edge of SCK 0x1 CPOL Clock Polarity 31 1 read-write CPOL_0 The inactive state value of SCK is low 0 CPOL_1 The inactive state value of SCK is high 0x1 FRAMESZ Frame Size 0 12 read-write LSBF LSB First 23 1 read-write LSBF_0 Data is transferred MSB first 0 LSBF_1 Data is transferred LSB first 0x1 PCS Peripheral Chip Select 24 2 read-write PCS_0 Transfer using LPSPI_PCS[0] 0 PCS_1 Transfer using LPSPI_PCS[1] 0x1 PCS_2 Transfer using LPSPI_PCS[2] 0x2 PCS_3 Transfer using LPSPI_PCS[3] 0x3 PRESCALE Prescaler Value 27 3 read-write PRESCALE_0 Divide by 1 0 PRESCALE_1 Divide by 2 0x1 PRESCALE_2 Divide by 4 0x2 PRESCALE_3 Divide by 8 0x3 PRESCALE_4 Divide by 16 0x4 PRESCALE_5 Divide by 32 0x5 PRESCALE_6 Divide by 64 0x6 PRESCALE_7 Divide by 128 0x7 RXMSK Receive Data Mask 19 1 read-write RXMSK_0 Normal transfer 0 RXMSK_1 Receive data is masked 0x1 TXMSK Transmit Data Mask 18 1 read-write TXMSK_0 Normal transfer 0 TXMSK_1 Mask transmit data 0x1 WIDTH Transfer Width 16 2 read-write WIDTH_0 1 bit transfer 0 WIDTH_1 2 bit transfer 0x1 WIDTH_2 4 bit transfer 0x2 TDR Transmit Data Register 0x64 32 write-only n 0x0 0x0 DATA Transmit Data 0 32 write-only VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Module Identification Number 0 16 read-only FEATURE_4 Standard feature set supporting a 32-bit shift register. 0x4 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only LPTMR0 LPTMR LPTIMER0 0x0 0x0 0x10 registers n LPTMR0 29 CMR Low Power Timer Compare Register 0x8 32 read-write n 0x0 0x0 COMPARE Compare Value 0 32 read-write CNR Low Power Timer Counter Register 0xC 32 read-write n 0x0 0x0 COUNTER Counter Value 0 32 read-write CSR Low Power Timer Control Status Register 0x0 32 read-write n 0x0 0x0 TCF Timer Compare Flag 7 1 read-write oneToClear TCF_0 The value of CNR is not equal to CMR and increments. 0 TCF_1 The value of CNR is equal to CMR and increments. 0x1 TDRE Timer DMA Request Enable 8 1 read-write TDRE_0 Timer DMA Request disabled. 0 TDRE_1 Timer DMA Request enabled. 0x1 TEN Timer Enable 0 1 read-write TEN_0 LPTMR is disabled and internal logic is reset. 0 TEN_1 LPTMR is enabled. 0x1 TFC Timer Free-Running Counter 2 1 read-write TFC_0 CNR is reset whenever TCF is set. 0 TFC_1 CNR is reset on overflow. 0x1 TIE Timer Interrupt Enable 6 1 read-write TIE_0 Timer interrupt disabled. 0 TIE_1 Timer interrupt enabled. 0x1 TMS Timer Mode Select 1 1 read-write TMS_0 Time Counter mode. 0 TMS_1 Pulse Counter mode. 0x1 TPP Timer Pin Polarity 3 1 read-write TPP_0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. 0 TPP_1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. 0x1 TPS Timer Pin Select 4 2 read-write TPS_0 Pulse counter input 0 is selected. 0 TPS_1 Pulse counter input 1 is selected. 0x1 TPS_2 Pulse counter input 2 is selected. 0x2 TPS_3 Pulse counter input 3 is selected. 0x3 PSR Low Power Timer Prescale Register 0x4 32 read-write n 0x0 0x0 PBYP Prescaler Bypass 2 1 read-write PBYP_0 Prescaler/glitch filter is enabled. 0 PBYP_1 Prescaler/glitch filter is bypassed. 0x1 PCS Prescaler Clock Select 0 2 read-write PCS_0 Prescaler/glitch filter clock 0 selected. 0 PCS_1 Prescaler/glitch filter clock 1 selected. 0x1 PCS_2 Prescaler/glitch filter clock 2 selected. 0x2 PCS_3 Prescaler/glitch filter clock 3 selected. 0x3 PRESCALE Prescale Value 3 4 read-write PRESCALE_0 Prescaler divides the prescaler clock by 2 glitch filter does not support this configuration. 0 PRESCALE_1 Prescaler divides the prescaler clock by 4 glitch filter recognizes change on input pin after 2 rising clock edges. 0x1 PRESCALE_2 Prescaler divides the prescaler clock by 8 glitch filter recognizes change on input pin after 4 rising clock edges. 0x2 PRESCALE_3 Prescaler divides the prescaler clock by 16 glitch filter recognizes change on input pin after 8 rising clock edges. 0x3 PRESCALE_4 Prescaler divides the prescaler clock by 32 glitch filter recognizes change on input pin after 16 rising clock edges. 0x4 PRESCALE_5 Prescaler divides the prescaler clock by 64 glitch filter recognizes change on input pin after 32 rising clock edges. 0x5 PRESCALE_6 Prescaler divides the prescaler clock by 128 glitch filter recognizes change on input pin after 64 rising clock edges. 0x6 PRESCALE_7 Prescaler divides the prescaler clock by 256 glitch filter recognizes change on input pin after 128 rising clock edges. 0x7 PRESCALE_8 Prescaler divides the prescaler clock by 512 glitch filter recognizes change on input pin after 256 rising clock edges. 0x8 PRESCALE_9 Prescaler divides the prescaler clock by 1024 glitch filter recognizes change on input pin after 512 rising clock edges. 0x9 PRESCALE_10 Prescaler divides the prescaler clock by 2048 glitch filter recognizes change on input pin after 1024 rising clock edges. 0xA PRESCALE_11 Prescaler divides the prescaler clock by 4096 glitch filter recognizes change on input pin after 2048 rising clock edges. 0xB PRESCALE_12 Prescaler divides the prescaler clock by 8192 glitch filter recognizes change on input pin after 4096 rising clock edges. 0xC PRESCALE_13 Prescaler divides the prescaler clock by 16,384 glitch filter recognizes change on input pin after 8192 rising clock edges. 0xD PRESCALE_14 Prescaler divides the prescaler clock by 32,768 glitch filter recognizes change on input pin after 16,384 rising clock edges. 0xE PRESCALE_15 Prescaler divides the prescaler clock by 65,536 glitch filter recognizes change on input pin after 32,768 rising clock edges. 0xF LPTMR1 LPTMR LPTIMER1 0x0 0x0 0x10 registers n LPTMR1 30 CMR Low Power Timer Compare Register 0x8 32 read-write n 0x0 0x0 COMPARE Compare Value 0 32 read-write CNR Low Power Timer Counter Register 0xC 32 read-write n 0x0 0x0 COUNTER Counter Value 0 32 read-write CSR Low Power Timer Control Status Register 0x0 32 read-write n 0x0 0x0 TCF Timer Compare Flag 7 1 read-write oneToClear TCF_0 The value of CNR is not equal to CMR and increments. 0 TCF_1 The value of CNR is equal to CMR and increments. 0x1 TDRE Timer DMA Request Enable 8 1 read-write TDRE_0 Timer DMA Request disabled. 0 TDRE_1 Timer DMA Request enabled. 0x1 TEN Timer Enable 0 1 read-write TEN_0 LPTMR is disabled and internal logic is reset. 0 TEN_1 LPTMR is enabled. 0x1 TFC Timer Free-Running Counter 2 1 read-write TFC_0 CNR is reset whenever TCF is set. 0 TFC_1 CNR is reset on overflow. 0x1 TIE Timer Interrupt Enable 6 1 read-write TIE_0 Timer interrupt disabled. 0 TIE_1 Timer interrupt enabled. 0x1 TMS Timer Mode Select 1 1 read-write TMS_0 Time Counter mode. 0 TMS_1 Pulse Counter mode. 0x1 TPP Timer Pin Polarity 3 1 read-write TPP_0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. 0 TPP_1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. 0x1 TPS Timer Pin Select 4 2 read-write TPS_0 Pulse counter input 0 is selected. 0 TPS_1 Pulse counter input 1 is selected. 0x1 TPS_2 Pulse counter input 2 is selected. 0x2 TPS_3 Pulse counter input 3 is selected. 0x3 PSR Low Power Timer Prescale Register 0x4 32 read-write n 0x0 0x0 PBYP Prescaler Bypass 2 1 read-write PBYP_0 Prescaler/glitch filter is enabled. 0 PBYP_1 Prescaler/glitch filter is bypassed. 0x1 PCS Prescaler Clock Select 0 2 read-write PCS_0 Prescaler/glitch filter clock 0 selected. 0 PCS_1 Prescaler/glitch filter clock 1 selected. 0x1 PCS_2 Prescaler/glitch filter clock 2 selected. 0x2 PCS_3 Prescaler/glitch filter clock 3 selected. 0x3 PRESCALE Prescale Value 3 4 read-write PRESCALE_0 Prescaler divides the prescaler clock by 2 glitch filter does not support this configuration. 0 PRESCALE_1 Prescaler divides the prescaler clock by 4 glitch filter recognizes change on input pin after 2 rising clock edges. 0x1 PRESCALE_2 Prescaler divides the prescaler clock by 8 glitch filter recognizes change on input pin after 4 rising clock edges. 0x2 PRESCALE_3 Prescaler divides the prescaler clock by 16 glitch filter recognizes change on input pin after 8 rising clock edges. 0x3 PRESCALE_4 Prescaler divides the prescaler clock by 32 glitch filter recognizes change on input pin after 16 rising clock edges. 0x4 PRESCALE_5 Prescaler divides the prescaler clock by 64 glitch filter recognizes change on input pin after 32 rising clock edges. 0x5 PRESCALE_6 Prescaler divides the prescaler clock by 128 glitch filter recognizes change on input pin after 64 rising clock edges. 0x6 PRESCALE_7 Prescaler divides the prescaler clock by 256 glitch filter recognizes change on input pin after 128 rising clock edges. 0x7 PRESCALE_8 Prescaler divides the prescaler clock by 512 glitch filter recognizes change on input pin after 256 rising clock edges. 0x8 PRESCALE_9 Prescaler divides the prescaler clock by 1024 glitch filter recognizes change on input pin after 512 rising clock edges. 0x9 PRESCALE_10 Prescaler divides the prescaler clock by 2048 glitch filter recognizes change on input pin after 1024 rising clock edges. 0xA PRESCALE_11 Prescaler divides the prescaler clock by 4096 glitch filter recognizes change on input pin after 2048 rising clock edges. 0xB PRESCALE_12 Prescaler divides the prescaler clock by 8192 glitch filter recognizes change on input pin after 4096 rising clock edges. 0xC PRESCALE_13 Prescaler divides the prescaler clock by 16,384 glitch filter recognizes change on input pin after 8192 rising clock edges. 0xD PRESCALE_14 Prescaler divides the prescaler clock by 32,768 glitch filter recognizes change on input pin after 16,384 rising clock edges. 0xE PRESCALE_15 Prescaler divides the prescaler clock by 65,536 glitch filter recognizes change on input pin after 32,768 rising clock edges. 0xF LPTMR2 LPTMR LPTIMER2 0x0 0x0 0x10 registers n LPTMR2 59 CMR Low Power Timer Compare Register 0x8 32 read-write n 0x0 0x0 COMPARE Compare Value 0 32 read-write CNR Low Power Timer Counter Register 0xC 32 read-write n 0x0 0x0 COUNTER Counter Value 0 32 read-write CSR Low Power Timer Control Status Register 0x0 32 read-write n 0x0 0x0 TCF Timer Compare Flag 7 1 read-write oneToClear TCF_0 The value of CNR is not equal to CMR and increments. 0 TCF_1 The value of CNR is equal to CMR and increments. 0x1 TDRE Timer DMA Request Enable 8 1 read-write TDRE_0 Timer DMA Request disabled. 0 TDRE_1 Timer DMA Request enabled. 0x1 TEN Timer Enable 0 1 read-write TEN_0 LPTMR is disabled and internal logic is reset. 0 TEN_1 LPTMR is enabled. 0x1 TFC Timer Free-Running Counter 2 1 read-write TFC_0 CNR is reset whenever TCF is set. 0 TFC_1 CNR is reset on overflow. 0x1 TIE Timer Interrupt Enable 6 1 read-write TIE_0 Timer interrupt disabled. 0 TIE_1 Timer interrupt enabled. 0x1 TMS Timer Mode Select 1 1 read-write TMS_0 Time Counter mode. 0 TMS_1 Pulse Counter mode. 0x1 TPP Timer Pin Polarity 3 1 read-write TPP_0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. 0 TPP_1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. 0x1 TPS Timer Pin Select 4 2 read-write TPS_0 Pulse counter input 0 is selected. 0 TPS_1 Pulse counter input 1 is selected. 0x1 TPS_2 Pulse counter input 2 is selected. 0x2 TPS_3 Pulse counter input 3 is selected. 0x3 PSR Low Power Timer Prescale Register 0x4 32 read-write n 0x0 0x0 PBYP Prescaler Bypass 2 1 read-write PBYP_0 Prescaler/glitch filter is enabled. 0 PBYP_1 Prescaler/glitch filter is bypassed. 0x1 PCS Prescaler Clock Select 0 2 read-write PCS_0 Prescaler/glitch filter clock 0 selected. 0 PCS_1 Prescaler/glitch filter clock 1 selected. 0x1 PCS_2 Prescaler/glitch filter clock 2 selected. 0x2 PCS_3 Prescaler/glitch filter clock 3 selected. 0x3 PRESCALE Prescale Value 3 4 read-write PRESCALE_0 Prescaler divides the prescaler clock by 2 glitch filter does not support this configuration. 0 PRESCALE_1 Prescaler divides the prescaler clock by 4 glitch filter recognizes change on input pin after 2 rising clock edges. 0x1 PRESCALE_2 Prescaler divides the prescaler clock by 8 glitch filter recognizes change on input pin after 4 rising clock edges. 0x2 PRESCALE_3 Prescaler divides the prescaler clock by 16 glitch filter recognizes change on input pin after 8 rising clock edges. 0x3 PRESCALE_4 Prescaler divides the prescaler clock by 32 glitch filter recognizes change on input pin after 16 rising clock edges. 0x4 PRESCALE_5 Prescaler divides the prescaler clock by 64 glitch filter recognizes change on input pin after 32 rising clock edges. 0x5 PRESCALE_6 Prescaler divides the prescaler clock by 128 glitch filter recognizes change on input pin after 64 rising clock edges. 0x6 PRESCALE_7 Prescaler divides the prescaler clock by 256 glitch filter recognizes change on input pin after 128 rising clock edges. 0x7 PRESCALE_8 Prescaler divides the prescaler clock by 512 glitch filter recognizes change on input pin after 256 rising clock edges. 0x8 PRESCALE_9 Prescaler divides the prescaler clock by 1024 glitch filter recognizes change on input pin after 512 rising clock edges. 0x9 PRESCALE_10 Prescaler divides the prescaler clock by 2048 glitch filter recognizes change on input pin after 1024 rising clock edges. 0xA PRESCALE_11 Prescaler divides the prescaler clock by 4096 glitch filter recognizes change on input pin after 2048 rising clock edges. 0xB PRESCALE_12 Prescaler divides the prescaler clock by 8192 glitch filter recognizes change on input pin after 4096 rising clock edges. 0xC PRESCALE_13 Prescaler divides the prescaler clock by 16,384 glitch filter recognizes change on input pin after 8192 rising clock edges. 0xD PRESCALE_14 Prescaler divides the prescaler clock by 32,768 glitch filter recognizes change on input pin after 16,384 rising clock edges. 0xE PRESCALE_15 Prescaler divides the prescaler clock by 65,536 glitch filter recognizes change on input pin after 32,768 rising clock edges. 0xF LPUART0 LPUART LPUART0 0x0 0x0 0x30 registers n LPUART0 44 BAUD LPUART Baud Rate Register 0x10 32 read-write n 0x0 0x0 BOTHEDGE Both Edge Sampling 17 1 read-write BOTHEDGE_0 Receiver samples input data using the rising edge of the baud rate clock. 0 BOTHEDGE_1 Receiver samples input data using the rising and falling edge of the baud rate clock. 0x1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write LBKDIE_0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). 0 LBKDIE_1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. 0x1 M10 10-bit Mode select 29 1 read-write M10_0 Receiver and transmitter use 7-bit to 9-bit data characters. 0 M10_1 Receiver and transmitter use 10-bit data characters. 0x1 MAEN1 Match Address Mode Enable 1 31 1 read-write MAEN1_0 Normal operation. 0 MAEN1_1 Enables automatic address matching or data matching mode for MATCH[MA1]. 0x1 MAEN2 Match Address Mode Enable 2 30 1 read-write MAEN2_0 Normal operation. 0 MAEN2_1 Enables automatic address matching or data matching mode for MATCH[MA2]. 0x1 MATCFG Match Configuration 18 2 read-write MATCFG_0 Address Match Wakeup 0 MATCFG_1 Idle Match Wakeup 0x1 MATCFG_2 Match On and Match Off 0x2 MATCFG_3 no description available 0x3 OSR Oversampling Ratio 24 5 read-write OSR_0 Writing 0 to this field will result in an oversampling ratio of 16 0 OSR_16 Oversampling ratio of 17. 0x10 OSR_17 Oversampling ratio of 18. 0x11 OSR_18 Oversampling ratio of 19. 0x12 OSR_19 Oversampling ratio of 20. 0x13 OSR_20 Oversampling ratio of 21. 0x14 OSR_21 Oversampling ratio of 22. 0x15 OSR_22 Oversampling ratio of 23. 0x16 OSR_23 Oversampling ratio of 24. 0x17 OSR_24 Oversampling ratio of 25. 0x18 OSR_25 Oversampling ratio of 26. 0x19 OSR_26 Oversampling ratio of 27. 0x1A OSR_27 Oversampling ratio of 28. 0x1B OSR_28 Oversampling ratio of 29. 0x1C OSR_29 Oversampling ratio of 30. 0x1D OSR_30 Oversampling ratio of 31. 0x1E OSR_31 Oversampling ratio of 32. 0x1F OSR_3 Oversampling ratio of 4, requires BOTHEDGE to be set. 0x3 OSR_4 Oversampling ratio of 5, requires BOTHEDGE to be set. 0x4 OSR_5 Oversampling ratio of 6, requires BOTHEDGE to be set. 0x5 OSR_6 Oversampling ratio of 7, requires BOTHEDGE to be set. 0x6 OSR_7 Oversampling ratio of 8. 0x7 OSR_8 Oversampling ratio of 9. 0x8 OSR_9 Oversampling ratio of 10. 0x9 OSR_10 Oversampling ratio of 11. 0xA OSR_11 Oversampling ratio of 12. 0xB OSR_12 Oversampling ratio of 13. 0xC OSR_13 Oversampling ratio of 14. 0xD OSR_14 Oversampling ratio of 15. 0xE OSR_15 Oversampling ratio of 16. 0xF RDMAE Receiver Full DMA Enable 21 1 read-write RDMAE_0 DMA request disabled. 0 RDMAE_1 DMA request enabled. 0x1 RESYNCDIS Resynchronization Disable 16 1 read-write RESYNCDIS_0 Resynchronization during received data word is supported 0 RESYNCDIS_1 Resynchronization during received data word is disabled 0x1 RIDMAE Receiver Idle DMA Enable 20 1 read-write RIDMAE_0 DMA request disabled. 0 RIDMAE_1 DMA request enabled. 0x1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write RXEDGIE_0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled. 0 RXEDGIE_1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. 0x1 SBNS Stop Bit Number Select 13 1 read-write SBNS_0 One stop bit. 0 SBNS_1 Two stop bits. 0x1 SBR Baud Rate Modulo Divisor. 0 13 read-write TDMAE Transmitter DMA Enable 23 1 read-write TDMAE_0 DMA request disabled. 0 TDMAE_1 DMA request enabled. 0x1 CTRL LPUART Control Register 0x18 32 read-write n 0x0 0x0 DOZEEN Doze Enable 6 1 read-write DOZEEN_0 LPUART is enabled in Doze mode. 0 DOZEEN_1 LPUART is disabled in Doze mode. 0x1 FEIE Framing Error Interrupt Enable 25 1 read-write FEIE_0 FE interrupts disabled use polling. 0 FEIE_1 Hardware interrupt requested when FE is set. 0x1 IDLECFG Idle Configuration 8 3 read-write IDLECFG_0 1 idle character 0 IDLECFG_1 2 idle characters 0x1 IDLECFG_2 4 idle characters 0x2 IDLECFG_3 8 idle characters 0x3 IDLECFG_4 16 idle characters 0x4 IDLECFG_5 32 idle characters 0x5 IDLECFG_6 64 idle characters 0x6 IDLECFG_7 128 idle characters 0x7 ILIE Idle Line Interrupt Enable 20 1 read-write ILIE_0 Hardware interrupts from IDLE disabled use polling. 0 ILIE_1 Hardware interrupt requested when IDLE flag is 1. 0x1 ILT Idle Line Type Select 2 1 read-write ILT_0 Idle character bit count starts after start bit. 0 ILT_1 Idle character bit count starts after stop bit. 0x1 LOOPS Loop Mode Select 7 1 read-write LOOPS_0 Normal operation - RXD and TXD use separate pins. 0 LOOPS_1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). 0x1 M 9-Bit or 8-Bit Mode Select 4 1 read-write M_0 Receiver and transmitter use 8-bit data characters. 0 M_1 Receiver and transmitter use 9-bit data characters. 0x1 M7 7-Bit Mode Select 11 1 read-write M7_0 Receiver and transmitter use 8-bit to 10-bit data characters. 0 M7_1 Receiver and transmitter use 7-bit data characters. 0x1 MA1IE Match 1 Interrupt Enable 15 1 read-write MA1IE_0 MA1F interrupt disabled 0 MA1IE_1 MA1F interrupt enabled 0x1 MA2IE Match 2 Interrupt Enable 14 1 read-write MA2IE_0 MA2F interrupt disabled 0 MA2IE_1 MA2F interrupt enabled 0x1 NEIE Noise Error Interrupt Enable 26 1 read-write NEIE_0 NF interrupts disabled use polling. 0 NEIE_1 Hardware interrupt requested when NF is set. 0x1 ORIE Overrun Interrupt Enable 27 1 read-write ORIE_0 OR interrupts disabled use polling. 0 ORIE_1 Hardware interrupt requested when OR is set. 0x1 PE Parity Enable 1 1 read-write PE_0 No hardware parity generation or checking. 0 PE_1 Parity enabled. 0x1 PEIE Parity Error Interrupt Enable 24 1 read-write PEIE_0 PF interrupts disabled use polling). 0 PEIE_1 Hardware interrupt requested when PF is set. 0x1 PT Parity Type 0 1 read-write PT_0 Even parity. 0 PT_1 Odd parity. 0x1 R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write RE Receiver Enable 18 1 read-write RE_0 Receiver disabled. 0 RE_1 Receiver enabled. 0x1 RIE Receiver Interrupt Enable 21 1 read-write RIE_0 Hardware interrupts from RDRF disabled use polling. 0 RIE_1 Hardware interrupt requested when RDRF flag is 1. 0x1 RSRC Receiver Source Select 5 1 read-write RSRC_0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. 0 RSRC_1 Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. 0x1 RWU Receiver Wakeup Control 17 1 read-write RWU_0 Normal receiver operation. 0 RWU_1 LPUART receiver in standby waiting for wakeup condition. 0x1 SBK Send Break 16 1 read-write SBK_0 Normal transmitter operation. 0 SBK_1 Queue break character(s) to be sent. 0x1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write TCIE_0 Hardware interrupts from TC disabled use polling. 0 TCIE_1 Hardware interrupt requested when TC flag is 1. 0x1 TE Transmitter Enable 19 1 read-write TE_0 Transmitter disabled. 0 TE_1 Transmitter enabled. 0x1 TIE Transmit Interrupt Enable 23 1 read-write TIE_0 Hardware interrupts from TDRE disabled use polling. 0 TIE_1 Hardware interrupt requested when TDRE flag is 1. 0x1 TXDIR TXD Pin Direction in Single-Wire Mode 29 1 read-write TXDIR_0 TXD pin is an input in single-wire mode. 0 TXDIR_1 TXD pin is an output in single-wire mode. 0x1 TXINV Transmit Data Inversion 28 1 read-write TXINV_0 Transmit data not inverted. 0 TXINV_1 Transmit data inverted. 0x1 WAKE Receiver Wakeup Method Select 3 1 read-write WAKE_0 Configures RWU for idle-line wakeup. 0 WAKE_1 Configures RWU with address-mark wakeup. 0x1 DATA LPUART Data Register 0x1C 32 read-write n 0x0 0x0 FRETSC Frame Error / Transmit Special Character 13 1 read-write FRETSC_0 The dataword was received without a frame error on read, or transmit a normal character on write. 0 FRETSC_1 The dataword was received with a frame error, or transmit an idle or break character on transmit. 0x1 IDLINE Idle Line 11 1 read-only IDLINE_0 Receiver was not idle before receiving this character. 0 IDLINE_1 Receiver was idle before receiving this character. 0x1 NOISY NOISY 15 1 read-only NOISY_0 The dataword was received without noise. 0 NOISY_1 The data was received with noise. 0x1 PARITYE PARITYE 14 1 read-only PARITYE_0 The dataword was received without a parity error. 0 PARITYE_1 The dataword was received with a parity error. 0x1 R0T0 R0T0 0 1 read-write R1T1 R1T1 1 1 read-write R2T2 R2T2 2 1 read-write R3T3 R3T3 3 1 read-write R4T4 R4T4 4 1 read-write R5T5 R5T5 5 1 read-write R6T6 R6T6 6 1 read-write R7T7 R7T7 7 1 read-write R8T8 R8T8 8 1 read-write R9T9 R9T9 9 1 read-write RXEMPT Receive Buffer Empty 12 1 read-only RXEMPT_0 Receive buffer contains valid data. 0 RXEMPT_1 Receive buffer is empty, data returned on read is not valid. 0x1 FIFO LPUART FIFO Register 0x28 32 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only RXEMPT_0 Receive buffer is not empty. 0 RXEMPT_1 Receive buffer is empty. 0x1 RXFE Receive FIFO Enable 3 1 read-write RXFE_0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) 0 RXFE_1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. 0x1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only RXFIFOSIZE_0 Receive FIFO/Buffer depth = 1 dataword. 0 RXFIFOSIZE_1 Receive FIFO/Buffer depth = 4 datawords. 0x1 RXFIFOSIZE_2 Receive FIFO/Buffer depth = 8 datawords. 0x2 RXFIFOSIZE_3 Receive FIFO/Buffer depth = 16 datawords. 0x3 RXFIFOSIZE_4 Receive FIFO/Buffer depth = 32 datawords. 0x4 RXFIFOSIZE_5 Receive FIFO/Buffer depth = 64 datawords. 0x5 RXFIFOSIZE_6 Receive FIFO/Buffer depth = 128 datawords. 0x6 RXFIFOSIZE_7 Receive FIFO/Buffer depth = 256 datawords. 0x7 RXFLUSH Receive FIFO/Buffer Flush 14 1 write-only RXFLUSH_0 No flush operation occurs. 0 RXFLUSH_1 All data in the receive FIFO/buffer is cleared out. 0x1 RXIDEN Receiver Idle Empty Enable 10 3 read-write RXIDEN_0 Disable RDRF assertion due to partially filled FIFO when receiver is idle. 0 RXIDEN_1 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. 0x1 RXIDEN_2 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. 0x2 RXIDEN_3 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. 0x3 RXIDEN_4 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. 0x4 RXIDEN_5 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. 0x5 RXIDEN_6 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. 0x6 RXIDEN_7 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. 0x7 RXUF Receiver Buffer Underflow Flag 16 1 read-write oneToClear RXUF_0 No receive buffer underflow has occurred since the last time the flag was cleared. 0 RXUF_1 At least one receive buffer underflow has occurred since the last time the flag was cleared. 0x1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write RXUFE_0 RXUF flag does not generate an interrupt to the host. 0 RXUFE_1 RXUF flag generates an interrupt to the host. 0x1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only TXEMPT_0 Transmit buffer is not empty. 0 TXEMPT_1 Transmit buffer is empty. 0x1 TXFE Transmit FIFO Enable 7 1 read-write TXFE_0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). 0 TXFE_1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. 0x1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only TXFIFOSIZE_0 Transmit FIFO/Buffer depth = 1 dataword. 0 TXFIFOSIZE_1 Transmit FIFO/Buffer depth = 4 datawords. 0x1 TXFIFOSIZE_2 Transmit FIFO/Buffer depth = 8 datawords. 0x2 TXFIFOSIZE_3 Transmit FIFO/Buffer depth = 16 datawords. 0x3 TXFIFOSIZE_4 Transmit FIFO/Buffer depth = 32 datawords. 0x4 TXFIFOSIZE_5 Transmit FIFO/Buffer depth = 64 datawords. 0x5 TXFIFOSIZE_6 Transmit FIFO/Buffer depth = 128 datawords. 0x6 TXFIFOSIZE_7 Transmit FIFO/Buffer depth = 256 datawords 0x7 TXFLUSH Transmit FIFO/Buffer Flush 15 1 write-only TXFLUSH_0 No flush operation occurs. 0 TXFLUSH_1 All data in the transmit FIFO/Buffer is cleared out. 0x1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write oneToClear TXOF_0 No transmit buffer overflow has occurred since the last time the flag was cleared. 0 TXOF_1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. 0x1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write TXOFE_0 TXOF flag does not generate an interrupt to the host. 0 TXOFE_1 TXOF flag generates an interrupt to the host. 0x1 GLOBAL LPUART Global Register 0x8 32 read-write n 0x0 0x0 RST Software Reset 1 1 read-write RST_0 Module is not reset. 0 RST_1 Module is reset. 0x1 MATCH LPUART Match Address Register 0x20 32 read-write n 0x0 0x0 MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x24 32 read-write n 0x0 0x0 IREN Infrared enable 18 1 read-write IREN_0 IR disabled. 0 IREN_1 IR enabled. 0x1 RTSWATER Receive RTS Configuration 8 3 read-write RXRTSE Receiver request-to-send enable 3 1 read-write RXRTSE_0 The receiver has no effect on RTS. 0 RXRTSE_1 no description available 0x1 TNP Transmitter narrow pulse 16 2 read-write TNP_0 1/OSR. 0 TNP_1 2/OSR. 0x1 TNP_2 3/OSR. 0x2 TNP_3 4/OSR. 0x3 TXCTSC Transmit CTS Configuration 4 1 read-write TXCTSC_0 CTS input is sampled at the start of each character. 0 TXCTSC_1 CTS input is sampled when the transmitter is idle. 0x1 TXCTSE Transmitter clear-to-send enable 0 1 read-write TXCTSE_0 CTS has no effect on the transmitter. 0 TXCTSE_1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. 0x1 TXCTSSRC Transmit CTS Source 5 1 read-write TXCTSSRC_0 CTS input is the CTS_B pin. 0 TXCTSSRC_1 CTS input is the inverted Receiver Match result. 0x1 TXRTSE Transmitter request-to-send enable 1 1 read-write TXRTSE_0 The transmitter has no effect on RTS. 0 TXRTSE_1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. 0x1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write TXRTSPOL_0 Transmitter RTS is active low. 0 TXRTSPOL_1 Transmitter RTS is active high. 0x1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 RXFIFO Receive FIFO Size 8 8 read-only TXFIFO Transmit FIFO Size 0 8 read-only PINCFG LPUART Pin Configuration Register 0xC 32 read-write n 0x0 0x0 TRGSEL Trigger Select 0 2 read-write TRGSEL_0 Input trigger is disabled. 0 TRGSEL_1 Input trigger is used instead of RXD pin input. 0x1 TRGSEL_2 Input trigger is used instead of CTS_B pin input. 0x2 TRGSEL_3 Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. 0x3 STAT LPUART Status Register 0x14 32 read-write n 0x0 0x0 BRK13 Break Character Generation Length 26 1 read-write BRK13_0 Break character is transmitted with length of 9 to 13 bit times. 0 BRK13_1 Break character is transmitted with length of 12 to 15 bit times. 0x1 FE Framing Error Flag 17 1 read-write oneToClear FE_0 No framing error detected. This does not guarantee the framing is correct. 0 FE_1 Framing error. 0x1 IDLE Idle Line Flag 20 1 read-write oneToClear IDLE_0 No idle line detected. 0 IDLE_1 Idle line was detected. 0x1 LBKDE LIN Break Detection Enable 25 1 read-write LBKDE_0 LIN break detect is disabled, normal break character can be detected. 0 LBKDE_1 LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). 0x1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write oneToClear LBKDIF_0 No LIN break character has been detected. 0 LBKDIF_1 LIN break character has been detected. 0x1 MA1F Match 1 Flag 15 1 read-write oneToClear MA1F_0 Received data is not equal to MA1 0 MA1F_1 Received data is equal to MA1 0x1 MA2F Match 2 Flag 14 1 read-write oneToClear MA2F_0 Received data is not equal to MA2 0 MA2F_1 Received data is equal to MA2 0x1 MSBF MSB First 29 1 read-write MSBF_0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. 0 MSBF_1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. 0x1 NF Noise Flag 18 1 read-write oneToClear NF_0 No noise detected. 0 NF_1 Noise detected in the received character in LPUART_DATA. 0x1 OR Receiver Overrun Flag 19 1 read-write oneToClear OR_0 No overrun. 0 OR_1 Receive overrun (new LPUART data lost). 0x1 PF Parity Error Flag 16 1 read-write oneToClear PF_0 No parity error. 0 PF_1 Parity error. 0x1 RAF Receiver Active Flag 24 1 read-only RAF_0 LPUART receiver idle waiting for a start bit. 0 RAF_1 LPUART receiver active (RXD input not idle). 0x1 RDRF Receive Data Register Full Flag 21 1 read-only RDRF_0 Receive data buffer empty. 0 RDRF_1 Receive data buffer full. 0x1 RWUID Receive Wake Up Idle Detect 27 1 read-write RWUID_0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. 0 RWUID_1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. 0x1 RXEDGIF RXD Pin Active Edge Interrupt Flag 30 1 read-write oneToClear RXEDGIF_0 No active edge on the receive pin has occurred. 0 RXEDGIF_1 An active edge on the receive pin has occurred. 0x1 RXINV Receive Data Inversion 28 1 read-write RXINV_0 Receive data not inverted. 0 RXINV_1 Receive data inverted. 0x1 TC Transmission Complete Flag 22 1 read-only TC_0 Transmitter active (sending data, a preamble, or a break). 0 TC_1 Transmitter idle (transmission activity complete). 0x1 TDRE Transmit Data Register Empty Flag 23 1 read-only TDRE_0 Transmit data buffer full. 0 TDRE_1 Transmit data buffer empty. 0x1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Identification Number 0 16 read-only FEATURE_1 Standard feature set. 0x1 FEATURE_3 Standard feature set with MODEM/IrDA support. 0x3 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only WATER LPUART Watermark Register 0x2C 32 read-write n 0x0 0x0 RXCOUNT Receive Counter 24 4 read-only RXWATER Receive Watermark 16 3 read-write TXCOUNT Transmit Counter 8 4 read-only TXWATER Transmit Watermark 0 3 read-write LPUART1 LPUART LPUART1 0x0 0x0 0x30 registers n LPUART1 45 BAUD LPUART Baud Rate Register 0x10 32 read-write n 0x0 0x0 BOTHEDGE Both Edge Sampling 17 1 read-write BOTHEDGE_0 Receiver samples input data using the rising edge of the baud rate clock. 0 BOTHEDGE_1 Receiver samples input data using the rising and falling edge of the baud rate clock. 0x1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write LBKDIE_0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). 0 LBKDIE_1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. 0x1 M10 10-bit Mode select 29 1 read-write M10_0 Receiver and transmitter use 7-bit to 9-bit data characters. 0 M10_1 Receiver and transmitter use 10-bit data characters. 0x1 MAEN1 Match Address Mode Enable 1 31 1 read-write MAEN1_0 Normal operation. 0 MAEN1_1 Enables automatic address matching or data matching mode for MATCH[MA1]. 0x1 MAEN2 Match Address Mode Enable 2 30 1 read-write MAEN2_0 Normal operation. 0 MAEN2_1 Enables automatic address matching or data matching mode for MATCH[MA2]. 0x1 MATCFG Match Configuration 18 2 read-write MATCFG_0 Address Match Wakeup 0 MATCFG_1 Idle Match Wakeup 0x1 MATCFG_2 Match On and Match Off 0x2 MATCFG_3 no description available 0x3 OSR Oversampling Ratio 24 5 read-write OSR_0 Writing 0 to this field will result in an oversampling ratio of 16 0 OSR_16 Oversampling ratio of 17. 0x10 OSR_17 Oversampling ratio of 18. 0x11 OSR_18 Oversampling ratio of 19. 0x12 OSR_19 Oversampling ratio of 20. 0x13 OSR_20 Oversampling ratio of 21. 0x14 OSR_21 Oversampling ratio of 22. 0x15 OSR_22 Oversampling ratio of 23. 0x16 OSR_23 Oversampling ratio of 24. 0x17 OSR_24 Oversampling ratio of 25. 0x18 OSR_25 Oversampling ratio of 26. 0x19 OSR_26 Oversampling ratio of 27. 0x1A OSR_27 Oversampling ratio of 28. 0x1B OSR_28 Oversampling ratio of 29. 0x1C OSR_29 Oversampling ratio of 30. 0x1D OSR_30 Oversampling ratio of 31. 0x1E OSR_31 Oversampling ratio of 32. 0x1F OSR_3 Oversampling ratio of 4, requires BOTHEDGE to be set. 0x3 OSR_4 Oversampling ratio of 5, requires BOTHEDGE to be set. 0x4 OSR_5 Oversampling ratio of 6, requires BOTHEDGE to be set. 0x5 OSR_6 Oversampling ratio of 7, requires BOTHEDGE to be set. 0x6 OSR_7 Oversampling ratio of 8. 0x7 OSR_8 Oversampling ratio of 9. 0x8 OSR_9 Oversampling ratio of 10. 0x9 OSR_10 Oversampling ratio of 11. 0xA OSR_11 Oversampling ratio of 12. 0xB OSR_12 Oversampling ratio of 13. 0xC OSR_13 Oversampling ratio of 14. 0xD OSR_14 Oversampling ratio of 15. 0xE OSR_15 Oversampling ratio of 16. 0xF RDMAE Receiver Full DMA Enable 21 1 read-write RDMAE_0 DMA request disabled. 0 RDMAE_1 DMA request enabled. 0x1 RESYNCDIS Resynchronization Disable 16 1 read-write RESYNCDIS_0 Resynchronization during received data word is supported 0 RESYNCDIS_1 Resynchronization during received data word is disabled 0x1 RIDMAE Receiver Idle DMA Enable 20 1 read-write RIDMAE_0 DMA request disabled. 0 RIDMAE_1 DMA request enabled. 0x1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write RXEDGIE_0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled. 0 RXEDGIE_1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. 0x1 SBNS Stop Bit Number Select 13 1 read-write SBNS_0 One stop bit. 0 SBNS_1 Two stop bits. 0x1 SBR Baud Rate Modulo Divisor. 0 13 read-write TDMAE Transmitter DMA Enable 23 1 read-write TDMAE_0 DMA request disabled. 0 TDMAE_1 DMA request enabled. 0x1 CTRL LPUART Control Register 0x18 32 read-write n 0x0 0x0 DOZEEN Doze Enable 6 1 read-write DOZEEN_0 LPUART is enabled in Doze mode. 0 DOZEEN_1 LPUART is disabled in Doze mode. 0x1 FEIE Framing Error Interrupt Enable 25 1 read-write FEIE_0 FE interrupts disabled use polling. 0 FEIE_1 Hardware interrupt requested when FE is set. 0x1 IDLECFG Idle Configuration 8 3 read-write IDLECFG_0 1 idle character 0 IDLECFG_1 2 idle characters 0x1 IDLECFG_2 4 idle characters 0x2 IDLECFG_3 8 idle characters 0x3 IDLECFG_4 16 idle characters 0x4 IDLECFG_5 32 idle characters 0x5 IDLECFG_6 64 idle characters 0x6 IDLECFG_7 128 idle characters 0x7 ILIE Idle Line Interrupt Enable 20 1 read-write ILIE_0 Hardware interrupts from IDLE disabled use polling. 0 ILIE_1 Hardware interrupt requested when IDLE flag is 1. 0x1 ILT Idle Line Type Select 2 1 read-write ILT_0 Idle character bit count starts after start bit. 0 ILT_1 Idle character bit count starts after stop bit. 0x1 LOOPS Loop Mode Select 7 1 read-write LOOPS_0 Normal operation - RXD and TXD use separate pins. 0 LOOPS_1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). 0x1 M 9-Bit or 8-Bit Mode Select 4 1 read-write M_0 Receiver and transmitter use 8-bit data characters. 0 M_1 Receiver and transmitter use 9-bit data characters. 0x1 M7 7-Bit Mode Select 11 1 read-write M7_0 Receiver and transmitter use 8-bit to 10-bit data characters. 0 M7_1 Receiver and transmitter use 7-bit data characters. 0x1 MA1IE Match 1 Interrupt Enable 15 1 read-write MA1IE_0 MA1F interrupt disabled 0 MA1IE_1 MA1F interrupt enabled 0x1 MA2IE Match 2 Interrupt Enable 14 1 read-write MA2IE_0 MA2F interrupt disabled 0 MA2IE_1 MA2F interrupt enabled 0x1 NEIE Noise Error Interrupt Enable 26 1 read-write NEIE_0 NF interrupts disabled use polling. 0 NEIE_1 Hardware interrupt requested when NF is set. 0x1 ORIE Overrun Interrupt Enable 27 1 read-write ORIE_0 OR interrupts disabled use polling. 0 ORIE_1 Hardware interrupt requested when OR is set. 0x1 PE Parity Enable 1 1 read-write PE_0 No hardware parity generation or checking. 0 PE_1 Parity enabled. 0x1 PEIE Parity Error Interrupt Enable 24 1 read-write PEIE_0 PF interrupts disabled use polling). 0 PEIE_1 Hardware interrupt requested when PF is set. 0x1 PT Parity Type 0 1 read-write PT_0 Even parity. 0 PT_1 Odd parity. 0x1 R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write RE Receiver Enable 18 1 read-write RE_0 Receiver disabled. 0 RE_1 Receiver enabled. 0x1 RIE Receiver Interrupt Enable 21 1 read-write RIE_0 Hardware interrupts from RDRF disabled use polling. 0 RIE_1 Hardware interrupt requested when RDRF flag is 1. 0x1 RSRC Receiver Source Select 5 1 read-write RSRC_0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. 0 RSRC_1 Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. 0x1 RWU Receiver Wakeup Control 17 1 read-write RWU_0 Normal receiver operation. 0 RWU_1 LPUART receiver in standby waiting for wakeup condition. 0x1 SBK Send Break 16 1 read-write SBK_0 Normal transmitter operation. 0 SBK_1 Queue break character(s) to be sent. 0x1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write TCIE_0 Hardware interrupts from TC disabled use polling. 0 TCIE_1 Hardware interrupt requested when TC flag is 1. 0x1 TE Transmitter Enable 19 1 read-write TE_0 Transmitter disabled. 0 TE_1 Transmitter enabled. 0x1 TIE Transmit Interrupt Enable 23 1 read-write TIE_0 Hardware interrupts from TDRE disabled use polling. 0 TIE_1 Hardware interrupt requested when TDRE flag is 1. 0x1 TXDIR TXD Pin Direction in Single-Wire Mode 29 1 read-write TXDIR_0 TXD pin is an input in single-wire mode. 0 TXDIR_1 TXD pin is an output in single-wire mode. 0x1 TXINV Transmit Data Inversion 28 1 read-write TXINV_0 Transmit data not inverted. 0 TXINV_1 Transmit data inverted. 0x1 WAKE Receiver Wakeup Method Select 3 1 read-write WAKE_0 Configures RWU for idle-line wakeup. 0 WAKE_1 Configures RWU with address-mark wakeup. 0x1 DATA LPUART Data Register 0x1C 32 read-write n 0x0 0x0 FRETSC Frame Error / Transmit Special Character 13 1 read-write FRETSC_0 The dataword was received without a frame error on read, or transmit a normal character on write. 0 FRETSC_1 The dataword was received with a frame error, or transmit an idle or break character on transmit. 0x1 IDLINE Idle Line 11 1 read-only IDLINE_0 Receiver was not idle before receiving this character. 0 IDLINE_1 Receiver was idle before receiving this character. 0x1 NOISY NOISY 15 1 read-only NOISY_0 The dataword was received without noise. 0 NOISY_1 The data was received with noise. 0x1 PARITYE PARITYE 14 1 read-only PARITYE_0 The dataword was received without a parity error. 0 PARITYE_1 The dataword was received with a parity error. 0x1 R0T0 R0T0 0 1 read-write R1T1 R1T1 1 1 read-write R2T2 R2T2 2 1 read-write R3T3 R3T3 3 1 read-write R4T4 R4T4 4 1 read-write R5T5 R5T5 5 1 read-write R6T6 R6T6 6 1 read-write R7T7 R7T7 7 1 read-write R8T8 R8T8 8 1 read-write R9T9 R9T9 9 1 read-write RXEMPT Receive Buffer Empty 12 1 read-only RXEMPT_0 Receive buffer contains valid data. 0 RXEMPT_1 Receive buffer is empty, data returned on read is not valid. 0x1 FIFO LPUART FIFO Register 0x28 32 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only RXEMPT_0 Receive buffer is not empty. 0 RXEMPT_1 Receive buffer is empty. 0x1 RXFE Receive FIFO Enable 3 1 read-write RXFE_0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) 0 RXFE_1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. 0x1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only RXFIFOSIZE_0 Receive FIFO/Buffer depth = 1 dataword. 0 RXFIFOSIZE_1 Receive FIFO/Buffer depth = 4 datawords. 0x1 RXFIFOSIZE_2 Receive FIFO/Buffer depth = 8 datawords. 0x2 RXFIFOSIZE_3 Receive FIFO/Buffer depth = 16 datawords. 0x3 RXFIFOSIZE_4 Receive FIFO/Buffer depth = 32 datawords. 0x4 RXFIFOSIZE_5 Receive FIFO/Buffer depth = 64 datawords. 0x5 RXFIFOSIZE_6 Receive FIFO/Buffer depth = 128 datawords. 0x6 RXFIFOSIZE_7 Receive FIFO/Buffer depth = 256 datawords. 0x7 RXFLUSH Receive FIFO/Buffer Flush 14 1 write-only RXFLUSH_0 No flush operation occurs. 0 RXFLUSH_1 All data in the receive FIFO/buffer is cleared out. 0x1 RXIDEN Receiver Idle Empty Enable 10 3 read-write RXIDEN_0 Disable RDRF assertion due to partially filled FIFO when receiver is idle. 0 RXIDEN_1 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. 0x1 RXIDEN_2 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. 0x2 RXIDEN_3 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. 0x3 RXIDEN_4 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. 0x4 RXIDEN_5 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. 0x5 RXIDEN_6 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. 0x6 RXIDEN_7 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. 0x7 RXUF Receiver Buffer Underflow Flag 16 1 read-write oneToClear RXUF_0 No receive buffer underflow has occurred since the last time the flag was cleared. 0 RXUF_1 At least one receive buffer underflow has occurred since the last time the flag was cleared. 0x1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write RXUFE_0 RXUF flag does not generate an interrupt to the host. 0 RXUFE_1 RXUF flag generates an interrupt to the host. 0x1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only TXEMPT_0 Transmit buffer is not empty. 0 TXEMPT_1 Transmit buffer is empty. 0x1 TXFE Transmit FIFO Enable 7 1 read-write TXFE_0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). 0 TXFE_1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. 0x1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only TXFIFOSIZE_0 Transmit FIFO/Buffer depth = 1 dataword. 0 TXFIFOSIZE_1 Transmit FIFO/Buffer depth = 4 datawords. 0x1 TXFIFOSIZE_2 Transmit FIFO/Buffer depth = 8 datawords. 0x2 TXFIFOSIZE_3 Transmit FIFO/Buffer depth = 16 datawords. 0x3 TXFIFOSIZE_4 Transmit FIFO/Buffer depth = 32 datawords. 0x4 TXFIFOSIZE_5 Transmit FIFO/Buffer depth = 64 datawords. 0x5 TXFIFOSIZE_6 Transmit FIFO/Buffer depth = 128 datawords. 0x6 TXFIFOSIZE_7 Transmit FIFO/Buffer depth = 256 datawords 0x7 TXFLUSH Transmit FIFO/Buffer Flush 15 1 write-only TXFLUSH_0 No flush operation occurs. 0 TXFLUSH_1 All data in the transmit FIFO/Buffer is cleared out. 0x1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write oneToClear TXOF_0 No transmit buffer overflow has occurred since the last time the flag was cleared. 0 TXOF_1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. 0x1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write TXOFE_0 TXOF flag does not generate an interrupt to the host. 0 TXOFE_1 TXOF flag generates an interrupt to the host. 0x1 GLOBAL LPUART Global Register 0x8 32 read-write n 0x0 0x0 RST Software Reset 1 1 read-write RST_0 Module is not reset. 0 RST_1 Module is reset. 0x1 MATCH LPUART Match Address Register 0x20 32 read-write n 0x0 0x0 MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x24 32 read-write n 0x0 0x0 IREN Infrared enable 18 1 read-write IREN_0 IR disabled. 0 IREN_1 IR enabled. 0x1 RTSWATER Receive RTS Configuration 8 3 read-write RXRTSE Receiver request-to-send enable 3 1 read-write RXRTSE_0 The receiver has no effect on RTS. 0 RXRTSE_1 no description available 0x1 TNP Transmitter narrow pulse 16 2 read-write TNP_0 1/OSR. 0 TNP_1 2/OSR. 0x1 TNP_2 3/OSR. 0x2 TNP_3 4/OSR. 0x3 TXCTSC Transmit CTS Configuration 4 1 read-write TXCTSC_0 CTS input is sampled at the start of each character. 0 TXCTSC_1 CTS input is sampled when the transmitter is idle. 0x1 TXCTSE Transmitter clear-to-send enable 0 1 read-write TXCTSE_0 CTS has no effect on the transmitter. 0 TXCTSE_1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. 0x1 TXCTSSRC Transmit CTS Source 5 1 read-write TXCTSSRC_0 CTS input is the CTS_B pin. 0 TXCTSSRC_1 CTS input is the inverted Receiver Match result. 0x1 TXRTSE Transmitter request-to-send enable 1 1 read-write TXRTSE_0 The transmitter has no effect on RTS. 0 TXRTSE_1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. 0x1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write TXRTSPOL_0 Transmitter RTS is active low. 0 TXRTSPOL_1 Transmitter RTS is active high. 0x1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 RXFIFO Receive FIFO Size 8 8 read-only TXFIFO Transmit FIFO Size 0 8 read-only PINCFG LPUART Pin Configuration Register 0xC 32 read-write n 0x0 0x0 TRGSEL Trigger Select 0 2 read-write TRGSEL_0 Input trigger is disabled. 0 TRGSEL_1 Input trigger is used instead of RXD pin input. 0x1 TRGSEL_2 Input trigger is used instead of CTS_B pin input. 0x2 TRGSEL_3 Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. 0x3 STAT LPUART Status Register 0x14 32 read-write n 0x0 0x0 BRK13 Break Character Generation Length 26 1 read-write BRK13_0 Break character is transmitted with length of 9 to 13 bit times. 0 BRK13_1 Break character is transmitted with length of 12 to 15 bit times. 0x1 FE Framing Error Flag 17 1 read-write oneToClear FE_0 No framing error detected. This does not guarantee the framing is correct. 0 FE_1 Framing error. 0x1 IDLE Idle Line Flag 20 1 read-write oneToClear IDLE_0 No idle line detected. 0 IDLE_1 Idle line was detected. 0x1 LBKDE LIN Break Detection Enable 25 1 read-write LBKDE_0 LIN break detect is disabled, normal break character can be detected. 0 LBKDE_1 LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). 0x1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write oneToClear LBKDIF_0 No LIN break character has been detected. 0 LBKDIF_1 LIN break character has been detected. 0x1 MA1F Match 1 Flag 15 1 read-write oneToClear MA1F_0 Received data is not equal to MA1 0 MA1F_1 Received data is equal to MA1 0x1 MA2F Match 2 Flag 14 1 read-write oneToClear MA2F_0 Received data is not equal to MA2 0 MA2F_1 Received data is equal to MA2 0x1 MSBF MSB First 29 1 read-write MSBF_0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. 0 MSBF_1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. 0x1 NF Noise Flag 18 1 read-write oneToClear NF_0 No noise detected. 0 NF_1 Noise detected in the received character in LPUART_DATA. 0x1 OR Receiver Overrun Flag 19 1 read-write oneToClear OR_0 No overrun. 0 OR_1 Receive overrun (new LPUART data lost). 0x1 PF Parity Error Flag 16 1 read-write oneToClear PF_0 No parity error. 0 PF_1 Parity error. 0x1 RAF Receiver Active Flag 24 1 read-only RAF_0 LPUART receiver idle waiting for a start bit. 0 RAF_1 LPUART receiver active (RXD input not idle). 0x1 RDRF Receive Data Register Full Flag 21 1 read-only RDRF_0 Receive data buffer empty. 0 RDRF_1 Receive data buffer full. 0x1 RWUID Receive Wake Up Idle Detect 27 1 read-write RWUID_0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. 0 RWUID_1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. 0x1 RXEDGIF RXD Pin Active Edge Interrupt Flag 30 1 read-write oneToClear RXEDGIF_0 No active edge on the receive pin has occurred. 0 RXEDGIF_1 An active edge on the receive pin has occurred. 0x1 RXINV Receive Data Inversion 28 1 read-write RXINV_0 Receive data not inverted. 0 RXINV_1 Receive data inverted. 0x1 TC Transmission Complete Flag 22 1 read-only TC_0 Transmitter active (sending data, a preamble, or a break). 0 TC_1 Transmitter idle (transmission activity complete). 0x1 TDRE Transmit Data Register Empty Flag 23 1 read-only TDRE_0 Transmit data buffer full. 0 TDRE_1 Transmit data buffer empty. 0x1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Identification Number 0 16 read-only FEATURE_1 Standard feature set. 0x1 FEATURE_3 Standard feature set with MODEM/IrDA support. 0x3 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only WATER LPUART Watermark Register 0x2C 32 read-write n 0x0 0x0 RXCOUNT Receive Counter 24 4 read-only RXWATER Receive Watermark 16 3 read-write TXCOUNT Transmit Counter 8 4 read-only TXWATER Transmit Watermark 0 3 read-write LPUART2 LPUART LPUART2 0x0 0x0 0x30 registers n LPUART2 46 BAUD LPUART Baud Rate Register 0x10 32 read-write n 0x0 0x0 BOTHEDGE Both Edge Sampling 17 1 read-write BOTHEDGE_0 Receiver samples input data using the rising edge of the baud rate clock. 0 BOTHEDGE_1 Receiver samples input data using the rising and falling edge of the baud rate clock. 0x1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write LBKDIE_0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). 0 LBKDIE_1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. 0x1 M10 10-bit Mode select 29 1 read-write M10_0 Receiver and transmitter use 7-bit to 9-bit data characters. 0 M10_1 Receiver and transmitter use 10-bit data characters. 0x1 MAEN1 Match Address Mode Enable 1 31 1 read-write MAEN1_0 Normal operation. 0 MAEN1_1 Enables automatic address matching or data matching mode for MATCH[MA1]. 0x1 MAEN2 Match Address Mode Enable 2 30 1 read-write MAEN2_0 Normal operation. 0 MAEN2_1 Enables automatic address matching or data matching mode for MATCH[MA2]. 0x1 MATCFG Match Configuration 18 2 read-write MATCFG_0 Address Match Wakeup 0 MATCFG_1 Idle Match Wakeup 0x1 MATCFG_2 Match On and Match Off 0x2 MATCFG_3 no description available 0x3 OSR Oversampling Ratio 24 5 read-write OSR_0 Writing 0 to this field will result in an oversampling ratio of 16 0 OSR_16 Oversampling ratio of 17. 0x10 OSR_17 Oversampling ratio of 18. 0x11 OSR_18 Oversampling ratio of 19. 0x12 OSR_19 Oversampling ratio of 20. 0x13 OSR_20 Oversampling ratio of 21. 0x14 OSR_21 Oversampling ratio of 22. 0x15 OSR_22 Oversampling ratio of 23. 0x16 OSR_23 Oversampling ratio of 24. 0x17 OSR_24 Oversampling ratio of 25. 0x18 OSR_25 Oversampling ratio of 26. 0x19 OSR_26 Oversampling ratio of 27. 0x1A OSR_27 Oversampling ratio of 28. 0x1B OSR_28 Oversampling ratio of 29. 0x1C OSR_29 Oversampling ratio of 30. 0x1D OSR_30 Oversampling ratio of 31. 0x1E OSR_31 Oversampling ratio of 32. 0x1F OSR_3 Oversampling ratio of 4, requires BOTHEDGE to be set. 0x3 OSR_4 Oversampling ratio of 5, requires BOTHEDGE to be set. 0x4 OSR_5 Oversampling ratio of 6, requires BOTHEDGE to be set. 0x5 OSR_6 Oversampling ratio of 7, requires BOTHEDGE to be set. 0x6 OSR_7 Oversampling ratio of 8. 0x7 OSR_8 Oversampling ratio of 9. 0x8 OSR_9 Oversampling ratio of 10. 0x9 OSR_10 Oversampling ratio of 11. 0xA OSR_11 Oversampling ratio of 12. 0xB OSR_12 Oversampling ratio of 13. 0xC OSR_13 Oversampling ratio of 14. 0xD OSR_14 Oversampling ratio of 15. 0xE OSR_15 Oversampling ratio of 16. 0xF RDMAE Receiver Full DMA Enable 21 1 read-write RDMAE_0 DMA request disabled. 0 RDMAE_1 DMA request enabled. 0x1 RESYNCDIS Resynchronization Disable 16 1 read-write RESYNCDIS_0 Resynchronization during received data word is supported 0 RESYNCDIS_1 Resynchronization during received data word is disabled 0x1 RIDMAE Receiver Idle DMA Enable 20 1 read-write RIDMAE_0 DMA request disabled. 0 RIDMAE_1 DMA request enabled. 0x1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write RXEDGIE_0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled. 0 RXEDGIE_1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. 0x1 SBNS Stop Bit Number Select 13 1 read-write SBNS_0 One stop bit. 0 SBNS_1 Two stop bits. 0x1 SBR Baud Rate Modulo Divisor. 0 13 read-write TDMAE Transmitter DMA Enable 23 1 read-write TDMAE_0 DMA request disabled. 0 TDMAE_1 DMA request enabled. 0x1 CTRL LPUART Control Register 0x18 32 read-write n 0x0 0x0 DOZEEN Doze Enable 6 1 read-write DOZEEN_0 LPUART is enabled in Doze mode. 0 DOZEEN_1 LPUART is disabled in Doze mode. 0x1 FEIE Framing Error Interrupt Enable 25 1 read-write FEIE_0 FE interrupts disabled use polling. 0 FEIE_1 Hardware interrupt requested when FE is set. 0x1 IDLECFG Idle Configuration 8 3 read-write IDLECFG_0 1 idle character 0 IDLECFG_1 2 idle characters 0x1 IDLECFG_2 4 idle characters 0x2 IDLECFG_3 8 idle characters 0x3 IDLECFG_4 16 idle characters 0x4 IDLECFG_5 32 idle characters 0x5 IDLECFG_6 64 idle characters 0x6 IDLECFG_7 128 idle characters 0x7 ILIE Idle Line Interrupt Enable 20 1 read-write ILIE_0 Hardware interrupts from IDLE disabled use polling. 0 ILIE_1 Hardware interrupt requested when IDLE flag is 1. 0x1 ILT Idle Line Type Select 2 1 read-write ILT_0 Idle character bit count starts after start bit. 0 ILT_1 Idle character bit count starts after stop bit. 0x1 LOOPS Loop Mode Select 7 1 read-write LOOPS_0 Normal operation - RXD and TXD use separate pins. 0 LOOPS_1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). 0x1 M 9-Bit or 8-Bit Mode Select 4 1 read-write M_0 Receiver and transmitter use 8-bit data characters. 0 M_1 Receiver and transmitter use 9-bit data characters. 0x1 M7 7-Bit Mode Select 11 1 read-write M7_0 Receiver and transmitter use 8-bit to 10-bit data characters. 0 M7_1 Receiver and transmitter use 7-bit data characters. 0x1 MA1IE Match 1 Interrupt Enable 15 1 read-write MA1IE_0 MA1F interrupt disabled 0 MA1IE_1 MA1F interrupt enabled 0x1 MA2IE Match 2 Interrupt Enable 14 1 read-write MA2IE_0 MA2F interrupt disabled 0 MA2IE_1 MA2F interrupt enabled 0x1 NEIE Noise Error Interrupt Enable 26 1 read-write NEIE_0 NF interrupts disabled use polling. 0 NEIE_1 Hardware interrupt requested when NF is set. 0x1 ORIE Overrun Interrupt Enable 27 1 read-write ORIE_0 OR interrupts disabled use polling. 0 ORIE_1 Hardware interrupt requested when OR is set. 0x1 PE Parity Enable 1 1 read-write PE_0 No hardware parity generation or checking. 0 PE_1 Parity enabled. 0x1 PEIE Parity Error Interrupt Enable 24 1 read-write PEIE_0 PF interrupts disabled use polling). 0 PEIE_1 Hardware interrupt requested when PF is set. 0x1 PT Parity Type 0 1 read-write PT_0 Even parity. 0 PT_1 Odd parity. 0x1 R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write RE Receiver Enable 18 1 read-write RE_0 Receiver disabled. 0 RE_1 Receiver enabled. 0x1 RIE Receiver Interrupt Enable 21 1 read-write RIE_0 Hardware interrupts from RDRF disabled use polling. 0 RIE_1 Hardware interrupt requested when RDRF flag is 1. 0x1 RSRC Receiver Source Select 5 1 read-write RSRC_0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. 0 RSRC_1 Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. 0x1 RWU Receiver Wakeup Control 17 1 read-write RWU_0 Normal receiver operation. 0 RWU_1 LPUART receiver in standby waiting for wakeup condition. 0x1 SBK Send Break 16 1 read-write SBK_0 Normal transmitter operation. 0 SBK_1 Queue break character(s) to be sent. 0x1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write TCIE_0 Hardware interrupts from TC disabled use polling. 0 TCIE_1 Hardware interrupt requested when TC flag is 1. 0x1 TE Transmitter Enable 19 1 read-write TE_0 Transmitter disabled. 0 TE_1 Transmitter enabled. 0x1 TIE Transmit Interrupt Enable 23 1 read-write TIE_0 Hardware interrupts from TDRE disabled use polling. 0 TIE_1 Hardware interrupt requested when TDRE flag is 1. 0x1 TXDIR TXD Pin Direction in Single-Wire Mode 29 1 read-write TXDIR_0 TXD pin is an input in single-wire mode. 0 TXDIR_1 TXD pin is an output in single-wire mode. 0x1 TXINV Transmit Data Inversion 28 1 read-write TXINV_0 Transmit data not inverted. 0 TXINV_1 Transmit data inverted. 0x1 WAKE Receiver Wakeup Method Select 3 1 read-write WAKE_0 Configures RWU for idle-line wakeup. 0 WAKE_1 Configures RWU with address-mark wakeup. 0x1 DATA LPUART Data Register 0x1C 32 read-write n 0x0 0x0 FRETSC Frame Error / Transmit Special Character 13 1 read-write FRETSC_0 The dataword was received without a frame error on read, or transmit a normal character on write. 0 FRETSC_1 The dataword was received with a frame error, or transmit an idle or break character on transmit. 0x1 IDLINE Idle Line 11 1 read-only IDLINE_0 Receiver was not idle before receiving this character. 0 IDLINE_1 Receiver was idle before receiving this character. 0x1 NOISY NOISY 15 1 read-only NOISY_0 The dataword was received without noise. 0 NOISY_1 The data was received with noise. 0x1 PARITYE PARITYE 14 1 read-only PARITYE_0 The dataword was received without a parity error. 0 PARITYE_1 The dataword was received with a parity error. 0x1 R0T0 R0T0 0 1 read-write R1T1 R1T1 1 1 read-write R2T2 R2T2 2 1 read-write R3T3 R3T3 3 1 read-write R4T4 R4T4 4 1 read-write R5T5 R5T5 5 1 read-write R6T6 R6T6 6 1 read-write R7T7 R7T7 7 1 read-write R8T8 R8T8 8 1 read-write R9T9 R9T9 9 1 read-write RXEMPT Receive Buffer Empty 12 1 read-only RXEMPT_0 Receive buffer contains valid data. 0 RXEMPT_1 Receive buffer is empty, data returned on read is not valid. 0x1 FIFO LPUART FIFO Register 0x28 32 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only RXEMPT_0 Receive buffer is not empty. 0 RXEMPT_1 Receive buffer is empty. 0x1 RXFE Receive FIFO Enable 3 1 read-write RXFE_0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) 0 RXFE_1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. 0x1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only RXFIFOSIZE_0 Receive FIFO/Buffer depth = 1 dataword. 0 RXFIFOSIZE_1 Receive FIFO/Buffer depth = 4 datawords. 0x1 RXFIFOSIZE_2 Receive FIFO/Buffer depth = 8 datawords. 0x2 RXFIFOSIZE_3 Receive FIFO/Buffer depth = 16 datawords. 0x3 RXFIFOSIZE_4 Receive FIFO/Buffer depth = 32 datawords. 0x4 RXFIFOSIZE_5 Receive FIFO/Buffer depth = 64 datawords. 0x5 RXFIFOSIZE_6 Receive FIFO/Buffer depth = 128 datawords. 0x6 RXFIFOSIZE_7 Receive FIFO/Buffer depth = 256 datawords. 0x7 RXFLUSH Receive FIFO/Buffer Flush 14 1 write-only RXFLUSH_0 No flush operation occurs. 0 RXFLUSH_1 All data in the receive FIFO/buffer is cleared out. 0x1 RXIDEN Receiver Idle Empty Enable 10 3 read-write RXIDEN_0 Disable RDRF assertion due to partially filled FIFO when receiver is idle. 0 RXIDEN_1 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. 0x1 RXIDEN_2 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. 0x2 RXIDEN_3 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. 0x3 RXIDEN_4 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. 0x4 RXIDEN_5 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. 0x5 RXIDEN_6 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. 0x6 RXIDEN_7 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. 0x7 RXUF Receiver Buffer Underflow Flag 16 1 read-write oneToClear RXUF_0 No receive buffer underflow has occurred since the last time the flag was cleared. 0 RXUF_1 At least one receive buffer underflow has occurred since the last time the flag was cleared. 0x1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write RXUFE_0 RXUF flag does not generate an interrupt to the host. 0 RXUFE_1 RXUF flag generates an interrupt to the host. 0x1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only TXEMPT_0 Transmit buffer is not empty. 0 TXEMPT_1 Transmit buffer is empty. 0x1 TXFE Transmit FIFO Enable 7 1 read-write TXFE_0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). 0 TXFE_1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. 0x1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only TXFIFOSIZE_0 Transmit FIFO/Buffer depth = 1 dataword. 0 TXFIFOSIZE_1 Transmit FIFO/Buffer depth = 4 datawords. 0x1 TXFIFOSIZE_2 Transmit FIFO/Buffer depth = 8 datawords. 0x2 TXFIFOSIZE_3 Transmit FIFO/Buffer depth = 16 datawords. 0x3 TXFIFOSIZE_4 Transmit FIFO/Buffer depth = 32 datawords. 0x4 TXFIFOSIZE_5 Transmit FIFO/Buffer depth = 64 datawords. 0x5 TXFIFOSIZE_6 Transmit FIFO/Buffer depth = 128 datawords. 0x6 TXFIFOSIZE_7 Transmit FIFO/Buffer depth = 256 datawords 0x7 TXFLUSH Transmit FIFO/Buffer Flush 15 1 write-only TXFLUSH_0 No flush operation occurs. 0 TXFLUSH_1 All data in the transmit FIFO/Buffer is cleared out. 0x1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write oneToClear TXOF_0 No transmit buffer overflow has occurred since the last time the flag was cleared. 0 TXOF_1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. 0x1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write TXOFE_0 TXOF flag does not generate an interrupt to the host. 0 TXOFE_1 TXOF flag generates an interrupt to the host. 0x1 GLOBAL LPUART Global Register 0x8 32 read-write n 0x0 0x0 RST Software Reset 1 1 read-write RST_0 Module is not reset. 0 RST_1 Module is reset. 0x1 MATCH LPUART Match Address Register 0x20 32 read-write n 0x0 0x0 MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x24 32 read-write n 0x0 0x0 IREN Infrared enable 18 1 read-write IREN_0 IR disabled. 0 IREN_1 IR enabled. 0x1 RTSWATER Receive RTS Configuration 8 3 read-write RXRTSE Receiver request-to-send enable 3 1 read-write RXRTSE_0 The receiver has no effect on RTS. 0 RXRTSE_1 no description available 0x1 TNP Transmitter narrow pulse 16 2 read-write TNP_0 1/OSR. 0 TNP_1 2/OSR. 0x1 TNP_2 3/OSR. 0x2 TNP_3 4/OSR. 0x3 TXCTSC Transmit CTS Configuration 4 1 read-write TXCTSC_0 CTS input is sampled at the start of each character. 0 TXCTSC_1 CTS input is sampled when the transmitter is idle. 0x1 TXCTSE Transmitter clear-to-send enable 0 1 read-write TXCTSE_0 CTS has no effect on the transmitter. 0 TXCTSE_1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. 0x1 TXCTSSRC Transmit CTS Source 5 1 read-write TXCTSSRC_0 CTS input is the CTS_B pin. 0 TXCTSSRC_1 CTS input is the inverted Receiver Match result. 0x1 TXRTSE Transmitter request-to-send enable 1 1 read-write TXRTSE_0 The transmitter has no effect on RTS. 0 TXRTSE_1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. 0x1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write TXRTSPOL_0 Transmitter RTS is active low. 0 TXRTSPOL_1 Transmitter RTS is active high. 0x1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 RXFIFO Receive FIFO Size 8 8 read-only TXFIFO Transmit FIFO Size 0 8 read-only PINCFG LPUART Pin Configuration Register 0xC 32 read-write n 0x0 0x0 TRGSEL Trigger Select 0 2 read-write TRGSEL_0 Input trigger is disabled. 0 TRGSEL_1 Input trigger is used instead of RXD pin input. 0x1 TRGSEL_2 Input trigger is used instead of CTS_B pin input. 0x2 TRGSEL_3 Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. 0x3 STAT LPUART Status Register 0x14 32 read-write n 0x0 0x0 BRK13 Break Character Generation Length 26 1 read-write BRK13_0 Break character is transmitted with length of 9 to 13 bit times. 0 BRK13_1 Break character is transmitted with length of 12 to 15 bit times. 0x1 FE Framing Error Flag 17 1 read-write oneToClear FE_0 No framing error detected. This does not guarantee the framing is correct. 0 FE_1 Framing error. 0x1 IDLE Idle Line Flag 20 1 read-write oneToClear IDLE_0 No idle line detected. 0 IDLE_1 Idle line was detected. 0x1 LBKDE LIN Break Detection Enable 25 1 read-write LBKDE_0 LIN break detect is disabled, normal break character can be detected. 0 LBKDE_1 LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). 0x1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write oneToClear LBKDIF_0 No LIN break character has been detected. 0 LBKDIF_1 LIN break character has been detected. 0x1 MA1F Match 1 Flag 15 1 read-write oneToClear MA1F_0 Received data is not equal to MA1 0 MA1F_1 Received data is equal to MA1 0x1 MA2F Match 2 Flag 14 1 read-write oneToClear MA2F_0 Received data is not equal to MA2 0 MA2F_1 Received data is equal to MA2 0x1 MSBF MSB First 29 1 read-write MSBF_0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. 0 MSBF_1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. 0x1 NF Noise Flag 18 1 read-write oneToClear NF_0 No noise detected. 0 NF_1 Noise detected in the received character in LPUART_DATA. 0x1 OR Receiver Overrun Flag 19 1 read-write oneToClear OR_0 No overrun. 0 OR_1 Receive overrun (new LPUART data lost). 0x1 PF Parity Error Flag 16 1 read-write oneToClear PF_0 No parity error. 0 PF_1 Parity error. 0x1 RAF Receiver Active Flag 24 1 read-only RAF_0 LPUART receiver idle waiting for a start bit. 0 RAF_1 LPUART receiver active (RXD input not idle). 0x1 RDRF Receive Data Register Full Flag 21 1 read-only RDRF_0 Receive data buffer empty. 0 RDRF_1 Receive data buffer full. 0x1 RWUID Receive Wake Up Idle Detect 27 1 read-write RWUID_0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. 0 RWUID_1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. 0x1 RXEDGIF RXD Pin Active Edge Interrupt Flag 30 1 read-write oneToClear RXEDGIF_0 No active edge on the receive pin has occurred. 0 RXEDGIF_1 An active edge on the receive pin has occurred. 0x1 RXINV Receive Data Inversion 28 1 read-write RXINV_0 Receive data not inverted. 0 RXINV_1 Receive data inverted. 0x1 TC Transmission Complete Flag 22 1 read-only TC_0 Transmitter active (sending data, a preamble, or a break). 0 TC_1 Transmitter idle (transmission activity complete). 0x1 TDRE Transmit Data Register Empty Flag 23 1 read-only TDRE_0 Transmit data buffer full. 0 TDRE_1 Transmit data buffer empty. 0x1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Identification Number 0 16 read-only FEATURE_1 Standard feature set. 0x1 FEATURE_3 Standard feature set with MODEM/IrDA support. 0x3 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only WATER LPUART Watermark Register 0x2C 32 read-write n 0x0 0x0 RXCOUNT Receive Counter 24 4 read-only RXWATER Receive Watermark 16 3 read-write TXCOUNT Transmit Counter 8 4 read-only TXWATER Transmit Watermark 0 3 read-write LPUART3 LPUART LPUART3 0x0 0x0 0x30 registers n LPUART3 63 BAUD LPUART Baud Rate Register 0x10 32 read-write n 0x0 0x0 BOTHEDGE Both Edge Sampling 17 1 read-write BOTHEDGE_0 Receiver samples input data using the rising edge of the baud rate clock. 0 BOTHEDGE_1 Receiver samples input data using the rising and falling edge of the baud rate clock. 0x1 LBKDIE LIN Break Detect Interrupt Enable 15 1 read-write LBKDIE_0 Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). 0 LBKDIE_1 Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. 0x1 M10 10-bit Mode select 29 1 read-write M10_0 Receiver and transmitter use 7-bit to 9-bit data characters. 0 M10_1 Receiver and transmitter use 10-bit data characters. 0x1 MAEN1 Match Address Mode Enable 1 31 1 read-write MAEN1_0 Normal operation. 0 MAEN1_1 Enables automatic address matching or data matching mode for MATCH[MA1]. 0x1 MAEN2 Match Address Mode Enable 2 30 1 read-write MAEN2_0 Normal operation. 0 MAEN2_1 Enables automatic address matching or data matching mode for MATCH[MA2]. 0x1 MATCFG Match Configuration 18 2 read-write MATCFG_0 Address Match Wakeup 0 MATCFG_1 Idle Match Wakeup 0x1 MATCFG_2 Match On and Match Off 0x2 MATCFG_3 no description available 0x3 OSR Oversampling Ratio 24 5 read-write OSR_0 Writing 0 to this field will result in an oversampling ratio of 16 0 OSR_16 Oversampling ratio of 17. 0x10 OSR_17 Oversampling ratio of 18. 0x11 OSR_18 Oversampling ratio of 19. 0x12 OSR_19 Oversampling ratio of 20. 0x13 OSR_20 Oversampling ratio of 21. 0x14 OSR_21 Oversampling ratio of 22. 0x15 OSR_22 Oversampling ratio of 23. 0x16 OSR_23 Oversampling ratio of 24. 0x17 OSR_24 Oversampling ratio of 25. 0x18 OSR_25 Oversampling ratio of 26. 0x19 OSR_26 Oversampling ratio of 27. 0x1A OSR_27 Oversampling ratio of 28. 0x1B OSR_28 Oversampling ratio of 29. 0x1C OSR_29 Oversampling ratio of 30. 0x1D OSR_30 Oversampling ratio of 31. 0x1E OSR_31 Oversampling ratio of 32. 0x1F OSR_3 Oversampling ratio of 4, requires BOTHEDGE to be set. 0x3 OSR_4 Oversampling ratio of 5, requires BOTHEDGE to be set. 0x4 OSR_5 Oversampling ratio of 6, requires BOTHEDGE to be set. 0x5 OSR_6 Oversampling ratio of 7, requires BOTHEDGE to be set. 0x6 OSR_7 Oversampling ratio of 8. 0x7 OSR_8 Oversampling ratio of 9. 0x8 OSR_9 Oversampling ratio of 10. 0x9 OSR_10 Oversampling ratio of 11. 0xA OSR_11 Oversampling ratio of 12. 0xB OSR_12 Oversampling ratio of 13. 0xC OSR_13 Oversampling ratio of 14. 0xD OSR_14 Oversampling ratio of 15. 0xE OSR_15 Oversampling ratio of 16. 0xF RDMAE Receiver Full DMA Enable 21 1 read-write RDMAE_0 DMA request disabled. 0 RDMAE_1 DMA request enabled. 0x1 RESYNCDIS Resynchronization Disable 16 1 read-write RESYNCDIS_0 Resynchronization during received data word is supported 0 RESYNCDIS_1 Resynchronization during received data word is disabled 0x1 RIDMAE Receiver Idle DMA Enable 20 1 read-write RIDMAE_0 DMA request disabled. 0 RIDMAE_1 DMA request enabled. 0x1 RXEDGIE RX Input Active Edge Interrupt Enable 14 1 read-write RXEDGIE_0 Hardware interrupts from LPUART_STAT[RXEDGIF] disabled. 0 RXEDGIE_1 Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1. 0x1 SBNS Stop Bit Number Select 13 1 read-write SBNS_0 One stop bit. 0 SBNS_1 Two stop bits. 0x1 SBR Baud Rate Modulo Divisor. 0 13 read-write TDMAE Transmitter DMA Enable 23 1 read-write TDMAE_0 DMA request disabled. 0 TDMAE_1 DMA request enabled. 0x1 CTRL LPUART Control Register 0x18 32 read-write n 0x0 0x0 DOZEEN Doze Enable 6 1 read-write DOZEEN_0 LPUART is enabled in Doze mode. 0 DOZEEN_1 LPUART is disabled in Doze mode. 0x1 FEIE Framing Error Interrupt Enable 25 1 read-write FEIE_0 FE interrupts disabled use polling. 0 FEIE_1 Hardware interrupt requested when FE is set. 0x1 IDLECFG Idle Configuration 8 3 read-write IDLECFG_0 1 idle character 0 IDLECFG_1 2 idle characters 0x1 IDLECFG_2 4 idle characters 0x2 IDLECFG_3 8 idle characters 0x3 IDLECFG_4 16 idle characters 0x4 IDLECFG_5 32 idle characters 0x5 IDLECFG_6 64 idle characters 0x6 IDLECFG_7 128 idle characters 0x7 ILIE Idle Line Interrupt Enable 20 1 read-write ILIE_0 Hardware interrupts from IDLE disabled use polling. 0 ILIE_1 Hardware interrupt requested when IDLE flag is 1. 0x1 ILT Idle Line Type Select 2 1 read-write ILT_0 Idle character bit count starts after start bit. 0 ILT_1 Idle character bit count starts after stop bit. 0x1 LOOPS Loop Mode Select 7 1 read-write LOOPS_0 Normal operation - RXD and TXD use separate pins. 0 LOOPS_1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). 0x1 M 9-Bit or 8-Bit Mode Select 4 1 read-write M_0 Receiver and transmitter use 8-bit data characters. 0 M_1 Receiver and transmitter use 9-bit data characters. 0x1 M7 7-Bit Mode Select 11 1 read-write M7_0 Receiver and transmitter use 8-bit to 10-bit data characters. 0 M7_1 Receiver and transmitter use 7-bit data characters. 0x1 MA1IE Match 1 Interrupt Enable 15 1 read-write MA1IE_0 MA1F interrupt disabled 0 MA1IE_1 MA1F interrupt enabled 0x1 MA2IE Match 2 Interrupt Enable 14 1 read-write MA2IE_0 MA2F interrupt disabled 0 MA2IE_1 MA2F interrupt enabled 0x1 NEIE Noise Error Interrupt Enable 26 1 read-write NEIE_0 NF interrupts disabled use polling. 0 NEIE_1 Hardware interrupt requested when NF is set. 0x1 ORIE Overrun Interrupt Enable 27 1 read-write ORIE_0 OR interrupts disabled use polling. 0 ORIE_1 Hardware interrupt requested when OR is set. 0x1 PE Parity Enable 1 1 read-write PE_0 No hardware parity generation or checking. 0 PE_1 Parity enabled. 0x1 PEIE Parity Error Interrupt Enable 24 1 read-write PEIE_0 PF interrupts disabled use polling). 0 PEIE_1 Hardware interrupt requested when PF is set. 0x1 PT Parity Type 0 1 read-write PT_0 Even parity. 0 PT_1 Odd parity. 0x1 R8T9 Receive Bit 8 / Transmit Bit 9 31 1 read-write R9T8 Receive Bit 9 / Transmit Bit 8 30 1 read-write RE Receiver Enable 18 1 read-write RE_0 Receiver disabled. 0 RE_1 Receiver enabled. 0x1 RIE Receiver Interrupt Enable 21 1 read-write RIE_0 Hardware interrupts from RDRF disabled use polling. 0 RIE_1 Hardware interrupt requested when RDRF flag is 1. 0x1 RSRC Receiver Source Select 5 1 read-write RSRC_0 Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. 0 RSRC_1 Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. 0x1 RWU Receiver Wakeup Control 17 1 read-write RWU_0 Normal receiver operation. 0 RWU_1 LPUART receiver in standby waiting for wakeup condition. 0x1 SBK Send Break 16 1 read-write SBK_0 Normal transmitter operation. 0 SBK_1 Queue break character(s) to be sent. 0x1 TCIE Transmission Complete Interrupt Enable for 22 1 read-write TCIE_0 Hardware interrupts from TC disabled use polling. 0 TCIE_1 Hardware interrupt requested when TC flag is 1. 0x1 TE Transmitter Enable 19 1 read-write TE_0 Transmitter disabled. 0 TE_1 Transmitter enabled. 0x1 TIE Transmit Interrupt Enable 23 1 read-write TIE_0 Hardware interrupts from TDRE disabled use polling. 0 TIE_1 Hardware interrupt requested when TDRE flag is 1. 0x1 TXDIR TXD Pin Direction in Single-Wire Mode 29 1 read-write TXDIR_0 TXD pin is an input in single-wire mode. 0 TXDIR_1 TXD pin is an output in single-wire mode. 0x1 TXINV Transmit Data Inversion 28 1 read-write TXINV_0 Transmit data not inverted. 0 TXINV_1 Transmit data inverted. 0x1 WAKE Receiver Wakeup Method Select 3 1 read-write WAKE_0 Configures RWU for idle-line wakeup. 0 WAKE_1 Configures RWU with address-mark wakeup. 0x1 DATA LPUART Data Register 0x1C 32 read-write n 0x0 0x0 FRETSC Frame Error / Transmit Special Character 13 1 read-write FRETSC_0 The dataword was received without a frame error on read, or transmit a normal character on write. 0 FRETSC_1 The dataword was received with a frame error, or transmit an idle or break character on transmit. 0x1 IDLINE Idle Line 11 1 read-only IDLINE_0 Receiver was not idle before receiving this character. 0 IDLINE_1 Receiver was idle before receiving this character. 0x1 NOISY NOISY 15 1 read-only NOISY_0 The dataword was received without noise. 0 NOISY_1 The data was received with noise. 0x1 PARITYE PARITYE 14 1 read-only PARITYE_0 The dataword was received without a parity error. 0 PARITYE_1 The dataword was received with a parity error. 0x1 R0T0 R0T0 0 1 read-write R1T1 R1T1 1 1 read-write R2T2 R2T2 2 1 read-write R3T3 R3T3 3 1 read-write R4T4 R4T4 4 1 read-write R5T5 R5T5 5 1 read-write R6T6 R6T6 6 1 read-write R7T7 R7T7 7 1 read-write R8T8 R8T8 8 1 read-write R9T9 R9T9 9 1 read-write RXEMPT Receive Buffer Empty 12 1 read-only RXEMPT_0 Receive buffer contains valid data. 0 RXEMPT_1 Receive buffer is empty, data returned on read is not valid. 0x1 FIFO LPUART FIFO Register 0x28 32 read-write n 0x0 0x0 RXEMPT Receive Buffer/FIFO Empty 22 1 read-only RXEMPT_0 Receive buffer is not empty. 0 RXEMPT_1 Receive buffer is empty. 0x1 RXFE Receive FIFO Enable 3 1 read-write RXFE_0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) 0 RXFE_1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. 0x1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only RXFIFOSIZE_0 Receive FIFO/Buffer depth = 1 dataword. 0 RXFIFOSIZE_1 Receive FIFO/Buffer depth = 4 datawords. 0x1 RXFIFOSIZE_2 Receive FIFO/Buffer depth = 8 datawords. 0x2 RXFIFOSIZE_3 Receive FIFO/Buffer depth = 16 datawords. 0x3 RXFIFOSIZE_4 Receive FIFO/Buffer depth = 32 datawords. 0x4 RXFIFOSIZE_5 Receive FIFO/Buffer depth = 64 datawords. 0x5 RXFIFOSIZE_6 Receive FIFO/Buffer depth = 128 datawords. 0x6 RXFIFOSIZE_7 Receive FIFO/Buffer depth = 256 datawords. 0x7 RXFLUSH Receive FIFO/Buffer Flush 14 1 write-only RXFLUSH_0 No flush operation occurs. 0 RXFLUSH_1 All data in the receive FIFO/buffer is cleared out. 0x1 RXIDEN Receiver Idle Empty Enable 10 3 read-write RXIDEN_0 Disable RDRF assertion due to partially filled FIFO when receiver is idle. 0 RXIDEN_1 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. 0x1 RXIDEN_2 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. 0x2 RXIDEN_3 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. 0x3 RXIDEN_4 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. 0x4 RXIDEN_5 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. 0x5 RXIDEN_6 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. 0x6 RXIDEN_7 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. 0x7 RXUF Receiver Buffer Underflow Flag 16 1 read-write oneToClear RXUF_0 No receive buffer underflow has occurred since the last time the flag was cleared. 0 RXUF_1 At least one receive buffer underflow has occurred since the last time the flag was cleared. 0x1 RXUFE Receive FIFO Underflow Interrupt Enable 8 1 read-write RXUFE_0 RXUF flag does not generate an interrupt to the host. 0 RXUFE_1 RXUF flag generates an interrupt to the host. 0x1 TXEMPT Transmit Buffer/FIFO Empty 23 1 read-only TXEMPT_0 Transmit buffer is not empty. 0 TXEMPT_1 Transmit buffer is empty. 0x1 TXFE Transmit FIFO Enable 7 1 read-write TXFE_0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). 0 TXFE_1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. 0x1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only TXFIFOSIZE_0 Transmit FIFO/Buffer depth = 1 dataword. 0 TXFIFOSIZE_1 Transmit FIFO/Buffer depth = 4 datawords. 0x1 TXFIFOSIZE_2 Transmit FIFO/Buffer depth = 8 datawords. 0x2 TXFIFOSIZE_3 Transmit FIFO/Buffer depth = 16 datawords. 0x3 TXFIFOSIZE_4 Transmit FIFO/Buffer depth = 32 datawords. 0x4 TXFIFOSIZE_5 Transmit FIFO/Buffer depth = 64 datawords. 0x5 TXFIFOSIZE_6 Transmit FIFO/Buffer depth = 128 datawords. 0x6 TXFIFOSIZE_7 Transmit FIFO/Buffer depth = 256 datawords 0x7 TXFLUSH Transmit FIFO/Buffer Flush 15 1 write-only TXFLUSH_0 No flush operation occurs. 0 TXFLUSH_1 All data in the transmit FIFO/Buffer is cleared out. 0x1 TXOF Transmitter Buffer Overflow Flag 17 1 read-write oneToClear TXOF_0 No transmit buffer overflow has occurred since the last time the flag was cleared. 0 TXOF_1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. 0x1 TXOFE Transmit FIFO Overflow Interrupt Enable 9 1 read-write TXOFE_0 TXOF flag does not generate an interrupt to the host. 0 TXOFE_1 TXOF flag generates an interrupt to the host. 0x1 GLOBAL LPUART Global Register 0x8 32 read-write n 0x0 0x0 RST Software Reset 1 1 read-write RST_0 Module is not reset. 0 RST_1 Module is reset. 0x1 MATCH LPUART Match Address Register 0x20 32 read-write n 0x0 0x0 MA1 Match Address 1 0 10 read-write MA2 Match Address 2 16 10 read-write MODIR LPUART Modem IrDA Register 0x24 32 read-write n 0x0 0x0 IREN Infrared enable 18 1 read-write IREN_0 IR disabled. 0 IREN_1 IR enabled. 0x1 RTSWATER Receive RTS Configuration 8 3 read-write RXRTSE Receiver request-to-send enable 3 1 read-write RXRTSE_0 The receiver has no effect on RTS. 0 RXRTSE_1 no description available 0x1 TNP Transmitter narrow pulse 16 2 read-write TNP_0 1/OSR. 0 TNP_1 2/OSR. 0x1 TNP_2 3/OSR. 0x2 TNP_3 4/OSR. 0x3 TXCTSC Transmit CTS Configuration 4 1 read-write TXCTSC_0 CTS input is sampled at the start of each character. 0 TXCTSC_1 CTS input is sampled when the transmitter is idle. 0x1 TXCTSE Transmitter clear-to-send enable 0 1 read-write TXCTSE_0 CTS has no effect on the transmitter. 0 TXCTSE_1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. 0x1 TXCTSSRC Transmit CTS Source 5 1 read-write TXCTSSRC_0 CTS input is the CTS_B pin. 0 TXCTSSRC_1 CTS input is the inverted Receiver Match result. 0x1 TXRTSE Transmitter request-to-send enable 1 1 read-write TXRTSE_0 The transmitter has no effect on RTS. 0 TXRTSE_1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. 0x1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write TXRTSPOL_0 Transmitter RTS is active low. 0 TXRTSPOL_1 Transmitter RTS is active high. 0x1 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 RXFIFO Receive FIFO Size 8 8 read-only TXFIFO Transmit FIFO Size 0 8 read-only PINCFG LPUART Pin Configuration Register 0xC 32 read-write n 0x0 0x0 TRGSEL Trigger Select 0 2 read-write TRGSEL_0 Input trigger is disabled. 0 TRGSEL_1 Input trigger is used instead of RXD pin input. 0x1 TRGSEL_2 Input trigger is used instead of CTS_B pin input. 0x2 TRGSEL_3 Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. 0x3 STAT LPUART Status Register 0x14 32 read-write n 0x0 0x0 BRK13 Break Character Generation Length 26 1 read-write BRK13_0 Break character is transmitted with length of 9 to 13 bit times. 0 BRK13_1 Break character is transmitted with length of 12 to 15 bit times. 0x1 FE Framing Error Flag 17 1 read-write oneToClear FE_0 No framing error detected. This does not guarantee the framing is correct. 0 FE_1 Framing error. 0x1 IDLE Idle Line Flag 20 1 read-write oneToClear IDLE_0 No idle line detected. 0 IDLE_1 Idle line was detected. 0x1 LBKDE LIN Break Detection Enable 25 1 read-write LBKDE_0 LIN break detect is disabled, normal break character can be detected. 0 LBKDE_1 LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). 0x1 LBKDIF LIN Break Detect Interrupt Flag 31 1 read-write oneToClear LBKDIF_0 No LIN break character has been detected. 0 LBKDIF_1 LIN break character has been detected. 0x1 MA1F Match 1 Flag 15 1 read-write oneToClear MA1F_0 Received data is not equal to MA1 0 MA1F_1 Received data is equal to MA1 0x1 MA2F Match 2 Flag 14 1 read-write oneToClear MA2F_0 Received data is not equal to MA2 0 MA2F_1 Received data is equal to MA2 0x1 MSBF MSB First 29 1 read-write MSBF_0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. 0 MSBF_1 MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. 0x1 NF Noise Flag 18 1 read-write oneToClear NF_0 No noise detected. 0 NF_1 Noise detected in the received character in LPUART_DATA. 0x1 OR Receiver Overrun Flag 19 1 read-write oneToClear OR_0 No overrun. 0 OR_1 Receive overrun (new LPUART data lost). 0x1 PF Parity Error Flag 16 1 read-write oneToClear PF_0 No parity error. 0 PF_1 Parity error. 0x1 RAF Receiver Active Flag 24 1 read-only RAF_0 LPUART receiver idle waiting for a start bit. 0 RAF_1 LPUART receiver active (RXD input not idle). 0x1 RDRF Receive Data Register Full Flag 21 1 read-only RDRF_0 Receive data buffer empty. 0 RDRF_1 Receive data buffer full. 0x1 RWUID Receive Wake Up Idle Detect 27 1 read-write RWUID_0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. 0 RWUID_1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match. 0x1 RXEDGIF RXD Pin Active Edge Interrupt Flag 30 1 read-write oneToClear RXEDGIF_0 No active edge on the receive pin has occurred. 0 RXEDGIF_1 An active edge on the receive pin has occurred. 0x1 RXINV Receive Data Inversion 28 1 read-write RXINV_0 Receive data not inverted. 0 RXINV_1 Receive data inverted. 0x1 TC Transmission Complete Flag 22 1 read-only TC_0 Transmitter active (sending data, a preamble, or a break). 0 TC_1 Transmitter idle (transmission activity complete). 0x1 TDRE Transmit Data Register Empty Flag 23 1 read-only TDRE_0 Transmit data buffer full. 0 TDRE_1 Transmit data buffer empty. 0x1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Identification Number 0 16 read-only FEATURE_1 Standard feature set. 0x1 FEATURE_3 Standard feature set with MODEM/IrDA support. 0x3 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only WATER LPUART Watermark Register 0x2C 32 read-write n 0x0 0x0 RXCOUNT Receive Counter 24 4 read-only RXWATER Receive Watermark 16 3 read-write TXCOUNT Transmit Counter 8 4 read-only TXWATER Transmit Watermark 0 3 read-write MCM0 MCM MCM_CM4 0x0 0x0 0x44 registers n CTI0_MCM0 0 CPCR Core Platform Control Register 0xC 32 read-write n 0x0 0x0 CBRR Crossbar round-robin arbitration enable 9 1 read-write CBRR_0 Fixed-priority arbitration 0 CBRR_1 Round-robin arbitration 0x1 CPCR2 Core Platform Control Register 2 0x34 32 read-write n 0x0 0x0 CBCS Code Bus Cache Size 4 4 read-only CBCS_0 0 KB 0 CBCS_1 1 KB 0x1 CBCS_2 2 KB 0x2 CBCS_3 4 KB 0x3 CBCS_4 8 KB 0x4 CBCS_5 16 KB 0x5 CBCS_6 32 KB 0x6 CCBC Clear code bus cache, this field always reads as 0. 0 1 write-only CCBC_0 No effect 0 CCBC_1 Clear code bus cache 0x1 DCBC Disable code bus cache 3 1 read-write DCBC_0 Enable code bus cache 0 DCBC_1 Disable code bus cache 0x1 LCCPWB Limit code cache peripheral write buffering 17 1 read-write LCCPWB_0 Code cache peripheral write buffering is not limited 0 LCCPWB_1 Code cache peripheral write buffering is limited 0x1 PCCMCTRL Bypass fixed code cache map 16 1 read-write PCCMCTRL_0 The fixed code cache map is not bypassed 0 PCCMCTRL_1 The fixed code cache map is bypassed 0x1 CPO Compute Operation Control Register 0x40 32 read-write n 0x0 0x0 CPOACK Compute Operation acknowledge 1 1 read-only CPOACK_0 Compute operation entry has not completed or compute operation exit has completed. 0 CPOACK_1 Compute operation entry has completed or compute operation exit has not completed. 0x1 CPOREQ Compute Operation request 0 1 read-write CPOREQ_0 Request is cleared. 0 CPOREQ_1 Request Compute Operation. 0x1 CPOWOI Compute Operation wakeup on interrupt 2 1 read-write CPOWOI_0 No effect. 0 CPOWOI_1 When set, the CPOREQ is cleared on any interrupt or exception vector fetch. 0x1 ISCR Interrupt Status and Control Register 0x10 32 read-write n 0x0 0x0 FDZC FPU divide-by-zero interrupt status 9 1 read-only FDZC_0 No interrupt 0 FDZC_1 Interrupt occurred 0x1 FDZCE FPU divide-by-zero interrupt enable 25 1 read-write FDZCE_0 Disable interrupt 0 FDZCE_1 Enable interrupt 0x1 FIDC FPU input denormal interrupt status 15 1 read-only FIDC_0 No interrupt 0 FIDC_1 Interrupt occurred 0x1 FIDCE FPU input denormal interrupt enable 31 1 read-write FIDCE_0 Disable interrupt 0 FIDCE_1 Enable interrupt 0x1 FIOC FPU invalid operation interrupt status 8 1 read-only FIOC_0 No interrupt 0 FIOC_1 Interrupt occurred 0x1 FIOCE FPU invalid operation interrupt enable 24 1 read-write FIOCE_0 Disable interrupt 0 FIOCE_1 Enable interrupt 0x1 FIXC FPU inexact interrupt status 12 1 read-only FIXC_0 No interrupt 0 FIXC_1 Interrupt occurred 0x1 FIXCE FPU inexact interrupt enable 28 1 read-write FIXCE_0 Disable interrupt 0 FIXCE_1 Enable interrupt 0x1 FOFC FPU overflow interrupt status 10 1 read-only FOFC_0 No interrupt 0 FOFC_1 Interrupt occurred 0x1 FOFCE FPU overflow interrupt enable 26 1 read-write FOFCE_0 Disable interrupt 0 FOFCE_1 Enable interrupt 0x1 FUFC FPU underflow interrupt status 11 1 read-only FUFC_0 No interrupt 0 FUFC_1 Interrupt occurred 0x1 FUFCE FPU underflow interrupt enable 27 1 read-write FUFCE_0 Disable interrupt 0 FUFCE_1 Enable interrupt 0x1 PLAMC Crossbar Switch (AXBS) Master Configuration 0xA 16 read-only n 0x0 0x0 AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 8 read-only PLASC Crossbar Switch (AXBS) Slave Configuration 0x8 16 read-only n 0x0 0x0 ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 8 read-only MSCM MSCM MSCM 0x0 0x0 0x410 registers n CP0CFG0 Processor 0 Configuration Register 0 0x30 32 read-only n 0x0 0x0 DCSZ Level 1 Data Cache Size 8 8 read-only DCWY Level 1 Data Cache Ways 0 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only CP0CFG1 Processor 0 Configuration Register 1 0x34 32 read-only n 0x0 0x0 L2SZ Level 2 Instruction Cache Size 24 8 read-only L2WY Level 2 Instruction Cache Ways 16 8 read-only CP0CFG2 Processor 0 Configuration Register 2 0x38 32 read-only n 0x0 0x0 TMLSZ Tightly-coupled Memory Lower Size 24 8 read-only TMUSZ Tightly-coupled Memory Upper Size 8 8 read-only CP0CFG3 Processor 0 Configuration Register 3 0x3C 32 read-only n 0x0 0x0 BB Bit Banding 6 1 read-only BB_0 Bit Banding is not supported. 0 BB_1 Bit Banding is supported. 0x1 CMP Core Memory Protection unit 5 1 read-only CMP_0 Core Memory Protection is not included. 0 CMP_1 Core Memory Protection is included. 0x1 FPU Floating Point Unit 0 1 read-only FPU_0 FPU support is not included. 0 FPU_1 FPU support is included. 0x1 JAZ Jazelle support 2 1 read-only JAZ_0 Jazelle support is not included. 0 JAZ_1 Jazelle support is included. 0x1 MMU Memory Management Unit 3 1 read-only MMU_0 MMU support is not included. 0 MMU_1 MMU support is included. 0x1 SBP System Bus Ports 8 2 read-only SIMD SIMD/NEON instruction support 1 1 read-only SIMD_0 SIMD/NEON support is not included. 0 SIMD_1 SIMD/NEON support is included. 0x1 TZ Trust Zone 4 1 read-only TZ_0 Trust Zone support is not included. 0 TZ_1 Trust Zone support is included. 0x1 CP0COUNT Processor 0 Count Register 0x2C 32 read-only n 0x0 0x0 PCNT Processor Count 0 2 read-only CP0MASTER Processor 0 Master Register 0x28 32 read-only n 0x0 0x0 PPMN Processor 0 Physical Master Number 0 6 read-only CP0NUM Processor 0 Number Register 0x24 32 read-only n 0x0 0x0 CPN Processor 0 Number 0 1 read-only CP0TYPE Processor 0 Type Register 0x20 32 read-only n 0x0 0x0 PERSONALITY Processor 0 Personality 8 24 read-only RYPZ Processor 0 Revision 0 8 read-only CP1CFG0 Processor 1 Configuration Register 0 0x50 32 read-only n 0x0 0x0 DCSZ Level 1 Data Cache Size 8 8 read-only DCWY Level 1 Data Cache Ways 0 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only CP1CFG1 Processor 1 Configuration Register 1 0x54 32 read-only n 0x0 0x0 L2SZ Level 2 Instruction Cache Size 24 8 read-only L2WY Level 2 Instruction Cache Ways 16 8 read-only CP1CFG2 Processor 1 Configuration Register 2 0x58 32 read-only n 0x0 0x0 TMLSZ Tightly-coupled Memory Lower Size 24 8 read-only TMUSZ Tightly-coupled Memory Upper Size 8 8 read-only CP1CFG3 Processor 1 Configuration Register 3 0x5C 32 read-only n 0x0 0x0 BB Bit Banding 6 1 read-only BB_0 Bit Banding is not supported. 0 BB_1 Bit Banding is supported. 0x1 CMP Core Memory Protection unit 5 1 read-only CMP_0 Core Memory Protection is not included. 0 CMP_1 Core Memory Protection is included. 0x1 FPU Floating Point Unit 0 1 read-only FPU_0 FPU support is not included. 0 FPU_1 FPU support is included. 0x1 JAZ Jazelle support 2 1 read-only JAZ_0 Jazelle support is not included. 0 JAZ_1 Jazelle support is included. 0x1 MMU Memory Management Unit 3 1 read-only MMU_0 MMU support is not included. 0 MMU_1 MMU support is included. 0x1 SBP System Bus Ports 8 2 read-only SIMD SIMD/NEON instruction support 1 1 read-only SIMD_0 SIMD/NEON support is not included. 0 SIMD_1 SIMD/NEON support is included. 0x1 TZ Trust Zone 4 1 read-only TZ_0 Trust Zone support is not included. 0 TZ_1 Trust Zone support is included. 0x1 CP1COUNT Processor 1 Count Register 0x4C 32 read-only n 0x0 0x0 PCNT Processor Count 0 2 read-only CP1MASTER Processor 1 Master Register 0x48 32 read-only n 0x0 0x0 PPMN Processor 1 Physical Master Number 0 6 read-only CP1NUM Processor 1 Number Register 0x44 32 read-only n 0x0 0x0 CPN Processor 1 Number 0 1 read-only CP1TYPE Processor 1 Type Register 0x40 32 read-only n 0x0 0x0 PERSONALITY Processor 1 Personality 8 24 read-only RYPZ Processor 1 Revision 0 8 read-only CPxCFG0 Processor X Configuration Register 0 0x10 32 read-only n 0x0 0x0 DCSZ Level 1 Data Cache Size 8 8 read-only DCWY Level 1 Data Cache Ways 0 8 read-only ICSZ Level 1 Instruction Cache Size 24 8 read-only ICWY Level 1 Instruction Cache Ways 16 8 read-only CPxCFG1 Processor X Configuration Register 1 0x14 32 read-only n 0x0 0x0 L2SZ Level 2 Instruction Cache Size 24 8 read-only L2WY Level 2 Instruction Cache Ways 16 8 read-only CPxCFG2 Processor X Configuration Register 2 0x18 32 read-only n 0x0 0x0 TMLSZ Tightly-coupled Memory Lower Size 24 8 read-only TMUSZ Tightly-coupled Memory Upper Size 8 8 read-only CPxCFG3 Processor X Configuration Register 3 0x1C 32 read-only n 0x0 0x0 BB Bit Banding 6 1 read-only BB_0 Bit Banding is not supported. 0 BB_1 Bit Banding is supported. 0x1 CMP Core Memory Protection unit 5 1 read-only CMP_0 Core Memory Protection is not included. 0 CMP_1 Core Memory Protection is included. 0x1 FPU Floating Point Unit 0 1 read-only FPU_0 FPU support is not included. 0 FPU_1 FPU support is included. 0x1 JAZ Jazelle support 2 1 read-only JAZ_0 Jazelle support is not included. 0 JAZ_1 Jazelle support is included. 0x1 MMU Memory Management Unit 3 1 read-only MMU_0 MMU support is not included. 0 MMU_1 MMU support is included. 0x1 SBP System Bus Ports 8 2 read-only SIMD SIMD/NEON instruction support 1 1 read-only SIMD_0 SIMD/NEON support is not included. 0 SIMD_1 SIMD/NEON support is included. 0x1 TZ Trust Zone 4 1 read-only TZ_0 Trust Zone support is not included. 0 TZ_1 Trust Zone support is included. 0x1 CPxCOUNT Processor X Count Register 0xC 32 read-only n 0x0 0x0 PCNT Processor Count 0 2 read-only CPxMASTER Processor X Master Register 0x8 32 read-only n 0x0 0x0 PPMN Processor x Physical Master Number 0 6 read-only CPxNUM Processor X Number Register 0x4 32 read-only n 0x0 0x0 CPN Processor x Number 0 1 read-only CPxTYPE Processor X Type Register 0x0 32 read-only n 0x0 0x0 PERSONALITY Processor x Personality 8 24 read-only RYPZ Processor x Revision 0 8 read-only OCMDR0 On-Chip Memory Descriptor Register 0x400 32 read-write n 0x0 0x0 OCM1 OCMEM Control Field 1 4 2 read-write OCMPU OCMPU 12 1 read-only OCMSZ OCMSZ 24 4 read-only OCMSZ_0 no OCMEMn 0 OCMSZ_1 1KB OCMEMn 0x1 OCMSZ_2 2KB OCMEMn 0x2 OCMSZ_3 4KB OCMEMn 0x3 OCMSZ_4 8KB OCMEMn 0x4 OCMSZ_5 16KB OCMEMn 0x5 OCMSZ_6 32KB OCMEMn 0x6 OCMSZ_7 64KB OCMEMn 0x7 OCMSZ_8 128KB OCMEMn 0x8 OCMSZ_9 256KB OCMEMn 0x9 OCMSZ_10 512KB OCMEMn 0xA OCMSZ_11 1MB OCMEMn 0xB OCMSZ_12 2MB OCMEMn 0xC OCMSZ_13 4MB OCMEMn 0xD OCMSZ_14 8MB OCMEMn 0xE OCMSZ_15 16MB OCMEMn 0xF OCMSZH OCMSZH 28 1 read-only OCMSZH_0 OCMEMn is a power-of-2 capacity. 0 OCMSZH_1 OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. 0x1 OCMT OCMT 13 3 read-only OCMT_3 OCMEMn is a ROM. 0x3 OCMT_4 OCMEMn is a Program Flash. 0x4 OCMT_6 OCMEMn is an EEE. 0x6 OCMW OCMW 17 3 read-only OCMW_2 OCMEMn 32-bits wide 0x2 OCMW_3 OCMEMn 64-bits wide 0x3 OCMW_4 OCMEMn 128-bits wide 0x4 OCMW_5 OCMEMn 256-bits wide 0x5 RO RO 16 1 read-write RO_0 Writes to the OCMDRn[11:0] are allowed 0 RO_1 Writes to the OCMDRn[11:0] are ignored 0x1 V V 31 1 read-only V_0 OCMEMn is not present. 0 V_1 OCMEMn is present. 0x1 OCMDR1 On-Chip Memory Descriptor Register 0x404 32 read-write n 0x0 0x0 OCM1 OCMEM Control Field 1 4 2 read-write OCMPU OCMPU 12 1 read-only OCMSZ OCMSZ 24 4 read-only OCMSZ_0 no OCMEMn 0 OCMSZ_1 1KB OCMEMn 0x1 OCMSZ_2 2KB OCMEMn 0x2 OCMSZ_3 4KB OCMEMn 0x3 OCMSZ_4 8KB OCMEMn 0x4 OCMSZ_5 16KB OCMEMn 0x5 OCMSZ_6 32KB OCMEMn 0x6 OCMSZ_7 64KB OCMEMn 0x7 OCMSZ_8 128KB OCMEMn 0x8 OCMSZ_9 256KB OCMEMn 0x9 OCMSZ_10 512KB OCMEMn 0xA OCMSZ_11 1MB OCMEMn 0xB OCMSZ_12 2MB OCMEMn 0xC OCMSZ_13 4MB OCMEMn 0xD OCMSZ_14 8MB OCMEMn 0xE OCMSZ_15 16MB OCMEMn 0xF OCMSZH OCMSZH 28 1 read-only OCMSZH_0 OCMEMn is a power-of-2 capacity. 0 OCMSZH_1 OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. 0x1 OCMT OCMT 13 3 read-only OCMT_3 OCMEMn is a ROM. 0x3 OCMT_4 OCMEMn is a Program Flash. 0x4 OCMT_6 OCMEMn is an EEE. 0x6 OCMW OCMW 17 3 read-only OCMW_2 OCMEMn 32-bits wide 0x2 OCMW_3 OCMEMn 64-bits wide 0x3 OCMW_4 OCMEMn 128-bits wide 0x4 OCMW_5 OCMEMn 256-bits wide 0x5 RO RO 16 1 read-write RO_0 Writes to the OCMDRn[11:0] are allowed 0 RO_1 Writes to the OCMDRn[11:0] are ignored 0x1 V V 31 1 read-only V_0 OCMEMn is not present. 0 V_1 OCMEMn is present. 0x1 OCMDR2 On-Chip Memory Descriptor Register 0x408 32 read-write n 0x0 0x0 OCMPU OCMPU 12 1 read-only OCMSZ OCMSZ 24 4 read-only OCMSZ_0 no OCMEMn 0 OCMSZ_1 1KB OCMEMn 0x1 OCMSZ_2 2KB OCMEMn 0x2 OCMSZ_3 4KB OCMEMn 0x3 OCMSZ_4 8KB OCMEMn 0x4 OCMSZ_5 16KB OCMEMn 0x5 OCMSZ_6 32KB OCMEMn 0x6 OCMSZ_7 64KB OCMEMn 0x7 OCMSZ_8 128KB OCMEMn 0x8 OCMSZ_9 256KB OCMEMn 0x9 OCMSZ_10 512KB OCMEMn 0xA OCMSZ_11 1MB OCMEMn 0xB OCMSZ_12 2MB OCMEMn 0xC OCMSZ_13 4MB OCMEMn 0xD OCMSZ_14 8MB OCMEMn 0xE OCMSZ_15 16MB OCMEMn 0xF OCMSZH OCMSZH 28 1 read-only OCMSZH_0 OCMEMn is a power-of-2 capacity. 0 OCMSZH_1 OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. 0x1 OCMT OCMT 13 3 read-only OCMT_3 OCMEMn is a ROM. 0x3 OCMT_4 OCMEMn is a Program Flash. 0x4 OCMT_6 OCMEMn is an EEE. 0x6 OCMW OCMW 17 3 read-only OCMW_2 OCMEMn 32-bits wide 0x2 OCMW_3 OCMEMn 64-bits wide 0x3 OCMW_4 OCMEMn 128-bits wide 0x4 OCMW_5 OCMEMn 256-bits wide 0x5 RO RO 16 1 read-write RO_0 Writes to the OCMDRn[11:0] are allowed 0 RO_1 Writes to the OCMDRn[11:0] are ignored 0x1 V V 31 1 read-only V_0 OCMEMn is not present. 0 V_1 OCMEMn is present. 0x1 OCMDR3 On-Chip Memory Descriptor Register 0x40C 32 read-write n 0x0 0x0 OCMPU OCMPU 12 1 read-only OCMSZ OCMSZ 24 4 read-only OCMSZ_0 no OCMEMn 0 OCMSZ_1 1KB OCMEMn 0x1 OCMSZ_2 2KB OCMEMn 0x2 OCMSZ_3 4KB OCMEMn 0x3 OCMSZ_4 8KB OCMEMn 0x4 OCMSZ_5 16KB OCMEMn 0x5 OCMSZ_6 32KB OCMEMn 0x6 OCMSZ_7 64KB OCMEMn 0x7 OCMSZ_8 128KB OCMEMn 0x8 OCMSZ_9 256KB OCMEMn 0x9 OCMSZ_10 512KB OCMEMn 0xA OCMSZ_11 1MB OCMEMn 0xB OCMSZ_12 2MB OCMEMn 0xC OCMSZ_13 4MB OCMEMn 0xD OCMSZ_14 8MB OCMEMn 0xE OCMSZ_15 16MB OCMEMn 0xF OCMSZH OCMSZH 28 1 read-only OCMSZH_0 OCMEMn is a power-of-2 capacity. 0 OCMSZH_1 OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. 0x1 OCMT OCMT 13 3 read-only OCMT_3 OCMEMn is a ROM. 0x3 OCMT_4 OCMEMn is a Program Flash. 0x4 OCMT_6 OCMEMn is an EEE. 0x6 OCMW OCMW 17 3 read-only OCMW_2 OCMEMn 32-bits wide 0x2 OCMW_3 OCMEMn 64-bits wide 0x3 OCMW_4 OCMEMn 128-bits wide 0x4 OCMW_5 OCMEMn 256-bits wide 0x5 RO RO 16 1 read-write RO_0 Writes to the OCMDRn[11:0] are allowed 0 RO_1 Writes to the OCMDRn[11:0] are ignored 0x1 V V 31 1 read-only V_0 OCMEMn is not present. 0 V_1 OCMEMn is present. 0x1 MUA MUA MU 0x0 0x0 0x6C registers n MUA 23 CCR Core Control Register 0x68 32 read-write n 0x0 0x0 BOOT Slave Processor B Boot Config. 4 2 read-write BOOT_0 Boot from Dflash base 0 BOOT_2 Boot from CM0+ RAM base 0x2 CLKE MUB clock enable 3 1 read-write CLKE_0 MUB platform clock gated when MUB-side enters a stop mode. 0 CLKE_1 MUB platform clock kept running after MUB-side enters a stop mode, until MUA also enters a stop mode. 0x1 HR HR 0 1 read-write HR_0 De-assert Hardware reset to the Processor B. (default) 0 HR_1 Assert Hardware reset to the Processor B. 0x1 HRM When set, HR bit in MUB CCR has no effect 1 1 read-write HRM_0 HR bit in MUB CCR is not masked, enables the hardware reset to the Processor A (default after hardware reset). 0 HRM_1 HR bit in MUB CCR is masked, disables the hardware reset request to the Processor A. 0x1 RSTH Processor B Reset Hold 2 1 read-write RSTH_0 Release Processor B from reset 0 RSTH_1 Hold Processor B in reset 0x1 CR Control Register 0x64 32 read-write n 0x0 0x0 Fn Fn 0 3 read-write Fn_0 Clears the Fn bit in the SR register. 0 Fn_1 Sets the Fn bit in the SR register. 0x1 GIEn GIEn 28 4 read-write GIEn_0 Disables MUA General Interrupt n. (default) 0 GIEn_1 Enables MUA General Interrupt n. 0x1 GIRn GIRn 16 4 read-write GIRn_0 MUA General Interrupt n is not requested to the MUB (default). 0 GIRn_1 MUA General Interrupt n is requested to the MUB. 0x1 HRIE Processor A hardware reset interrupt enable 7 1 read-write HRIE_0 Disables Processor A General Purpose Interrupt 3 request due to Processor B issued HR to Processor A. 0 HRIE_1 Enables Processor A General Purpose Interrupt 3 request due to Processor B issued HR to Processor A. 0x1 MUR MUR 5 1 read-write MUR_0 N/A. Self clearing bit (default). 0 MUR_1 Asserts the MU reset. 0x1 MURIE MURIE 11 1 read-write MURIE_0 Disables Processor A-side General Purpose Interrupt 3 request due to MU reset issued by MUB. 0 MURIE_1 Enables Processor A-side General Purpose Interrupt 3 request due to MU reset issued by MUB. 0x1 NMI NMI 3 1 read-write NMI_0 Non-maskable interrupt is not issued to the Processor B by the Processor A (default). 0 NMI_1 Non-maskable interrupt is issued to the Processor B by the Processor A. 0x1 RAIE RAIE 12 1 read-write RAIE_0 Disables Processor A-side General Purpose Interrupt 3 request due to Processor B reset assertion. 0 RAIE_1 Enables Processor A-side General Purpose Interrupt 3 request due to Processor B reset assertion. 0x1 RDIE RDIE 6 1 read-write RDIE_0 Disables Processor A General Purpose Interrupt 3 request due to Processor B reset de-assertion. 0 RDIE_1 Enables Processor A General Purpose Interrupt 3 request due to Processor B reset de-assertion. 0x1 RIEn RIEn 24 4 read-write RIEn_0 Disables MUA Receive Interrupt n. (default) 0 RIEn_1 Enables MUA Receive Interrupt n. 0x1 TIEn TIEn 20 4 read-write TIEn_0 Disables MUA Transmit Interrupt n. (default) 0 TIEn_1 Enables MUA Transmit Interrupt n. 0x1 PAR Parameter Register 0x4 32 read-only n 0x0 0x0 PARAMETER This bitfield contains the parameter settings of MUA. 0 32 read-only RR0 Receive Register 0x40 32 read-only n 0x0 0x0 DATA DATA 0 32 read-only RR1 Receive Register 0x44 32 read-only n 0x0 0x0 DATA DATA 0 32 read-only RR2 Receive Register 0x48 32 read-only n 0x0 0x0 DATA DATA 0 32 read-only RR3 Receive Register 0x4C 32 read-only n 0x0 0x0 DATA DATA 0 32 read-only RR[0] Receive Register 0x80 32 read-only n 0x0 0x0 DATA DATA 0 32 read-only RR[1] Receive Register 0xC4 32 read-only n 0x0 0x0 DATA DATA 0 32 read-only RR[2] Receive Register 0x10C 32 read-only n 0x0 0x0 DATA DATA 0 32 read-only RR[3] Receive Register 0x158 32 read-only n 0x0 0x0 DATA DATA 0 32 read-only SR Status Register 0x60 32 read-write n 0x0 0x0 EP EP 4 1 read-only EP_0 The MUA side event is not pending (default). 0 EP_1 The MUA side event is pending. 0x1 Fn Fn 0 3 read-only Fn_0 Fn bit in the MUB CR register is written 0 (default). 0 Fn_1 Fn bit in the MUB CR register is written 1. 0x1 FUP FUP 8 1 read-only FUP_0 No flags updated, initiated by the MUA, in progress (default) 0 FUP_1 MUA initiated flags update, processing 0x1 GIPn GIPn 28 4 read-only GIPn_0 MUA general purpose interrupt n is not pending. (default) 0 GIPn_1 MUA general purpose interrupt n is pending. 0x1 HRIP HRIP 7 1 read-write oneToClear HRIP_0 MUB didn't issue hardware reset to Processor A 0 HRIP_1 MUB had initiated a hardware reset to Processor A through HR bit. 0x1 MURIP MURIP 11 1 read-write oneToClear MURIP_0 Processor B did not issue MU reset 0 MURIP_1 Processor B issued MU reset 0x1 NMIC NMIC 3 1 read-write oneToClear NMIC_0 Default 0 NMIC_1 Writing 1 clears the NMI bit in the MUB CR register. 0x1 PM PM 12 3 read-only RUN The MUB processor is in Run Mode. 0 COO The MUB processor is in COO Mode. 0x1 WAIT The MUB processor is in WAIT Mode. 0x2 STOP no description available 0x3 DSM no description available 0x4 RAIP RAIP 10 1 read-write oneToClear RAIP_0 Processor B did not enter reset 0 RAIP_1 Processor B entered reset 0x1 RDIP RDIP 9 1 read-write oneToClear RDIP_0 Processor B did not exit reset 0 RDIP_1 Processor B exited from reset 0x1 RFn RFn 24 4 read-only RFn_0 MUA RRn register is not full (default). 0 RFn_1 MUA RRn register has received data from MUB TRn register and is ready to be read by the MUA. 0x1 TEn TEn 20 4 read-only TEn_0 MUA TRn register is not empty. 0 TEn_1 MUA TRn register is empty (default). 0x1 TR0 Transmit Register 0x20 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write TR1 Transmit Register 0x24 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write TR2 Transmit Register 0x28 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write TR3 Transmit Register 0x2C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write TR[0] Transmit Register 0x40 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write TR[1] Transmit Register 0x64 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write TR[2] Transmit Register 0x8C 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write TR[3] Transmit Register 0xB8 32 read-write n 0x0 0x0 DATA DATA 0 32 read-write VER Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only FEATURE_0 Standard features implemented #000000000000xxx0 FEATURE_4 Core Control and Status Registers are implemented in both MUA and MUB. #100000000000x0xx MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only PCC0 PCC PCC_0 0x0 0x0 0x204 registers n PCC_ADC0 PCC ADC0 Register 0x128 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 FRAC Peripheral Clock Divider Fraction 3 1 read-write FRAC_0 Fractional value is 0. 0 FRAC_1 Fractional value is 1. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCD Peripheral Clock Divider Select 0 3 read-write PCD_0 Divide by 1. 0 PCD_1 Divide by 2. 0x1 PCD_2 Divide by 3. 0x2 PCD_3 Divide by 4. 0x3 PCD_4 Divide by 5. 0x4 PCD_5 Divide by 6. 0x5 PCD_6 Divide by 7. 0x6 PCD_7 Divide by 8. 0x7 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_AXBS0 PCC AXBS0 Register 0x10 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_CRC0 PCC CRC0 Register 0xBC 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_DMA0 PCC DMA0 Register 0x20 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_DMAMUX0 PCC DMAMUX0 Register 0x84 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_EMVSIM0 PCC EMVSIM0 Register 0xE0 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_EWM PCC EWM Register 0x88 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_FLEXBUS PCC FLEXBUS Register 0x30 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_FLEXIO0 PCC FLEXIO0 Register 0xE4 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_I2S0 PCC I2S0 Register 0xF4 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_LPDAC0 PCC LPDAC0 Register 0x130 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_LPI2C0 PCC LPI2C0 Register 0xE8 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_LPI2C1 PCC LPI2C1 Register 0xEC 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_LPI2C2 PCC LPI2C2 Register 0xF0 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_LPIT0 PCC LPIT0 Register 0xC0 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_LPSPI0 PCC LPSPI0 Register 0xFC 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_LPSPI1 PCC LPSPI1 Register 0x100 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_LPSPI2 PCC LPSPI2 Register 0x104 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_LPUART0 PCC LPUART0 Register 0x108 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_LPUART1 PCC LPUART1 Register 0x10C 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_LPUART2 PCC LPUART2 Register 0x110 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_MSCM PCC MSCM Register 0x4 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_MUA PCC MUA Register 0x94 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_PORTA PCC PORTA Register 0x118 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_PORTB PCC PORTB Register 0x11C 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_PORTC PCC PORTC Register 0x120 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_PORTD PCC PORTD Register 0x124 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_SEMA42_0 PCC SEMA42_0 Register 0x6C 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_TPM0 PCC TPM0 Register 0xD4 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_TPM1 PCC TPM1 Register 0xD8 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_TPM2 PCC TPM2 Register 0xDC 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_TRACE PCC TRACE Register 0x200 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 FRAC Peripheral Clock Divider Fraction 3 1 read-write FRAC_0 Fractional value is 0. 0 FRAC_1 Fractional value is 1. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCD Peripheral Clock Divider Select 0 3 read-write PCD_0 Divide by 1. 0 PCD_1 Divide by 2. 0x1 PCD_2 Divide by 3. 0x2 PCD_3 Divide by 4. 0x3 PCD_4 Divide by 5. 0x4 PCD_5 Divide by 6. 0x5 PCD_6 Divide by 7. 0x6 PCD_7 Divide by 8. 0x7 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_USB0 PCC USB0 Register 0x114 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_USDHC0 PCC USDHC0 Register 0xF8 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_VREF PCC VREF Register 0x134 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_XRDC_MGR PCC XRDC_MGR Register 0x50 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_XRDC_MRC PCC XRDC_MRC Register 0x5C 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_XRDC_PAC PCC XRDC_PAC Register 0x58 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC1 PCC PCC_1 0x0 0x0 0x208 registers n PCC_CAU3 PCC CAU3 Register 0xA0 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_DMA1 PCC DMA1 Register 0x20 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_DMAMUX1 PCC DMAMUX1 Register 0x84 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_EXT_CLK PCC EXT_CLK Register 0x204 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_GPIOE PCC GPIOE Register 0x3C 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_INTMUX1 PCC INTMUX1 Register 0x88 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_LPI2C3 PCC LPI2C3 Register 0xB8 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_LPIT1 PCC LPIT1 Register 0xA8 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_LPSPI3 PCC LPSPI3 Register 0xD4 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_LPUART3 PCC LPUART3 Register 0xD8 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_MTB PCC MTB Register 0x200 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_MUB PCC MUB Register 0x90 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_PORTE PCC PORTE Register 0xDC 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_SEMA42_1 PCC SEMA42_1 Register 0x6C 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_TPM3 PCC TPM3 Register 0xB4 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PCS Peripheral Clock Source Select 24 3 read-write PCS_0 Clock is off. 0 PCS_1 Clock option 1 0x1 PCS_2 Clock option 2 0x2 PCS_3 Clock option 3 0x3 PCS_4 Clock option 4 0x4 PCS_5 Clock option 5 0x5 PCS_6 Clock option 6 0x6 PCS_7 Clock option 7 0x7 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_TRNG PCC TRNG Register 0xA4 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_XRDC_MRC PCC XRDC_MRC Register 0x5C 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PCC_XRDC_PAC PCC XRDC_PAC Register 0x58 32 read-write n 0x0 0x0 CGC Clock Gate Control 30 1 read-write CGC_0 Clock disabled 0 CGC_1 Clock enabled. The current clock selection and divider options are locked. 0x1 INUSE In use flag 29 1 read-only INUSE_0 Peripheral is not being used. 0 INUSE_1 Peripheral is being used. Software cannot modify the existing clocking configuration. 0x1 PR Present 31 1 read-only PR_0 Peripheral is not present. 0 PR_1 Peripheral is present. 0x1 PORTA PORT PCTL_PTA 0x0 0x0 0xA4 registers n PORTA 48 GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write oneToClear PCR0 Pin Control Register 0 0x0 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PFE Passive Filter Enable 4 1 read-write PFE_0 Passive input filter is disabled on the corresponding pin. 0 PFE_1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics. 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR1 Pin Control Register 1 0x4 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR10 Pin Control Register 10 0x28 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR14 Pin Control Register 14 0x38 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR15 Pin Control Register 15 0x3C 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR17 Pin Control Register 17 0x44 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR18 Pin Control Register 18 0x48 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR19 Pin Control Register 19 0x4C 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR2 Pin Control Register 2 0x8 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR20 Pin Control Register 20 0x50 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR21 Pin Control Register 21 0x54 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR22 Pin Control Register 22 0x58 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR23 Pin Control Register 23 0x5C 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR24 Pin Control Register 24 0x60 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR25 Pin Control Register 25 0x64 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR26 Pin Control Register 26 0x68 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR27 Pin Control Register 27 0x6C 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR28 Pin Control Register 28 0x70 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR3 Pin Control Register 3 0xC 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR30 Pin Control Register 30 0x78 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR31 Pin Control Register 31 0x7C 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR4 Pin Control Register 4 0x10 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR9 Pin Control Register 9 0x24 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PORTB PORT PCTL_PTB 0x0 0x0 0xA4 registers n PORTB 49 GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write oneToClear PCR0 Pin Control Register 0 0x0 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR1 Pin Control Register 1 0x4 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR11 Pin Control Register 11 0x2C 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR12 Pin Control Register 12 0x30 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR13 Pin Control Register 13 0x34 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR14 Pin Control Register 14 0x38 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR15 Pin Control Register 15 0x3C 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR16 Pin Control Register 16 0x40 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR17 Pin Control Register 17 0x44 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR18 Pin Control Register 18 0x48 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR19 Pin Control Register 19 0x4C 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR2 Pin Control Register 2 0x8 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR20 Pin Control Register 20 0x50 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR21 Pin Control Register 21 0x54 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR22 Pin Control Register 22 0x58 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR24 Pin Control Register 24 0x60 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR25 Pin Control Register 25 0x64 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR26 Pin Control Register 26 0x68 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR28 Pin Control Register 28 0x70 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR29 Pin Control Register 29 0x74 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR3 Pin Control Register 3 0xC 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR30 Pin Control Register 30 0x78 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR31 Pin Control Register 31 0x7C 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR4 Pin Control Register 4 0x10 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR5 Pin Control Register 5 0x14 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR6 Pin Control Register 6 0x18 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR7 Pin Control Register 7 0x1C 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR8 Pin Control Register 8 0x20 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR9 Pin Control Register 9 0x24 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PORTC PORT PCTL_PTC 0x0 0x0 0xA4 registers n PORTC 50 GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write oneToClear PCR0 Pin Control Register 0 0x0 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR1 Pin Control Register 1 0x4 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR10 Pin Control Register 10 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write DSE_0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0 DSE_1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0x1 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR11 Pin Control Register 11 0x2C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write DSE_0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0 DSE_1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0x1 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR12 Pin Control Register 12 0x30 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write DSE_0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0 DSE_1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0x1 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR26 Pin Control Register 26 0x68 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR27 Pin Control Register 27 0x6C 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR28 Pin Control Register 28 0x70 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR29 Pin Control Register 29 0x74 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR30 Pin Control Register 30 0x78 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR7 Pin Control Register 7 0x1C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write DSE_0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0 DSE_1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0x1 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR8 Pin Control Register 8 0x20 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write DSE_0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0 DSE_1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0x1 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR9 Pin Control Register 9 0x24 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write DSE_0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0 DSE_1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0x1 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PORTD PORT PCTL_PTD 0x0 0x0 0xCC registers n PORTD 51 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write CS_0 Digital filters are clocked by the bus clock. 0 CS_1 no description available 0x1 DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write oneToClear PCR0 Pin Control Register 0 0x0 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR1 Pin Control Register 1 0x4 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR10 Pin Control Register 10 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write DSE_0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0 DSE_1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0x1 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR11 Pin Control Register 11 0x2C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write DSE_0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0 DSE_1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0x1 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR2 Pin Control Register 2 0x8 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR3 Pin Control Register 3 0xC 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR4 Pin Control Register 4 0x10 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR5 Pin Control Register 5 0x14 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR6 Pin Control Register 6 0x18 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR7 Pin Control Register 7 0x1C 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR8 Pin Control Register 8 0x20 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write DSE_0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0 DSE_1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0x1 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR9 Pin Control Register 9 0x24 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write DSE_0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0 DSE_1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0x1 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PORTE PORT PCTL_PTE 0x0 0x0 0xA4 registers n PORTE 64 GICHR Global Interrupt Control High Register 0x8C 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only GICLR Global Interrupt Control Low Register 0x88 32 write-only n 0x0 0x0 GIWD Global Interrupt Write Data 16 16 write-only GIWE Global Interrupt Write Enable 0 16 write-only GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write oneToClear PCR0 Pin Control Register 0 0x0 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR1 Pin Control Register 1 0x4 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR10 Pin Control Register 10 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write DSE_0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0 DSE_1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0x1 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR11 Pin Control Register 11 0x2C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write DSE_0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0 DSE_1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. 0x1 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR12 Pin Control Register 12 0x30 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR13 Pin Control Register 13 0x34 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR14 Pin Control Register 14 0x38 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR15 Pin Control Register 15 0x3C 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR16 Pin Control Register 16 0x40 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR17 Pin Control Register 17 0x44 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR18 Pin Control Register 18 0x48 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR19 Pin Control Register 19 0x4C 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR2 Pin Control Register 2 0x8 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR21 Pin Control Register 21 0x54 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR22 Pin Control Register 22 0x58 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR27 Pin Control Register 27 0x6C 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR28 Pin Control Register 28 0x70 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR29 Pin Control Register 29 0x74 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR3 Pin Control Register 3 0xC 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR30 Pin Control Register 30 0x78 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR4 Pin Control Register 4 0x10 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR5 Pin Control Register 5 0x14 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR8 Pin Control Register 8 0x20 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 PCR9 Pin Control Register 9 0x24 32 read-write n 0x0 0x0 IRQC Interrupt Configuration 16 4 read-write IRQC_0 Interrupt Status Flag (ISF) is disabled. 0 IRQC_1 ISF flag and DMA request on rising edge. 0x1 IRQC_2 ISF flag and DMA request on falling edge. 0x2 IRQC_3 ISF flag and DMA request on either edge. 0x3 IRQC_5 no description available 0x5 IRQC_6 no description available 0x6 IRQC_7 no description available 0x7 IRQC_8 ISF flag and Interrupt when logic 0. 0x8 IRQC_9 ISF flag and Interrupt on rising-edge. 0x9 IRQC_10 ISF flag and Interrupt on falling-edge. 0xA IRQC_11 ISF flag and Interrupt on either edge. 0xB IRQC_12 ISF flag and Interrupt when logic 1. 0xC IRQC_13 no description available 0xD IRQC_14 no description available 0xE ISF Interrupt Status Flag 24 1 read-write oneToClear ISF_0 Configured interrupt is not detected. 0 ISF_1 no description available 0x1 LK Lock Register 15 1 read-write LK_0 Pin Control Register is not locked. 0 LK_1 Pin Control Register is locked and cannot be updated until the next system reset. 0x1 MUX Pin Mux Control 8 3 read-write MUX_0 Pin disabled (Alternative 0) (analog). 0 MUX_1 Alternative 1 (GPIO). 0x1 MUX_2 Alternative 2 (chip-specific). 0x2 MUX_3 Alternative 3 (chip-specific). 0x3 MUX_4 Alternative 4 (chip-specific). 0x4 MUX_5 Alternative 5 (chip-specific). 0x5 MUX_6 Alternative 6 (chip-specific). 0x6 MUX_7 Alternative 7 (chip-specific). 0x7 ODE Open Drain Enable 5 1 read-write ODE_0 Open drain output is disabled on the corresponding pin. 0 ODE_1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. 0x1 PE Pull Enable 1 1 read-write PE_0 no description available 0 PE_1 no description available 0x1 PS Pull Select 0 1 read-write PS_0 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0 PS_1 Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. 0x1 SRE Slew Rate Enable 2 1 read-write SRE_0 Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0 SRE_1 Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 0x1 RSIM RSIM RSIM 0x0 0x0 0x130 registers n ANA_TEST Radio Analog Test Registers 0x128 32 read-write n 0x0 0x0 XTAL_OUT_BUF_EN XTAL Output Buffer Enable 4 1 read-write ANA_TRIM Radio Analog Trim Registers 0x12C 32 read-write n 0x0 0x0 BB_LDO_LS_SPARE rmap_bb_ldo_ls_spare_hv[1:0] 0 2 read-write BB_LDO_LS_TRIM rmap_bb_ldo_ls_trim_hv[2:0] 3 3 read-write BB_LDO_LS_TRIM_0 1.20 V (Default) 0 BB_LDO_LS_TRIM_1 1.25 V 0x1 BB_LDO_LS_TRIM_2 1.28 V 0x2 BB_LDO_LS_TRIM_3 1.33 V 0x3 BB_LDO_LS_TRIM_4 1.40 V 0x4 BB_LDO_LS_TRIM_5 1.44 V 0x5 BB_LDO_LS_TRIM_6 1.50 V 0x6 BB_LDO_LS_TRIM_7 1.66 V 0x7 BB_LDO_XO_SPARE rmap_bb_ldo_xo_spare_hv[1:0] 6 2 read-write BB_LDO_XO_TRIM rmap_bb_ldo_xo_trim_hv[2:0] 8 3 read-write BB_LDO_XO_TRIM_0 1.20 V (Default) 0 BB_LDO_XO_TRIM_1 1.25 V 0x1 BB_LDO_XO_TRIM_2 1.28 V 0x2 BB_LDO_XO_TRIM_3 1.33 V 0x3 BB_LDO_XO_TRIM_4 1.40 V 0x4 BB_LDO_XO_TRIM_5 1.44 V 0x5 BB_LDO_XO_TRIM_6 1.50 V 0x6 BB_LDO_XO_TRIM_7 1.66 V 0x7 BB_XTAL_SPARE rmap_bb_xtal_spare_hv[4:0] 11 5 read-write BB_XTAL_TRIM rmap_bb_xtal_trim_hv[7:0] 16 8 read-write BG_1V_TRIM rmap_bg_1v_trim_hv[3:0] 24 4 read-write BG_1V_TRIM_0 954.14 mV 0 BG_1V_TRIM_1 959.26 mV 0x1 BG_1V_TRIM_2 964.38 mV 0x2 BG_1V_TRIM_3 969.5 mV 0x3 BG_1V_TRIM_4 974.6 mV 0x4 BG_1V_TRIM_5 979.7 mV 0x5 BG_1V_TRIM_6 984.8 mV 0x6 BG_1V_TRIM_7 989.9 mV 0x7 BG_1V_TRIM_8 995 mV (Default) 0x8 BG_1V_TRIM_9 1 V 0x9 BG_1V_TRIM_10 1.005 V 0xA BG_1V_TRIM_11 1.01 V 0xB BG_1V_TRIM_12 1.015 V 0xC BG_1V_TRIM_13 1.02 V 0xD BG_1V_TRIM_14 1.025 V 0xE BG_1V_TRIM_15 1.031 V 0xF BG_IBIAS_5U_TRIM rmap_bg_ibias_5u_trim_hv[3:0] 28 4 read-write BG_IBIAS_5U_TRIM_0 3.55 uA 0 BG_IBIAS_5U_TRIM_1 3.73 uA 0x1 BG_IBIAS_5U_TRIM_2 4.04 uA 0x2 BG_IBIAS_5U_TRIM_3 4.22 uA 0x3 BG_IBIAS_5U_TRIM_4 4.39 uA 0x4 BG_IBIAS_5U_TRIM_5 4.57 uA 0x5 BG_IBIAS_5U_TRIM_6 4.89 uA 0x6 BG_IBIAS_5U_TRIM_7 5.06 (Default) 0x7 BG_IBIAS_5U_TRIM_8 5.23 uA 0x8 BG_IBIAS_5U_TRIM_9 5.41 uA 0x9 BG_IBIAS_5U_TRIM_10 5.72 uA 0xA BG_IBIAS_5U_TRIM_11 5.9 uA 0xB BG_IBIAS_5U_TRIM_12 6.07 uA 0xC BG_IBIAS_5U_TRIM_13 6.25 uA 0xD BG_IBIAS_5U_TRIM_14 6.56 uA 0xE BG_IBIAS_5U_TRIM_15 6.74 uA 0xF CONTROL Radio System Control 0x0 32 read-write n 0x0 0x0 BLE_DSM_EXIT BLE Force Deep Sleep Mode Exit 20 1 read-write BLE_RF_POWER_REQ_EN BLE RF Power Request Enable 0 1 read-write BLE_RF_POWER_REQ_INT BLE RF Power Request Interrupt Flag 5 1 read-write oneToClear BLE_RF_POWER_REQ_INT_EN BLE RF Power Request Interrupt Enable 4 1 read-write BLE_RF_POWER_REQ_STAT BLE RF Power Request Status 1 1 read-only IPP_OBE_BLE_EARLY_WARNING IPP_OBE_BLE_EARLY_WARNING 14 1 read-write IPP_OBE_RF_ACTIVE IPP_OBE_RF_ACTIVE 15 1 read-write IPP_OBE_RF_OSC_EN IPP_OBE_RF_OSC_EN 16 1 read-write IPP_OBE_RF_PRIORITY IPP_OBE_RF_PRIORITY 19 1 read-write IPP_OBE_RF_STATUS IPP_OBE_RF_STATUS 18 1 read-write RADIO_GASKET_BYPASS_OVRD Radio Gasket Bypass Override 13 1 read-write RADIO_GASKET_BYPASS_OVRD_0 XCVR and Link Layer Register Clock is the RF Ref Osc Clock 0 RADIO_GASKET_BYPASS_OVRD_1 XCVR and Link Layer Register Clock is the SoC IPG Clock 0x1 RADIO_GASKET_BYPASS_OVRD_EN Radio Gasket Bypass Override Enable 12 1 read-write RF_OSC_EN RF Ref Osc Enable 8 1 read-write RF_OSC_READY RF Ref Osc Ready 24 1 read-only RF_OSC_READY_OVRD RF Ref Osc Ready Override 26 1 read-write RF_OSC_READY_OVRD_EN RF Ref Osc Ready Override Enable 25 1 read-write RSIM_CGC_BLE_EN BLE Clock Gate Control 27 1 read-write RSIM_CGC_BLE_EN_0 Clock disabled 0 RSIM_CGC_BLE_EN_1 Clock enabled 0x1 RSIM_CGC_GEN_EN GEN Clock Gate Control 31 1 read-write RSIM_CGC_GEN_EN_0 Clock disabled 0 RSIM_CGC_GEN_EN_1 Clock enabled 0x1 RSIM_CGC_XCVR_EN XCVR Clock Gate Control 28 1 read-write RSIM_CGC_XCVR_EN_0 Clock disabled 0 RSIM_CGC_XCVR_EN_1 Clock enabled 0x1 RSIM_CGC_ZIG_EN ZIG Clock Gate Control 29 1 read-write RSIM_CGC_ZIG_EN_0 Clock disabled 0 RSIM_CGC_ZIG_EN_1 Clock enabled 0x1 WOR_DSM_EXIT Wake on Radio Force Deep Sleep Mode Exit 21 1 read-write DSM_CONTROL Deep Sleep Timer Control 0x104 32 read-write n 0x0 0x0 DSM_MAN_FINISHED MAN Deep Sleep Time Finished 10 1 read-only DSM_MAN_READY MAN Ready for Deep Sleep Mode 8 1 read-only DSM_TIMER_CLR Deep Sleep Mode Timer Clear 27 1 read-write DSM_TIMER_EN Deep Sleep Mode Timer Enable 31 1 read-write DSM_WOR_FINISHED WOR Deep Sleep Time Finished 2 1 read-only DSM_WOR_READY WOR Ready for Deep Sleep Mode 0 1 read-only MAN_DEEP_SLEEP_STATUS MAN Deep Sleep Mode Status 9 1 read-only MAN_SLEEP_REQUEST MAN Deep Sleep Requested 12 1 read-only MAN_WAKEUP_INTERRUPT_EN MAN Deep Sleep Module Radio Wakeup Interrupt Enable 14 1 read-write MAN_WAKEUP_REQ MAN Deep Sleep Module Radio Wakeup Status 13 1 read-only MAN_WAKEUP_REQUEST_EN Enable MAN Deep Sleep Module to initiate a Radio Wakeup 11 1 read-write MAN_WAKEUP_REQ_INT Interrupt Flag from an MAN Deep Sleep Module Radio Wakeup 15 1 read-write oneToClear RF_ACTIVE_ENDS_WITH_TSM RF_ACTIVE clearing mechanism 20 1 read-only SW_RF_ACTIVE_BIT Software RF_ACTIVE Control Bit 22 1 read-write SW_RF_ACTIVE_EN Software RF_ACTIVE Control Enable 23 1 read-only SW_RF_ACTIVE_ENDS_WITH_TSM Software RF_ACTIVE clearing mechanism 21 1 read-only WIFI_COEXIST_1 RF_ACTIVE Source 16 1 read-only WIFI_COEXIST_2 RF_STATUS Source 17 1 read-only WIFI_COEXIST_3 RF_EARLY_WARNING Source 18 1 read-only WOR_DEEP_SLEEP_STATUS WOR Deep Sleep Mode Status 1 1 read-only WOR_SLEEP_REQUEST WOR Deep Sleep Requested 4 1 read-only WOR_WAKEUP_INTERRUPT_EN WOR Deep Sleep Module Radio Wakeup Interrupt Enable 6 1 read-write WOR_WAKEUP_REQ WOR Deep Sleep Module Radio Wakeup Status 5 1 read-only WOR_WAKEUP_REQUEST_EN Enable WOR Deep Sleep Module to initiate a Radio Wakeup 3 1 read-write WOR_WAKEUP_REQ_INT Interrupt Flag from an WOR Deep Sleep Module Radio Wakeup 7 1 read-write oneToClear DSM_TIMER Deep Sleep Timer 0x100 32 read-only n 0x0 0x0 DSM_TIMER Deep Sleep Mode Timer 0 24 read-only DSM_WAKEUP Deep Sleep Wakeup Sequence 0x108 32 read-write n 0x0 0x0 ACTIVE_WARNING Deep Sleep Wakeup RF Active Warning Time 12 6 read-write COARSE_DELAY Deep Sleep Wakeup Coarse Delay Time 28 4 read-write DSM_POWER_OFFSET_TIME Deep Sleep Wakeup Power Offset Time 0 10 read-write FINE_DELAY Deep Sleep Wakeup Fine Delay Time 20 6 read-write MAN_SLEEP MAN Deep Sleep Time 0x11C 32 read-write n 0x0 0x0 MAN_SLEEP_TIME MAN Deep Sleep Module Sleep Time 0 24 read-write MAN_WAKE MAN Deep Sleep Wake Time 0x120 32 read-write n 0x0 0x0 MAN_FSM_STATE MAN Deep Sleep State Machine State 28 3 read-only MAN_WAKE_TIME MAN Deep Sleep Module Wake Time 0 24 read-write MISC Radio Miscellaneous 0x10 32 read-write n 0x0 0x0 RADIO_VERSION Radio Version ID number 24 8 read-write POWER RSIM Power Control 0x14 32 read-write n 0x0 0x0 RADIO_ISO_STAT Radio Isolation Status 17 1 read-only RADIO_RUN_REQ_STAT Radio Run Request Status 21 1 read-only RADIO_STOP_ACK_STAT Radio Stop Acknowledge Status 8 1 read-only RADIO_STOP_MODE_OVRD Radio Stop Mode Override 4 3 read-write RADIO_STOP_MODE_OVRD_EN Radio Stop Mode Override Enable 7 1 read-write RADIO_STOP_MODE_STAT Radio Stop Mode Status 0 3 read-only RADIO_STOP_REQ_STAT Radio Stop Request Status 9 1 read-only RF_OSC_EN_OVRD Radio Osc Enable Override 12 1 read-write RF_OSC_EN_OVRD_EN Radio Osc Enable Override Enable 13 1 read-write RF_POWER_EN_OVRD Radio Power Enable Override 14 1 read-write RF_POWER_EN_OVRD_EN Radio Power Enable Override Enable 15 1 read-write RSIM_ISO_OVRD RSIM ISO Override 18 1 read-write RSIM_ISO_OVRD_EN RSIM ISO Override Enable 19 1 read-write RSIM_RUN_REQUEST RSIM Run Regulator Request 31 1 read-write RSIM_RUN_REQ_OVRD RSIM Run Request Override 22 1 read-write RSIM_RUN_REQ_OVRD_EN RSIM Run Request Override Enable 23 1 read-write RSIM_STOP_MODE RSIM lowest allowed Stop Mode 28 3 read-write RSIM_STOP_MODE_3 RLLS mode (Radio State Retention mode) 0x3 RSIM_STOP_MODE_7 RVLLS mode (This is the POR setting) 0x7 RSIM_STOP_REQ_OVRD Radio Stop Request Override 10 1 read-write RSIM_STOP_REQ_OVRD_EN Radio Stop Request Override Enable 11 1 read-write SPM_ISO_STAT SPM ISO Status 16 1 read-only SPM_RUN_ACK_STAT SPM Run Request Acknowledge Status 20 1 read-only SPM_RUN_REQ_ACK_OVRD SPM Run Request Acknowledge Override 26 1 read-write SPM_RUN_REQ_ACK_OVRD_EN SPM Run Request Acknowledge Override Enable 27 1 read-write SPM_STOP_ACK_STAT SPM Stop Acknowledge Status 3 1 read-only SPM_STOP_REQ_ACK_OVRD SPM Stop Request Acknowledge Override 24 1 read-write SPM_STOP_REQ_ACK_OVRD_EN SPM Stop Request Acknowledge Override Enable 25 1 read-write RF_OSC_CTRL Radio Oscillator Control 0x124 32 read-write n 0x0 0x0 BB_XTAL_ALC_COUNT_SEL rmap_bb_xtal_alc_count_sel_hv[1:0] 0 2 read-write BB_XTAL_ALC_COUNT_SEL_0 2048 (64 us @ 32 MHz) 0 BB_XTAL_ALC_COUNT_SEL_1 4096 (128 us @ 32 MHz) 0x1 BB_XTAL_ALC_COUNT_SEL_2 8192 (256 us @ 32 MHz) 0x2 BB_XTAL_ALC_COUNT_SEL_3 16384 (512 us @ 32 MHz) 0x3 BB_XTAL_ALC_ON rmap_bb_xtal_alc_on_hv 2 1 read-write BB_XTAL_COMP_BIAS rmap_bb_xtal_comp_bias_hv[4:0] 4 5 read-write BB_XTAL_DC_COUP_MODE_EN rmap_bb_xtal_dc_coup_mode_en_hv 9 1 read-write BB_XTAL_DIAGSEL rmap_bb_xtal_diagsel_hv 10 1 read-write BB_XTAL_DIG_CLK_ON rmap_bb_xtal_dig_clk_on_hv 11 1 read-write BB_XTAL_GM rmap_bb_xtal_gm_hv[4:0] 12 5 read-write BB_XTAL_ON_OVRD rmap_bb_xtal_on_ovrd_hv 17 1 read-write BB_XTAL_ON_OVRD_ON rmap_bb_xtal_on_ovrd_on_hv 18 1 read-write BB_XTAL_ON_OVRD_ON_0 rfctrl_bb_xtal_on_hv is asserted 0 BB_XTAL_ON_OVRD_ON_1 rfctrl_bb_xtal_on_ovrd_hv is asserted 0x1 BB_XTAL_READY_COUNT_SEL rmap_bb_xtal_ready_count_sel_hv[1:0] 20 2 read-write BB_XTAL_READY_COUNT_SEL_0 1024 counts (32 us @ 32 MHz) 0 BB_XTAL_READY_COUNT_SEL_1 2048 (64 us @ 32 MHz) 0x1 BB_XTAL_READY_COUNT_SEL_2 4096 (128 us @ 32 MHz) 0x2 BB_XTAL_READY_COUNT_SEL_3 8192 (256 us @ 32 MHz) 0x3 RADIO_EXT_OSC_OVRD Radio External Request for RF OSC Override 28 1 read-write RADIO_EXT_OSC_OVRD_EN Radio External Request for RF OSC Override Enable 29 1 read-write RADIO_EXT_OSC_RF_EN_SEL Radio External Request for RF OSC Select 27 1 read-write RF_NOT_ALLOWED_OVRD RF Not Allowed Override 30 1 read-write RF_NOT_ALLOWED_OVRD_EN RF Not Allowed Override Enable 31 1 read-write RF_OSC_BYPASS_EN RF Ref Osc Bypass Enable 3 1 read-write SW_CONFIG Radio Software Configuration 0x18 32 read-write n 0x0 0x0 ALLOW_DFT_RESETS Allow the DFT Reset Pin to Reset the Radio 30 1 read-write BLOCK_EXT_OSC_PWR_REQ Block External Requests for RF OSC from starting a Radio Power Wakeup Sequence 31 1 read-write BLOCK_RADIO_OUTPUTS Block Radio Outputs 29 1 read-write BLOCK_SOC_RESETS Block SoC Resets of the Radio, cleared by Radio System Reset 28 1 read-write RADIO0_INTERRUPT_EN Radio0 Interrupt Enable 24 1 read-write RADIO1_INTERRUPT_EN Radio1 Interrupt Enable 25 1 read-write RADIO_CONFIGURED_POR_RESET Radio Configuration Bit, cleared by Radio Power On Reset 0 1 read-write RADIO_CONFIGURED_SYS_RESET Radio Configuration Bit, cleared by Radio System Reset 1 1 read-write RADIO_POR_BIT Software Power On Reset for the Radio 8 1 read-write RADIO_RESET_BIT Software System Reset for the Radio 16 1 read-write RSIM_RADIO_ISO_POR_OVRD RSIM ISO_POR Override 12 1 read-write RSIM_RF_ACTIVE_OVRD RF Active Internal Override 4 1 read-write RSIM_RF_ACTIVE_OVRD_EN RF Active Internal Override Enable 5 1 read-write WAKEUP_INTERRUPT_SOURCE RSIM Wakeup Interrupt Source Selector 20 2 read-write WAKEUP_INTERRUPT_SOURCE_0 No Radio Power-On Sequence interrupt will be generated. 0 WAKEUP_INTERRUPT_SOURCE_1 A Power-On Sequence interrupt will be generated when the RF Power Request occurs, including unblocked requests from an external source to use the RF OSC. 0x1 WAKEUP_INTERRUPT_SOURCE_2 A Power-On Sequence interrupt will be generated when the RF OSC Request occurs, but not if the RF OSC request was from an external source. 0x2 WAKEUP_INTERRUPT_SOURCE_3 A Power-On Sequence interrupt will be generated when the RSIM RF Active Warning occurs 0x3 WOR_DURATION WOR Deep Sleep Duration 0x10C 32 read-only n 0x0 0x0 WOR_DSM_DURATION WOR Deep Sleep Time Elapsed 0 24 read-only WOR_WAKE WOR Deep Sleep Wake Time 0x110 32 read-write n 0x0 0x0 WOR_FSM_STATE WOR Deep Sleep State Machine State 28 3 read-only WOR_WAKE_TIME WOR Deep Sleep Module Wake Time 0 24 read-write RTC RTC RTC 0x0 0x0 0x808 registers n RTC 28 CR RTC Control Register 0x10 32 read-write n 0x0 0x0 CLKO Clock Output 9 1 read-write CLKO_0 The 32 kHz clock is output to other peripherals. 0 CLKO_1 The 32 kHz clock is not output to other peripherals. 0x1 CPE Clock Pin Enable 24 2 read-write CPE_0 The RTC_CLKOUT function is disabled. 0 CPE_1 Enable RTC_CLKOUT pin on pin 1. 0x1 CPE_2 Enable RTC_CLKOUT pin on pin 2. 0x2 CPE_3 Enable RTC_CLKOUT pin on pin 3. 0x3 CPS Clock Pin Select 5 1 read-write CPS_0 The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT. 0 CPS_1 The RTC 32.768 kHz clock is output on RTC_CLKOUT, provided it is output to other peripherals. 0x1 LPOS LPO Select 7 1 read-write LPOS_0 RTC prescaler increments using 32.768 kHz clock. 0 LPOS_1 RTC prescaler increments using 1 kHz LPO, bits [4:0] of the prescaler are ignored. 0x1 OSCE Oscillator Enable 8 1 read-write OSCE_0 32.768 kHz oscillator is disabled. 0 OSCE_1 32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize. 0x1 OSCM Oscillator Mode Select 15 1 read-write OSCM_0 Configures the 32.768kHz crystal oscillator for robust operation supporting a wide range of crystals. 0 OSCM_1 Configures the 32.768kHz crystal oscillator for low power operation supporting a more limited range of crystals. 0x1 PORS POR Select 16 2 read-write PORS_0 POR brownout enabled for 120us every 128ms. 0 PORS_1 POR brownout enabled for 120us every 64ms. 0x1 PORS_2 POR brownout enabled for 120us every 32ms. 0x2 PORS_3 POR brownout always enabled. 0x3 SC16P Oscillator 16pF Load Configure 10 1 read-write SC16P_0 Disable the load. 0 SC16P_1 Enable the additional load. 0x1 SC2P Oscillator 2pF Load Configure 13 1 read-write SC2P_0 Disable the load. 0 SC2P_1 Enable the additional load. 0x1 SC4P Oscillator 4pF Load Configure 12 1 read-write SC4P_0 Disable the load. 0 SC4P_1 Enable the additional load. 0x1 SC8P Oscillator 8pF Load Configure 11 1 read-write SC8P_0 Disable the load. 0 SC8P_1 Enable the additional load. 0x1 SUP Supervisor Access 2 1 read-write SUP_0 Non-supervisor mode write accesses are not supported and generate a bus error. 0 SUP_1 Non-supervisor mode write accesses are supported. 0x1 SWR Software Reset 0 1 read-write SWR_0 No effect. 0 SWR_1 no description available 0x1 UM Update Mode 3 1 read-write UM_0 Registers cannot be written when locked. 0 UM_1 Registers can be written when locked under limited conditions. 0x1 WPE Wakeup Pin Enable 1 1 read-write WPE_0 RTC_WAKEUP pin is disabled. 0 WPE_1 RTC_WAKEUP pin is enabled and asserts if the RTC interrupt asserts or if the wakeup pin is forced on. 0x1 WPS Wakeup Pin Select 4 1 read-write WPS_0 RTC_WAKEUP pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on. 0 WPS_1 RTC_WAKEUP pin outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals. 0x1 IER RTC Interrupt Enable Register 0x1C 32 read-write n 0x0 0x0 MOIE Monotonic Overflow Interrupt Enable 3 1 read-write MOIE_0 Monotonic overflow flag does not generate an interrupt. 0 MOIE_1 Monotonic overflow flag does generate an interrupt. 0x1 TAIE Time Alarm Interrupt Enable 2 1 read-write TAIE_0 Time alarm flag does not generate an interrupt. 0 TAIE_1 Time alarm flag does generate an interrupt. 0x1 TIIE Time Invalid Interrupt Enable 0 1 read-write TIIE_0 Time invalid flag does not generate an interrupt. 0 TIIE_1 Time invalid flag does generate an interrupt. 0x1 TOIE Time Overflow Interrupt Enable 1 1 read-write TOIE_0 Time overflow flag does not generate an interrupt. 0 TOIE_1 Time overflow flag does generate an interrupt. 0x1 TSIC Timer Seconds Interrupt Configuration 16 3 read-write TSIC_0 1 Hz. 0 TSIC_1 2 Hz. 0x1 TSIC_2 4 Hz. 0x2 TSIC_3 8 Hz. 0x3 TSIC_4 16 Hz. 0x4 TSIC_5 32 Hz. 0x5 TSIC_6 64 Hz. 0x6 TSIC_7 128 Hz. 0x7 TSIE Time Seconds Interrupt Enable 4 1 read-write TSIE_0 Seconds interrupt is disabled. 0 TSIE_1 Seconds interrupt is enabled. 0x1 WPON Wakeup Pin On 7 1 read-write WPON_0 No effect. 0 WPON_1 If the RTC_WAKEUP pin is enabled, then the pin will assert. 0x1 LR RTC Lock Register 0x18 32 read-write n 0x0 0x0 CRL Control Register Lock 4 1 read-write CRL_0 Control Register is locked and writes are ignored. 0 CRL_1 Control Register is not locked and writes complete as normal. 0x1 LRL Lock Register Lock 6 1 read-write LRL_0 Lock Register is locked and writes are ignored. 0 LRL_1 Lock Register is not locked and writes complete as normal. 0x1 MCHL Monotonic Counter High Lock 11 1 read-write MCHL_0 Monotonic Counter High Register is locked and writes are ignored. 0 MCHL_1 Monotonic Counter High Register is not locked and writes complete as normal. 0x1 MCLL Monotonic Counter Low Lock 10 1 read-write MCLL_0 Monotonic Counter Low Register is locked and writes are ignored. 0 MCLL_1 Monotonic Counter Low Register is not locked and writes complete as normal. 0x1 MEL Monotonic Enable Lock 9 1 read-write MEL_0 Monotonic Enable Register is locked and writes are ignored. 0 MEL_1 Monotonic Enable Register is not locked and writes complete as normal. 0x1 PCL Pin Configuration Lock 16 4 read-write SRL Status Register Lock 5 1 read-write SRL_0 Status Register is locked and writes are ignored. 0 SRL_1 Status Register is not locked and writes complete as normal. 0x1 TCL Time Compensation Lock 3 1 read-write TCL_0 Time Compensation Register is locked and writes are ignored. 0 TCL_1 Time Compensation Register is not locked and writes complete as normal. 0x1 TDL Tamper Detect Lock 13 1 read-write TDL_0 Tamper Detect Register is locked and writes are ignored. 0 TDL_1 Tamper Detect Register is not locked and writes complete as normal. 0x1 TIL Tamper Interrupt Lock 15 1 read-write TIL_0 Tamper Interrupt Register is locked and writes are ignored. 0 TIL_1 Tamper Interrupt Register is not locked and writes complete as normal. 0x1 TTSL Tamper Time Seconds Lock 8 1 read-write TTSL_0 Tamper Time Seconds Register is locked and writes are ignored. 0 TTSL_1 Tamper Time Seconds Register is not locked and writes complete as normal. 0x1 MCHR RTC Monotonic Counter High Register 0x2C 32 read-write n 0x0 0x0 MCH Monotonic Counter High 0 32 read-write MCLR RTC Monotonic Counter Low Register 0x28 32 read-write n 0x0 0x0 MCL Monotonic Counter Low 0 32 read-write MER RTC Monotonic Enable Register 0x24 32 read-write n 0x0 0x0 MCE Monotonic Counter Enable 4 1 read-write MCE_0 Writes to the monotonic counter load the counter with the value written. 0 MCE_1 Writes to the monotonic counter increment the counter. 0x1 PCR0 RTC Pin Configuration Register 0x40 32 read-write n 0x0 0x0 TFE Tamper Filter Enable 26 1 read-write TFE_0 Input filter is disabled on the tamper pin. 0 TFE_1 Input filter is enabled on the tamper pin. 0x1 TPE Tamper Pull Enable 24 1 read-write TPE_0 Pull resistor is disabled on tamper pin. 0 TPE_1 Pull resistor is enabled on tamper pin. 0x1 TPID Tamper Pin Input Data 31 1 read-only TPID_0 Tamper pin input data is logic zero. 0 TPID_1 Tamper pin input data is logic one. 0x1 TPP Tamper Pin Polarity 27 1 read-write TPP_0 Tamper pin is active high. 0 TPP_1 Tamper pin is active low. 0x1 TPS Tamper Pull Select 25 1 read-write TPS_0 Tamper pin pull resistor direction will assert the tamper pin. 0 TPS_1 Tamper pin pull resistor direction will negate the tamper pin. 0x1 PCR1 RTC Pin Configuration Register 0x44 32 read-write n 0x0 0x0 TFE Tamper Filter Enable 26 1 read-write TFE_0 Input filter is disabled on the tamper pin. 0 TFE_1 Input filter is enabled on the tamper pin. 0x1 TPE Tamper Pull Enable 24 1 read-write TPE_0 Pull resistor is disabled on tamper pin. 0 TPE_1 Pull resistor is enabled on tamper pin. 0x1 TPID Tamper Pin Input Data 31 1 read-only TPID_0 Tamper pin input data is logic zero. 0 TPID_1 Tamper pin input data is logic one. 0x1 TPP Tamper Pin Polarity 27 1 read-write TPP_0 Tamper pin is active high. 0 TPP_1 Tamper pin is active low. 0x1 TPS Tamper Pull Select 25 1 read-write TPS_0 Tamper pin pull resistor direction will assert the tamper pin. 0 TPS_1 Tamper pin pull resistor direction will negate the tamper pin. 0x1 PCR2 RTC Pin Configuration Register 0x48 32 read-write n 0x0 0x0 TFE Tamper Filter Enable 26 1 read-write TFE_0 Input filter is disabled on the tamper pin. 0 TFE_1 Input filter is enabled on the tamper pin. 0x1 TPE Tamper Pull Enable 24 1 read-write TPE_0 Pull resistor is disabled on tamper pin. 0 TPE_1 Pull resistor is enabled on tamper pin. 0x1 TPID Tamper Pin Input Data 31 1 read-only TPID_0 Tamper pin input data is logic zero. 0 TPID_1 Tamper pin input data is logic one. 0x1 TPP Tamper Pin Polarity 27 1 read-write TPP_0 Tamper pin is active high. 0 TPP_1 Tamper pin is active low. 0x1 TPS Tamper Pull Select 25 1 read-write TPS_0 Tamper pin pull resistor direction will assert the tamper pin. 0 TPS_1 Tamper pin pull resistor direction will negate the tamper pin. 0x1 PCR3 RTC Pin Configuration Register 0x4C 32 read-write n 0x0 0x0 TFE Tamper Filter Enable 26 1 read-write TFE_0 Input filter is disabled on the tamper pin. 0 TFE_1 Input filter is enabled on the tamper pin. 0x1 TPE Tamper Pull Enable 24 1 read-write TPE_0 Pull resistor is disabled on tamper pin. 0 TPE_1 Pull resistor is enabled on tamper pin. 0x1 TPID Tamper Pin Input Data 31 1 read-only TPID_0 Tamper pin input data is logic zero. 0 TPID_1 Tamper pin input data is logic one. 0x1 TPP Tamper Pin Polarity 27 1 read-write TPP_0 Tamper pin is active high. 0 TPP_1 Tamper pin is active low. 0x1 TPS Tamper Pull Select 25 1 read-write TPS_0 Tamper pin pull resistor direction will assert the tamper pin. 0 TPS_1 Tamper pin pull resistor direction will negate the tamper pin. 0x1 PCR[0] RTC Pin Configuration Register 0x80 32 read-write n 0x0 0x0 TFE Tamper Filter Enable 26 1 read-write TFE_0 Input filter is disabled on the tamper pin. 0 TFE_1 Input filter is enabled on the tamper pin. 0x1 TPE Tamper Pull Enable 24 1 read-write TPE_0 Pull resistor is disabled on tamper pin. 0 TPE_1 Pull resistor is enabled on tamper pin. 0x1 TPID Tamper Pin Input Data 31 1 read-only TPID_0 Tamper pin input data is logic zero. 0 TPID_1 Tamper pin input data is logic one. 0x1 TPP Tamper Pin Polarity 27 1 read-write TPP_0 Tamper pin is active high. 0 TPP_1 Tamper pin is active low. 0x1 TPS Tamper Pull Select 25 1 read-write TPS_0 Tamper pin pull resistor direction will assert the tamper pin. 0 TPS_1 Tamper pin pull resistor direction will negate the tamper pin. 0x1 PCR[1] RTC Pin Configuration Register 0xC4 32 read-write n 0x0 0x0 TFE Tamper Filter Enable 26 1 read-write TFE_0 Input filter is disabled on the tamper pin. 0 TFE_1 Input filter is enabled on the tamper pin. 0x1 TPE Tamper Pull Enable 24 1 read-write TPE_0 Pull resistor is disabled on tamper pin. 0 TPE_1 Pull resistor is enabled on tamper pin. 0x1 TPID Tamper Pin Input Data 31 1 read-only TPID_0 Tamper pin input data is logic zero. 0 TPID_1 Tamper pin input data is logic one. 0x1 TPP Tamper Pin Polarity 27 1 read-write TPP_0 Tamper pin is active high. 0 TPP_1 Tamper pin is active low. 0x1 TPS Tamper Pull Select 25 1 read-write TPS_0 Tamper pin pull resistor direction will assert the tamper pin. 0 TPS_1 Tamper pin pull resistor direction will negate the tamper pin. 0x1 PCR[2] RTC Pin Configuration Register 0x10C 32 read-write n 0x0 0x0 TFE Tamper Filter Enable 26 1 read-write TFE_0 Input filter is disabled on the tamper pin. 0 TFE_1 Input filter is enabled on the tamper pin. 0x1 TPE Tamper Pull Enable 24 1 read-write TPE_0 Pull resistor is disabled on tamper pin. 0 TPE_1 Pull resistor is enabled on tamper pin. 0x1 TPID Tamper Pin Input Data 31 1 read-only TPID_0 Tamper pin input data is logic zero. 0 TPID_1 Tamper pin input data is logic one. 0x1 TPP Tamper Pin Polarity 27 1 read-write TPP_0 Tamper pin is active high. 0 TPP_1 Tamper pin is active low. 0x1 TPS Tamper Pull Select 25 1 read-write TPS_0 Tamper pin pull resistor direction will assert the tamper pin. 0 TPS_1 Tamper pin pull resistor direction will negate the tamper pin. 0x1 PCR[3] RTC Pin Configuration Register 0x158 32 read-write n 0x0 0x0 TFE Tamper Filter Enable 26 1 read-write TFE_0 Input filter is disabled on the tamper pin. 0 TFE_1 Input filter is enabled on the tamper pin. 0x1 TPE Tamper Pull Enable 24 1 read-write TPE_0 Pull resistor is disabled on tamper pin. 0 TPE_1 Pull resistor is enabled on tamper pin. 0x1 TPID Tamper Pin Input Data 31 1 read-only TPID_0 Tamper pin input data is logic zero. 0 TPID_1 Tamper pin input data is logic one. 0x1 TPP Tamper Pin Polarity 27 1 read-write TPP_0 Tamper pin is active high. 0 TPP_1 Tamper pin is active low. 0x1 TPS Tamper Pull Select 25 1 read-write TPS_0 Tamper pin pull resistor direction will assert the tamper pin. 0 TPS_1 Tamper pin pull resistor direction will negate the tamper pin. 0x1 RAR RTC Read Access Register 0x804 32 read-write n 0x0 0x0 CRR Control Register Read 4 1 read-write CRR_0 Reads to the Control Register are ignored. 0 CRR_1 Reads to the Control Register complete as normal. 0x1 IERR Interrupt Enable Register Read 7 1 read-write IERR_0 Reads to the Interrupt Enable Register are ignored. 0 IERR_1 Reads to the Interrupt Enable Register complete as normal. 0x1 LRR Lock Register Read 6 1 read-write LRR_0 Reads to the Lock Register are ignored. 0 LRR_1 Reads to the Lock Register complete as normal. 0x1 MCHR Monotonic Counter High Read 11 1 read-write MCHR_0 Reads to the Monotonic Counter High Register are ignored. 0 MCHR_1 Reads to the Monotonic Counter High Register complete as normal. 0x1 MCLR Monotonic Counter Low Read 10 1 read-write MCLR_0 Reads to the Monotonic Counter Low Register are ignored. 0 MCLR_1 Reads to the Monotonic Counter Low Register complete as normal. 0x1 MERR Monotonic Enable Register Read 9 1 read-write MERR_0 Reads to the Monotonic Enable Register are ignored. 0 MERR_1 Reads to the Monotonic Enable Register complete as normal. 0x1 PCRR Pin Configuration Register Read 16 4 read-write SRR Status Register Read 5 1 read-write SRR_0 Reads to the Status Register are ignored. 0 SRR_1 Reads to the Status Register complete as normal. 0x1 TARR Time Alarm Register Read 2 1 read-write TARR_0 Reads to the Time Alarm Register are ignored. 0 TARR_1 Reads to the Time Alarm Register complete as normal. 0x1 TCRR Time Compensation Register Read 3 1 read-write TCRR_0 Reads to the Time Compensation Register are ignored. 0 TCRR_1 Reads to the Time Compensation Register complete as normal. 0x1 TDRR Tamper Detect Register Read 13 1 read-write TDRR_0 Reads to the Tamper Detect Register are ignored. 0 TDRR_1 Reads to the Tamper Detect Register complete as normal. 0x1 TIRR Tamper Interrupt Register Read 15 1 read-write TIRR_0 Reads to the Tamper Interrupt Register are ignored. 0 TIRR_1 Reads to the Tamper Interrupt Register complete as normal. 0x1 TPRR Time Prescaler Register Read 1 1 read-write TPRR_0 Reads to the Time Pprescaler Register are ignored. 0 TPRR_1 Reads to the Time Prescaler Register complete as normal. 0x1 TSRR Time Seconds Register Read 0 1 read-write TSRR_0 Reads to the Time Seconds Register are ignored. 0 TSRR_1 Reads to the Time Seconds Register complete as normal. 0x1 TTSR Tamper Time Seconds Read 8 1 read-write TTSR_0 Reads to the Tamper Time Seconds Register are ignored. 0 TTSR_1 Reads to the Tamper Time Seconds Register complete as normal. 0x1 SR RTC Status Register 0x14 32 read-write n 0x0 0x0 MOF Monotonic Overflow Flag 3 1 read-only MOF_0 Monotonic counter overflow has not occurred. 0 MOF_1 Monotonic counter overflow has occurred and monotonic counter is read as zero. 0x1 TAF Time Alarm Flag 2 1 read-only TAF_0 Time alarm has not occurred. 0 TAF_1 Time alarm has occurred. 0x1 TCE Time Counter Enable 4 1 read-write TCE_0 Time counter is disabled. 0 TCE_1 Time counter is enabled. 0x1 TIDF Tamper Interrupt Detect Flag 7 1 read-only TIDF_0 Tamper interrupt has not asserted. 0 TIDF_1 Tamper interrupt has asserted. 0x1 TIF Time Invalid Flag 0 1 read-only TIF_0 Time is valid. 0 TIF_1 Time is invalid and time counter is read as zero. 0x1 TOF Time Overflow Flag 1 1 read-only TOF_0 Time overflow has not occurred. 0 TOF_1 Time overflow has occurred and time counter is read as zero. 0x1 TAR RTC Time Alarm Register 0x8 32 read-write n 0x0 0x0 TAR Time Alarm Register 0 32 read-write TCR RTC Time Compensation Register 0xC 32 read-write n 0x0 0x0 CIC Compensation Interval Counter 24 8 read-only CIR Compensation Interval Register 8 8 read-write TCR Time Compensation Register 0 8 read-write TCR_0 Time Prescaler Register overflows every 32768 clock cycles. 0 TCR_1 Time Prescaler Register overflows every 32767 clock cycles. 0x1 TCR_126 Time Prescaler Register overflows every 32642 clock cycles. 0x7E TCR_127 Time Prescaler Register overflows every 32641 clock cycles. 0x7F TCR_128 Time Prescaler Register overflows every 32896 clock cycles. 0x80 TCR_129 Time Prescaler Register overflows every 32895 clock cycles. 0x81 TCR_255 Time Prescaler Register overflows every 32769 clock cycles. 0xFF TCV Time Compensation Value 16 8 read-only TDR RTC Tamper Detect Register 0x34 32 read-write n 0x0 0x0 FSF Flash Security Flag 6 1 read-write oneToClear FSF_0 Tamper not detected. 0 FSF_1 Flash security tamper detected. 0x1 LCTF Loss of Clock Tamper Flag 4 1 read-write oneToClear LCTF_0 Tamper not detected. 0 LCTF_1 Loss of Clock tamper detected. 0x1 STF Security Tamper Flag 5 1 read-write oneToClear STF_0 Tamper not detected. 0 STF_1 Security module tamper detected. 0x1 TMF Test Mode Flag 7 1 read-write oneToClear TMF_0 Tamper not detected. 0 TMF_1 Test mode tamper detected. 0x1 TPF Tamper Pin Flag 16 4 read-write oneToClear TIR RTC Tamper Interrupt Register 0x3C 32 read-write n 0x0 0x0 FSIE Flash Security Interrupt Enable 6 1 read-write FSIE_0 Interupt disabled. 0 FSIE_1 An interrupt is generated when the flash security flag is set. 0x1 LCIE Loss of Clock Interrupt Enable 4 1 read-write LCIE_0 Interupt disabled. 0 LCIE_1 An interrupt is generated when the loss of clock flag is set. 0x1 SIE Security Module Interrupt Enable 5 1 read-write SIE_0 Interupt disabled. 0 SIE_1 An interrupt is generated when the security module flag is set. 0x1 TMIE Test Mode Interrupt Enable 7 1 read-write TMIE_0 Interupt disabled. 0 TMIE_1 An interrupt is generated when the test mode flag is set. 0x1 TPIE Tamper Pin Interrupt Enable 16 4 read-write TPR RTC Time Prescaler Register 0x4 32 read-write n 0x0 0x0 TPR Time Prescaler Register 0 16 read-write TSR RTC Time Seconds Register 0x0 32 read-write n 0x0 0x0 TSR Time Seconds Register 0 32 read-write TTSR RTC Tamper Time Seconds Register 0x20 32 read-only n 0x0 0x0 TTS Tamper Time Seconds 0 32 read-only WAR RTC Write Access Register 0x800 32 read-write n 0x0 0x0 CRW Control Register Write 4 1 read-write CRW_0 Writes to the Control Register are ignored. 0 CRW_1 Writes to the Control Register complete as normal. 0x1 IERW Interrupt Enable Register Write 7 1 read-write IERW_0 Writes to the Interupt Enable Register are ignored. 0 IERW_1 Writes to the Interrupt Enable Register complete as normal. 0x1 LRW Lock Register Write 6 1 read-write LRW_0 Writes to the Lock Register are ignored. 0 LRW_1 Writes to the Lock Register complete as normal. 0x1 MCHW Monotonic Counter High Write 11 1 read-write MCHW_0 Writes to the Monotonic Counter High Register are ignored. 0 MCHW_1 Writes to the Monotonic Counter High Register complete as normal. 0x1 MCLW Monotonic Counter Low Write 10 1 read-write MCLW_0 Writes to the Monotonic Counter Low Register are ignored. 0 MCLW_1 Writes to the Monotonic Counter Low Register complete as normal. 0x1 MERW Monotonic Enable Register Write 9 1 read-write MERW_0 Writes to the Monotonic Enable Register are ignored. 0 MERW_1 Writes to the Monotonic Enable Register complete as normal. 0x1 PCRW Pin Configuration Register Write 16 4 read-write SRW Status Register Write 5 1 read-write SRW_0 Writes to the Status Register are ignored. 0 SRW_1 Writes to the Status Register complete as normal. 0x1 TARW Time Alarm Register Write 2 1 read-write TARW_0 Writes to the Time Alarm Register are ignored. 0 TARW_1 Writes to the Time Alarm Register complete as normal. 0x1 TCRW Time Compensation Register Write 3 1 read-write TCRW_0 Writes to the Time Compensation Register are ignored. 0 TCRW_1 Writes to the Time Compensation Register complete as normal. 0x1 TDRW Tamper Detect Register Write 13 1 read-write TDRW_0 Writes to the Tamper Detect Register are ignored. 0 TDRW_1 Writes to the Tamper Detect Register complete as normal. 0x1 TIRW Tamper Interrupt Register Write 15 1 read-write TIRW_0 Writes to the Tamper Interrupt Register are ignored. 0 TIRW_1 Writes to the Tamper Interrupt Register complete as normal. 0x1 TPRW Time Prescaler Register Write 1 1 read-write TPRW_0 Writes to the Time Prescaler Register are ignored. 0 TPRW_1 Writes to the Time Prescaler Register complete as normal. 0x1 TSRW Time Seconds Register Write 0 1 read-write TSRW_0 Writes to the Time Seconds Register are ignored. 0 TSRW_1 Writes to the Time Seconds Register complete as normal. 0x1 TTSW Tamper Time Seconds Write 8 1 read-write TTSW_0 Writes to the Tamper Time Seconds Register are ignored. 0 TTSW_1 Writes to the Tamper Time Seconds Register complete as normal. 0x1 SCG SCG SCG 0x0 0x0 0x518 registers n SCG 26 CLKOUTCNFG SCG CLKOUT Configuration Register 0x20 32 read-write n 0x0 0x0 CLKOUTSEL SCG Clkout Select 24 4 read-write CLKOUTSEL_0 no description available 0 CLKOUTSEL_1 no description available 0x1 CLKOUTSEL_2 no description available 0x2 CLKOUTSEL_3 no description available 0x3 CLKOUTSEL_4 no description available 0x4 CLKOUTSEL_5 no description available 0x5 CSR Clock Status Register 0x10 32 read-only n 0x0 0x0 DIVBUS Bus Clock Divide Ratio 4 4 read-only DIVBUS_0 Divide-by-1 0 DIVBUS_1 Divide-by-2 0x1 DIVBUS_2 Divide-by-3 0x2 DIVBUS_3 Divide-by-4 0x3 DIVBUS_4 Divide-by-5 0x4 DIVBUS_5 Divide-by-6 0x5 DIVBUS_6 Divide-by-7 0x6 DIVBUS_7 Divide-by-8 0x7 DIVBUS_8 Divide-by-9 0x8 DIVBUS_9 Divide-by-10 0x9 DIVBUS_10 Divide-by-11 0xA DIVBUS_11 Divide-by-12 0xB DIVBUS_12 Divide-by-13 0xC DIVBUS_13 Divide-by-14 0xD DIVBUS_14 Divide-by-15 0xE DIVBUS_15 Divide-by-16 0xF DIVCORE Core Clock Divide Ratio 16 4 read-only DIVCORE_0 Divide-by-1 0 DIVCORE_1 Divide-by-2 0x1 DIVCORE_2 Divide-by-3 0x2 DIVCORE_3 Divide-by-4 0x3 DIVCORE_4 Divide-by-5 0x4 DIVCORE_5 Divide-by-6 0x5 DIVCORE_6 Divide-by-7 0x6 DIVCORE_7 Divide-by-8 0x7 DIVCORE_8 Divide-by-9 0x8 DIVCORE_9 Divide-by-10 0x9 DIVCORE_10 Divide-by-11 0xA DIVCORE_11 Divide-by-12 0xB DIVCORE_12 Divide-by-13 0xC DIVCORE_13 Divide-by-14 0xD DIVCORE_14 Divide-by-15 0xE DIVCORE_15 Divide-by-16 0xF DIVEXT External Clock Divide Ratio 8 4 read-only DIVEXT_0 Divide-by-1 0 DIVEXT_1 Divide-by-2 0x1 DIVEXT_2 Divide-by-3 0x2 DIVEXT_3 Divide-by-4 0x3 DIVEXT_4 Divide-by-5 0x4 DIVEXT_5 Divide-by-6 0x5 DIVEXT_6 Divide-by-7 0x6 DIVEXT_7 Divide-by-8 0x7 DIVEXT_8 Divide-by-9 0x8 DIVEXT_9 Divide-by-10 0x9 DIVEXT_10 Divide-by-11 0xA DIVEXT_11 Divide-by-12 0xB DIVEXT_12 Divide-by-13 0xC DIVEXT_13 Divide-by-14 0xD DIVEXT_14 Divide-by-15 0xE DIVEXT_15 Divide-by-16 0xF DIVSLOW Slow Clock Divide Ratio 0 4 read-only DIVSLOW_1 Divide-by-2 0x1 DIVSLOW_2 Divide-by-3 0x2 DIVSLOW_3 Divide-by-4 0x3 DIVSLOW_4 Divide-by-5 0x4 DIVSLOW_5 Divide-by-6 0x5 DIVSLOW_6 Divide-by-7 0x6 DIVSLOW_7 Divide-by-8 0x7 DIVSLOW_8 no description available 0x8 DIVSLOW_9 no description available 0x9 DIVSLOW_10 no description available 0xA DIVSLOW_11 no description available 0xB DIVSLOW_12 no description available 0xC DIVSLOW_13 no description available 0xD DIVSLOW_14 no description available 0xE DIVSLOW_15 no description available 0xF SCS System Clock Source 24 4 read-only SCS_1 no description available 0x1 SCS_2 no description available 0x2 SCS_3 no description available 0x3 SCS_4 no description available 0x4 SCS_5 no description available 0x5 FIRCCFG Fast IRC Configuration Register 0x308 32 read-write n 0x0 0x0 RANGE Frequency Range 0 2 read-write RANGE_0 Fast IRC is trimmed to 48 MHz 0 RANGE_1 Fast IRC is trimmed to 52 MHz 0x1 RANGE_2 Fast IRC is trimmed to 56 MHz 0x2 RANGE_3 Fast IRC is trimmed to 60 MHz 0x3 FIRCCSR Fast IRC Control Status Register 0x300 32 read-write n 0x0 0x0 FIRCEN Fast IRC Enable 0 1 read-write FIRCEN_0 Fast IRC is disabled 0 FIRCEN_1 Fast IRC is enabled 0x1 FIRCERR Fast IRC Clock Error 26 1 read-write oneToClear FIRCERR_0 Error not detected with the Fast IRC trimming. 0 FIRCERR_1 Error detected with the Fast IRC trimming. 0x1 FIRCLPEN Fast IRC Low Power Enable 2 1 read-write FIRCLPEN_0 Fast IRC is disabled in VLP modes 0 FIRCLPEN_1 Fast IRC is enabled in VLP modes 0x1 FIRCREGOFF Fast IRC Regulator Enable 3 1 read-write FIRCREGOFF_0 Fast IRC Regulator is enabled. 0 FIRCREGOFF_1 Fast IRC Regulator is disabled. 0x1 FIRCSEL Fast IRC Selected status 25 1 read-only FIRCSEL_0 Fast IRC is not the system clock source 0 FIRCSEL_1 Fast IRC is the system clock source 0x1 FIRCSTEN Fast IRC Stop Enable 1 1 read-write FIRCSTEN_0 Fast IRC is disabled in Stop modes. 0 FIRCSTEN_1 Fast IRC is enabled in Stop modes 0x1 FIRCTREN Fast IRC Trim Enable 8 1 read-write FIRCTREN_0 Disable trimming Fast IRC to an external clock source 0 FIRCTREN_1 Enable trimming Fast IRC to an external clock source 0x1 FIRCTRUP Fast IRC Trim Update 9 1 read-write FIRCTRUP_0 Disable Fast IRC trimming updates 0 FIRCTRUP_1 Enable Fast IRC trimming updates 0x1 FIRCVLD Fast IRC Valid status 24 1 read-only FIRCVLD_0 Fast IRC is not enabled or clock is not valid. 0 FIRCVLD_1 Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the FIRC analog. 0x1 LK Lock Register 23 1 read-write LK_0 Control Status Register can be written. 0 LK_1 Control Status Register cannot be written. 0x1 FIRCDIV Fast IRC Divide Register 0x304 32 read-write n 0x0 0x0 FIRCDIV1 Fast IRC Clock Divide 1 0 3 read-write FIRCDIV1_0 Output disabled 0 FIRCDIV1_1 Divide by 1 0x1 FIRCDIV1_2 Divide by 2 0x2 FIRCDIV1_3 Divide by 4 0x3 FIRCDIV1_4 Divide by 8 0x4 FIRCDIV1_5 Divide by 16 0x5 FIRCDIV1_6 Divide by 32 0x6 FIRCDIV1_7 Divide by 64 0x7 FIRCDIV2 Fast IRC Clock Divide 2 8 3 read-write FIRCDIV2_0 Output disabled 0 FIRCDIV2_1 Divide by 1 0x1 FIRCDIV2_2 Divide by 2 0x2 FIRCDIV2_3 Divide by 4 0x3 FIRCDIV2_4 Divide by 8 0x4 FIRCDIV2_5 Divide by 16 0x5 FIRCDIV2_6 Divide by 32 0x6 FIRCDIV2_7 Divide by 64 0x7 FIRCDIV3 Fast IRC Clock Divider 3 16 3 read-write FIRCDIV3_0 Clock disabled 0 FIRCDIV3_1 Divide by 1 0x1 FIRCDIV3_2 Divide by 2 0x2 FIRCDIV3_3 Divide by 4 0x3 FIRCDIV3_4 Divide by 8 0x4 FIRCDIV3_5 Divide by 16 0x5 FIRCDIV3_6 Divide by 32 0x6 FIRCDIV3_7 Divide by 64 0x7 FIRCSTAT Fast IRC Status Register 0x318 32 read-write n 0x0 0x0 TRIMCOAR Trim Coarse 8 6 read-write TRIMFINE Trim Fine Status 0 7 read-write FIRCTCFG Fast IRC Trim Configuration Register 0x30C 32 read-write n 0x0 0x0 TRIMDIV Fast IRC Trim Predivide 8 3 read-write TRIMDIV_0 Divide by 1 0 TRIMDIV_1 Divide by 128 0x1 TRIMDIV_2 Divide by 256 0x2 TRIMDIV_3 Divide by 512 0x3 TRIMDIV_4 Divide by 1024 0x4 TRIMDIV_5 Divide by 2048 0x5 TRIMSRC Trim Source 0 2 read-write TRIMSRC_2 no description available 0x2 TRIMSRC_3 no description available 0x3 HCCR HSRUN Clock Control Register 0x1C 32 read-write n 0x0 0x0 DIVBUS Bus Clock Divide Ratio 4 4 read-write DIVBUS_0 Divide-by-1 0 DIVBUS_1 Divide-by-2 0x1 DIVBUS_2 Divide-by-3 0x2 DIVBUS_3 Divide-by-4 0x3 DIVBUS_4 Divide-by-5 0x4 DIVBUS_5 Divide-by-6 0x5 DIVBUS_6 Divide-by-7 0x6 DIVBUS_7 Divide-by-8 0x7 DIVBUS_8 Divide-by-9 0x8 DIVBUS_9 Divide-by-10 0x9 DIVBUS_10 Divide-by-11 0xA DIVBUS_11 Divide-by-12 0xB DIVBUS_12 Divide-by-13 0xC DIVBUS_13 Divide-by-14 0xD DIVBUS_14 Divide-by-15 0xE DIVBUS_15 Divide-by-16 0xF DIVCORE Core Clock Divide Ratio 16 4 read-write DIVCORE_0 Divide-by-1 0 DIVCORE_1 Divide-by-2 0x1 DIVCORE_2 Divide-by-3 0x2 DIVCORE_3 Divide-by-4 0x3 DIVCORE_4 Divide-by-5 0x4 DIVCORE_5 Divide-by-6 0x5 DIVCORE_6 Divide-by-7 0x6 DIVCORE_7 Divide-by-8 0x7 DIVCORE_8 Divide-by-9 0x8 DIVCORE_9 Divide-by-10 0x9 DIVCORE_10 Divide-by-11 0xA DIVCORE_11 Divide-by-12 0xB DIVCORE_12 Divide-by-13 0xC DIVCORE_13 Divide-by-14 0xD DIVCORE_14 Divide-by-15 0xE DIVCORE_15 Divide-by-16 0xF DIVEXT External Clock Divide Ratio 8 4 read-write DIVEXT_0 Divide-by-1 0 DIVEXT_1 Divide-by-2 0x1 DIVEXT_2 Divide-by-3 0x2 DIVEXT_3 Divide-by-4 0x3 DIVEXT_4 Divide-by-5 0x4 DIVEXT_5 Divide-by-6 0x5 DIVEXT_6 Divide-by-7 0x6 DIVEXT_7 Divide-by-8 0x7 DIVEXT_8 Divide-by-9 0x8 DIVEXT_9 Divide-by-10 0x9 DIVEXT_10 Divide-by-11 0xA DIVEXT_11 Divide-by-12 0xB DIVEXT_12 Divide-by-13 0xC DIVEXT_13 Divide-by-14 0xD DIVEXT_14 Divide-by-15 0xE DIVEXT_15 Divide-by-16 0xF DIVSLOW Slow Clock Divide Ratio 0 4 read-write DIVSLOW_1 Divide-by-2 0x1 DIVSLOW_2 Divide-by-3 0x2 DIVSLOW_3 Divide-by-4 0x3 DIVSLOW_4 Divide-by-5 0x4 DIVSLOW_5 Divide-by-6 0x5 DIVSLOW_6 Divide-by-7 0x6 DIVSLOW_7 Divide-by-8 0x7 DIVSLOW_8 no description available 0x8 DIVSLOW_9 no description available 0x9 DIVSLOW_10 no description available 0xA DIVSLOW_11 no description available 0xB DIVSLOW_12 no description available 0xC DIVSLOW_13 no description available 0xD DIVSLOW_14 no description available 0xE DIVSLOW_15 no description available 0xF SCS System Clock Source 24 4 read-write SCS_1 no description available 0x1 SCS_2 no description available 0x2 SCS_3 no description available 0x3 SCS_4 no description available 0x4 SCS_5 no description available 0x5 LPFLLCFG Low Power FLL Configuration Register 0x508 32 read-write n 0x0 0x0 FSEL Frequency Select 0 2 read-write FSEL_0 LPFLL is trimmed to 48 MHz. 0 FSEL_1 LPFLL is trimmed to 72 MHz. 0x1 LPFLLCSR Low Power FLL Control Status Register 0x500 32 read-write n 0x0 0x0 LK Lock Register 23 1 read-write LK_0 Control Status Register can be written. 0 LK_1 Control Status Register cannot be written. 0x1 LPFLLCM LPFLL Clock Monitor 16 1 read-write LPFLLCM_0 LPFLL Clock Monitor is disabled 0 LPFLLCM_1 LPFLL Clock Monitor is enabled 0x1 LPFLLCMRE LPFLL Clock Monitor ResetEnable 17 1 read-write LPFLLCMRE_0 Clock Monitor generates interrupt when error detected 0 LPFLLCMRE_1 Clock Monitor generates reset when error detected 0x1 LPFLLEN LPFLL Enable 0 1 read-write LPFLLEN_0 LPFLL is disabled 0 LPFLLEN_1 LPFLL is enabled 0x1 LPFLLERR LPFLL Clock Error 26 1 read-write oneToClear LPFLLERR_0 Error not detected with the LPFLL trimming. 0 LPFLLERR_1 Error detected with the LPFLL trimming. 0x1 LPFLLSEL LPFLL Selected 25 1 read-only LPFLLSEL_0 LPFLL is not the system clock source 0 LPFLLSEL_1 LPFLL is the system clock source 0x1 LPFLLSTEN LPFLL Stop Enable 1 1 read-write LPFLLSTEN_0 LPFLL is disabled in Stop modes. 0 LPFLLSTEN_1 LPFLL is enabled in Stop modes 0x1 LPFLLTREN LPFLL Trim Enable 8 1 read-write LPFLLTREN_0 Disable trimming LPFLL to an reference clock source 0 LPFLLTREN_1 Enable trimming LPFLL to an reference clock source 0x1 LPFLLTRMLOCK LPFLL Trim LOCK 10 1 read-only LPFLLTRMLOCK_0 LPFLL not Locked 0 LPFLLTRMLOCK_1 LPFLL trimmed and Locked 0x1 LPFLLTRUP LPFLL Trim Update 9 1 read-write LPFLLTRUP_0 Disable LPFLL trimming updates. LPFLL frequency determined by AUTOTRIM written value. 0 LPFLLTRUP_1 Enable LPFLL trimming updates. LPFLL frequency determined by reference clock multiplication 0x1 LPFLLVLD LPFLL Valid 24 1 read-only LPFLLVLD_0 LPFLL is not enabled or clock is not valid. 0 LPFLLVLD_1 LPFLL is enabled and output clock is valid. 0x1 LPFLLDIV Low Power FLL Divide Register 0x504 32 read-write n 0x0 0x0 LPFLLDIV1 LPFLL Clock Divide 1 0 3 read-write LPFLLDIV1_0 Output disabled 0 LPFLLDIV1_1 Divide by 1 0x1 LPFLLDIV1_2 Divide by 2 0x2 LPFLLDIV1_3 Divide by 4 0x3 LPFLLDIV1_4 Divide by 8 0x4 LPFLLDIV1_5 Divide by 16 0x5 LPFLLDIV1_6 Divide by 32 0x6 LPFLLDIV1_7 Divide by 64 0x7 LPFLLDIV2 LPFLL Clock Divide 2 8 3 read-write LPFLLDIV2_0 Output disabled 0 LPFLLDIV2_1 Divide by 1 0x1 LPFLLDIV2_2 Divide by 2 0x2 LPFLLDIV2_3 Divide by 4 0x3 LPFLLDIV2_4 Divide by 8 0x4 LPFLLDIV2_5 Divide by 16 0x5 LPFLLDIV2_6 Divide by 32 0x6 LPFLLDIV2_7 Divide by 64 0x7 LPFLLDIV3 LPFLL Clock Divide 3 16 3 read-write LPFLLDIV3_0 Clock disabled 0 LPFLLDIV3_1 Divide by 1 0x1 LPFLLDIV3_2 Divide by 2 0x2 LPFLLDIV3_3 Divide by 4 0x3 LPFLLDIV3_4 Divide by 8 0x4 LPFLLDIV3_5 Divide by 16 0x5 LPFLLDIV3_6 Divide by 32 0x6 LPFLLDIV3_7 Divide by 64 0x7 LPFLLSTAT Low Power FLL Status Register 0x514 32 read-write n 0x0 0x0 AUTOTRIM Auto Tune Trim Status 0 8 read-write LPFLLTCFG Low Power FLL Trim Configuration Register 0x50C 32 read-write n 0x0 0x0 LOCKW2LSB Lock LPFLL with 2 LSBS 16 1 read-write LOCKW2LSB_0 LPFLL locks within 1LSB (0.4%) 0 LOCKW2LSB_1 LPFLL locks within 2LSB (0.8%) 0x1 TRIMDIV LPFLL Trim Predivide 8 5 read-write TRIMSRC Trim Source 0 2 read-write TRIMSRC_0 SIRC 0 TRIMSRC_1 FIRC 0x1 TRIMSRC_2 System OSC 0x2 TRIMSRC_3 RTC OSC 0x3 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 CLKPRES Clock Present 0 8 read-only CLKPRES_2 System OSC (SOSC) is present. #xxxxxx1x DIVPRES Divider Present 27 5 read-only DIVPRES_1 System DIVSLOW is present. #xxxx1 RCCR Run Clock Control Register 0x14 32 read-write n 0x0 0x0 DIVBUS Bus Clock Divide Ratio 4 4 read-write DIVBUS_0 Divide-by-1 0 DIVBUS_1 Divide-by-2 0x1 DIVBUS_2 Divide-by-3 0x2 DIVBUS_3 Divide-by-4 0x3 DIVBUS_4 Divide-by-5 0x4 DIVBUS_5 Divide-by-6 0x5 DIVBUS_6 Divide-by-7 0x6 DIVBUS_7 Divide-by-8 0x7 DIVBUS_8 Divide-by-9 0x8 DIVBUS_9 Divide-by-10 0x9 DIVBUS_10 Divide-by-11 0xA DIVBUS_11 Divide-by-12 0xB DIVBUS_12 Divide-by-13 0xC DIVBUS_13 Divide-by-14 0xD DIVBUS_14 Divide-by-15 0xE DIVBUS_15 Divide-by-16 0xF DIVCORE Core Clock Divide Ratio 16 4 read-write DIVCORE_0 Divide-by-1 0 DIVCORE_1 Divide-by-2 0x1 DIVCORE_2 Divide-by-3 0x2 DIVCORE_3 Divide-by-4 0x3 DIVCORE_4 Divide-by-5 0x4 DIVCORE_5 Divide-by-6 0x5 DIVCORE_6 Divide-by-7 0x6 DIVCORE_7 Divide-by-8 0x7 DIVCORE_8 Divide-by-9 0x8 DIVCORE_9 Divide-by-10 0x9 DIVCORE_10 Divide-by-11 0xA DIVCORE_11 Divide-by-12 0xB DIVCORE_12 Divide-by-13 0xC DIVCORE_13 Divide-by-14 0xD DIVCORE_14 Divide-by-15 0xE DIVCORE_15 Divide-by-16 0xF DIVEXT External Clock Divide Ratio 8 4 read-write DIVEXT_0 Divide-by-1 0 DIVEXT_1 Divide-by-2 0x1 DIVEXT_2 Divide-by-3 0x2 DIVEXT_3 Divide-by-4 0x3 DIVEXT_4 Divide-by-5 0x4 DIVEXT_5 Divide-by-6 0x5 DIVEXT_6 Divide-by-7 0x6 DIVEXT_7 Divide-by-8 0x7 DIVEXT_8 Divide-by-9 0x8 DIVEXT_9 Divide-by-10 0x9 DIVEXT_10 Divide-by-11 0xA DIVEXT_11 Divide-by-12 0xB DIVEXT_12 Divide-by-13 0xC DIVEXT_13 Divide-by-14 0xD DIVEXT_14 Divide-by-15 0xE DIVEXT_15 Divide-by-16 0xF DIVSLOW Slow Clock Divide Ratio 0 4 read-write DIVSLOW_1 Divide-by-2 0x1 DIVSLOW_2 Divide-by-3 0x2 DIVSLOW_3 Divide-by-4 0x3 DIVSLOW_4 Divide-by-5 0x4 DIVSLOW_5 Divide-by-6 0x5 DIVSLOW_6 Divide-by-7 0x6 DIVSLOW_7 Divide-by-8 0x7 DIVSLOW_8 no description available 0x8 DIVSLOW_9 no description available 0x9 DIVSLOW_10 no description available 0xA DIVSLOW_11 no description available 0xB DIVSLOW_12 no description available 0xC DIVSLOW_13 no description available 0xD DIVSLOW_14 no description available 0xE DIVSLOW_15 no description available 0xF SCS System Clock Source 24 3 read-write SCS_1 no description available 0x1 SCS_2 no description available 0x2 SCS_3 no description available 0x3 SCS_4 no description available 0x4 SCS_5 no description available 0x5 ROSCCSR RTC OSC Control Status Register 0x400 32 read-write n 0x0 0x0 LK Lock Register 23 1 read-write LK_0 Control Status Register can be written. 0 LK_1 Control Status Register cannot be written. 0x1 ROSCCM RTC OSC Clock Monitor 16 1 read-write ROSCCM_0 RTC OSC Clock Monitor is disabled 0 ROSCCM_1 RTC OSC Clock Monitor is enabled 0x1 ROSCCMRE RTC OSC Clock Monitor Reset Enable 17 1 read-write ROSCCMRE_0 Clock Monitor generates interrupt when error detected 0 ROSCCMRE_1 Clock Monitor generates reset when error detected 0x1 ROSCERR RTC OSC Clock Error 26 1 read-write oneToClear ROSCERR_0 RTC OSC Clock Monitor is disabled or has not detected an error 0 ROSCERR_1 RTC OSC Clock Monitor is enabled and detected an RTC loss of clock error 0x1 ROSCSEL RTC OSC Selected 25 1 read-only ROSCSEL_0 RTC OSC is not the system clock source 0 ROSCSEL_1 RTC OSC is the system clock source 0x1 ROSCVLD RTC OSC Valid 24 1 read-only ROSCVLD_0 RTC OSC is not enabled or clock is not valid 0 ROSCVLD_1 RTC OSC is enabled and output clock is valid 0x1 SIRCCFG Slow IRC Configuration Register 0x208 32 read-write n 0x0 0x0 RANGE Frequency Range 0 1 read-write RANGE_0 no description available 0 RANGE_1 no description available 0x1 SIRCCSR Slow IRC Control Status Register 0x200 32 read-write n 0x0 0x0 LK Lock Register 23 1 read-write LK_0 Control Status Register can be written. 0 LK_1 Control Status Register cannot be written. 0x1 SIRCEN Slow IRC Enable 0 1 read-write SIRCEN_0 Slow IRC is disabled 0 SIRCEN_1 Slow IRC is enabled 0x1 SIRCLPEN Slow IRC Low Power Enable 2 1 read-write SIRCLPEN_0 Slow IRC is disabled in VLP modes 0 SIRCLPEN_1 Slow IRC is enabled in VLP modes 0x1 SIRCSEL Slow IRC Selected 25 1 read-only SIRCSEL_0 Slow IRC is not the system clock source 0 SIRCSEL_1 Slow IRC is the system clock source 0x1 SIRCSTEN Slow IRC Stop Enable 1 1 read-write SIRCSTEN_0 Slow IRC is disabled in Stop modes 0 SIRCSTEN_1 Slow IRC is enabled in Stop modes 0x1 SIRCVLD Slow IRC Valid 24 1 read-only SIRCVLD_0 Slow IRC is not enabled or clock is not valid 0 SIRCVLD_1 Slow IRC is enabled and output clock is valid 0x1 SIRCDIV Slow IRC Divide Register 0x204 32 read-write n 0x0 0x0 SIRCDIV1 Slow IRC Clock Divide 1 0 3 read-write SIRCDIV1_0 Output disabled 0 SIRCDIV1_1 Divide by 1 0x1 SIRCDIV1_2 Divide by 2 0x2 SIRCDIV1_3 Divide by 4 0x3 SIRCDIV1_4 Divide by 8 0x4 SIRCDIV1_5 Divide by 16 0x5 SIRCDIV1_6 Divide by 32 0x6 SIRCDIV1_7 Divide by 64 0x7 SIRCDIV2 Slow IRC Clock Divide 2 8 3 read-write SIRCDIV2_0 Output disabled 0 SIRCDIV2_1 Divide by 1 0x1 SIRCDIV2_2 Divide by 2 0x2 SIRCDIV2_3 Divide by 4 0x3 SIRCDIV2_4 Divide by 8 0x4 SIRCDIV2_5 Divide by 16 0x5 SIRCDIV2_6 Divide by 32 0x6 SIRCDIV2_7 Divide by 64 0x7 SIRCDIV3 Slow IRC Clock Divider 3 16 3 read-write SIRCDIV3_0 Output disabled 0 SIRCDIV3_1 Divide by 1 0x1 SIRCDIV3_2 Divide by 2 0x2 SIRCDIV3_3 Divide by 4 0x3 SIRCDIV3_4 Divide by 8 0x4 SIRCDIV3_5 Divide by 16 0x5 SIRCDIV3_6 Divide by 32 0x6 SIRCDIV3_7 Divide by 64 0x7 SOSCCSR System OSC Control Status Register 0x100 32 read-write n 0x0 0x0 LK Lock Register 23 1 read-write LK_0 This Control Status Register can be written. 0 LK_1 This Control Status Register cannot be written. 0x1 SOSCCM System OSC Clock Monitor 16 1 read-write SOSCCM_0 System OSC Clock Monitor is disabled 0 SOSCCM_1 System OSC Clock Monitor is enabled 0x1 SOSCCMRE System OSC Clock Monitor Reset Enable 17 1 read-write SOSCCMRE_0 Clock Monitor generates interrupt when error detected 0 SOSCCMRE_1 Clock Monitor generates reset when error detected 0x1 SOSCEN System OSC Enable 0 1 read-write SOSCEN_0 System OSC is disabled 0 SOSCEN_1 System OSC is enabled 0x1 SOSCERR System OSC Clock Error 26 1 read-write oneToClear SOSCERR_0 System OSC Clock Monitor is disabled or has not detected an error 0 SOSCERR_1 System OSC Clock Monitor is enabled and detected an error 0x1 SOSCLPEN System OSC Low Power Enable 2 1 read-write SOSCLPEN_0 System OSC is disabled in VLP modes 0 SOSCLPEN_1 System OSC is enabled in VLP modes 0x1 SOSCSEL System OSC Selected 25 1 read-only SOSCSEL_0 System OSC is not the system clock source 0 SOSCSEL_1 System OSC is the system clock source 0x1 SOSCSTEN System OSC Stop Enable 1 1 read-write SOSCSTEN_0 System OSC is disabled in Stop modes 0 SOSCSTEN_1 no description available 0x1 SOSCVLD System OSC Valid 24 1 read-only SOSCVLD_0 System OSC is not enabled or clock is not valid 0 SOSCVLD_1 System OSC is enabled and output clock is valid 0x1 SOSCDIV System OSC Divide Register 0x104 32 read-write n 0x0 0x0 SOSCDIV1 System OSC Clock Divide 1 0 3 read-write SOSCDIV1_0 Output disabled 0 SOSCDIV1_1 Divide by 1 0x1 SOSCDIV1_2 Divide by 2 0x2 SOSCDIV1_3 Divide by 4 0x3 SOSCDIV1_4 Divide by 8 0x4 SOSCDIV1_5 Divide by 16 0x5 SOSCDIV1_6 Divide by 32 0x6 SOSCDIV1_7 Divide by 64 0x7 SOSCDIV2 System OSC Clock Divide 2 8 3 read-write SOSCDIV2_0 Output disabled 0 SOSCDIV2_1 Divide by 1 0x1 SOSCDIV2_2 Divide by 2 0x2 SOSCDIV2_3 Divide by 4 0x3 SOSCDIV2_4 Divide by 8 0x4 SOSCDIV2_5 Divide by 16 0x5 SOSCDIV2_6 Divide by 32 0x6 SOSCDIV2_7 Divide by 64 0x7 SOSCDIV3 System OSC Clock Divide 3 16 3 read-write SOSCDIV3_0 Output disabled 0 SOSCDIV3_1 Divide by 1 0x1 SOSCDIV3_2 Divide by 2 0x2 SOSCDIV3_3 Divide by 4 0x3 SOSCDIV3_4 Divide by 8 0x4 SOSCDIV3_5 Divide by 16 0x5 SOSCDIV3_6 Divide by 32 0x6 SOSCDIV3_7 Divide by 64 0x7 VCCR VLPR Clock Control Register 0x18 32 read-write n 0x0 0x0 DIVBUS Bus Clock Divide Ratio 4 4 read-write DIVBUS_0 Divide-by-1 0 DIVBUS_1 Divide-by-2 0x1 DIVBUS_2 Divide-by-3 0x2 DIVBUS_3 Divide-by-4 0x3 DIVBUS_4 Divide-by-5 0x4 DIVBUS_5 Divide-by-6 0x5 DIVBUS_6 Divide-by-7 0x6 DIVBUS_7 Divide-by-8 0x7 DIVBUS_8 Divide-by-9 0x8 DIVBUS_9 Divide-by-10 0x9 DIVBUS_10 Divide-by-11 0xA DIVBUS_11 Divide-by-12 0xB DIVBUS_12 Divide-by-13 0xC DIVBUS_13 Divide-by-14 0xD DIVBUS_14 Divide-by-15 0xE DIVBUS_15 Divide-by-16 0xF DIVCORE Core Clock Divide Ratio 16 4 read-write DIVCORE_0 Divide-by-1 0 DIVCORE_1 Divide-by-2 0x1 DIVCORE_2 Divide-by-3 0x2 DIVCORE_3 Divide-by-4 0x3 DIVCORE_4 Divide-by-5 0x4 DIVCORE_5 Divide-by-6 0x5 DIVCORE_6 Divide-by-7 0x6 DIVCORE_7 Divide-by-8 0x7 DIVCORE_8 Divide-by-9 0x8 DIVCORE_9 Divide-by-10 0x9 DIVCORE_10 Divide-by-11 0xA DIVCORE_11 Divide-by-12 0xB DIVCORE_12 Divide-by-13 0xC DIVCORE_13 Divide-by-14 0xD DIVCORE_14 Divide-by-15 0xE DIVCORE_15 Divide-by-16 0xF DIVEXT External Clock Divide Ratio 8 4 read-write DIVEXT_0 Divide-by-1 0 DIVEXT_1 Divide-by-2 0x1 DIVEXT_2 Divide-by-3 0x2 DIVEXT_3 Divide-by-4 0x3 DIVEXT_4 Divide-by-5 0x4 DIVEXT_5 Divide-by-6 0x5 DIVEXT_6 Divide-by-7 0x6 DIVEXT_7 Divide-by-8 0x7 DIVEXT_8 Divide-by-9 0x8 DIVEXT_9 Divide-by-10 0x9 DIVEXT_10 Divide-by-11 0xA DIVEXT_11 Divide-by-12 0xB DIVEXT_12 Divide-by-13 0xC DIVEXT_13 Divide-by-14 0xD DIVEXT_14 Divide-by-15 0xE DIVEXT_15 Divide-by-16 0xF DIVSLOW Slow Clock Divide Ratio 0 4 read-write DIVSLOW_1 Divide-by-2 0x1 DIVSLOW_2 Divide-by-3 0x2 DIVSLOW_3 Divide-by-4 0x3 DIVSLOW_4 Divide-by-5 0x4 DIVSLOW_5 Divide-by-6 0x5 DIVSLOW_6 Divide-by-7 0x6 DIVSLOW_7 Divide-by-8 0x7 DIVSLOW_8 no description available 0x8 DIVSLOW_9 no description available 0x9 DIVSLOW_10 no description available 0xA DIVSLOW_11 no description available 0xB DIVSLOW_12 no description available 0xC DIVSLOW_13 no description available 0xD DIVSLOW_14 no description available 0xE DIVSLOW_15 no description available 0xF SCS System Clock Source 24 4 read-write SCS_1 no description available 0x1 SCS_2 no description available 0x2 SCS_4 no description available 0x4 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 VERSION SCG Version Number 0 32 read-only SEMA420 sema42_ips SEMA42_0 0x0 0x0 0x44 registers n GATE0 Gate Register 0x3 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE1 Gate Register 0x2 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE10 Gate Register 0x9 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE11 Gate Register 0x8 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE12 Gate Register 0xF 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE13 Gate Register 0xE 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE14 Gate Register 0xD 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE15 Gate Register 0xC 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE2 Gate Register 0x1 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE3 Gate Register 0x0 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE4 Gate Register 0x7 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE5 Gate Register 0x6 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE6 Gate Register 0x5 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE7 Gate Register 0x4 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE8 Gate Register 0xB 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE9 Gate Register 0xA 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF RSTGT_R Reset Gate Read RSTGT 0x42 16 read-only n 0x0 0x0 ROZ ROZ 14 2 read-only RSTGMS RSTGMS 8 4 read-only RSTGSM RSTGSM 12 2 read-only RSTGSM_0 Idle, waiting for the first data pattern write. 0 RSTGSM_1 Waiting for the second data pattern write. 0x1 RSTGSM_2 The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, this machine returns to the idle (waiting for first data pattern write) state. The 01 state persists for only one clock cycle. Software cannot observe this state. 0x2 RSTGSM_3 This state encoding is never used and therefore reserved. 0x3 RSTGTN RSTGTN 0 8 read-only RSTGT_W Reset Gate Write RSTGT 0x42 16 write-only n 0x0 0x0 RSTGDP RSTGDP 8 8 write-only RSTGTN RSTGTN 0 8 write-only SEMA421 sema42_ips SEMA42_1 0x0 0x0 0x44 registers n GATE0 Gate Register 0x3 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE1 Gate Register 0x2 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE10 Gate Register 0x9 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE11 Gate Register 0x8 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE12 Gate Register 0xF 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE13 Gate Register 0xE 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE14 Gate Register 0xD 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE15 Gate Register 0xC 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE2 Gate Register 0x1 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE3 Gate Register 0x0 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE4 Gate Register 0x7 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE5 Gate Register 0x6 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE6 Gate Register 0x5 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE7 Gate Register 0x4 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE8 Gate Register 0xB 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF GATE9 Gate Register 0xA 8 read-write n 0x0 0x0 GTFSM GTFSM 0 4 read-write GTFSM_0 The gate is unlocked (free). 0 GTFSM_1 The gate has been locked by processor 0. 0x1 GTFSM_2 The gate has been locked by processor 1. 0x2 GTFSM_3 The gate has been locked by processor 2. 0x3 GTFSM_4 The gate has been locked by processor 3. 0x4 GTFSM_5 The gate has been locked by processor 4. 0x5 GTFSM_6 The gate has been locked by processor 5. 0x6 GTFSM_7 The gate has been locked by processor 6. 0x7 GTFSM_8 The gate has been locked by processor 7. 0x8 GTFSM_9 The gate has been locked by processor 8. 0x9 GTFSM_10 The gate has been locked by processor 9. 0xA GTFSM_11 The gate has been locked by processor 10. 0xB GTFSM_12 The gate has been locked by processor 11. 0xC GTFSM_13 The gate has been locked by processor 12. 0xD GTFSM_14 The gate has been locked by processor 13. 0xE GTFSM_15 The gate has been locked by processor 14. 0xF RSTGT_R Reset Gate Read RSTGT 0x42 16 read-only n 0x0 0x0 ROZ ROZ 14 2 read-only RSTGMS RSTGMS 8 4 read-only RSTGSM RSTGSM 12 2 read-only RSTGSM_0 Idle, waiting for the first data pattern write. 0 RSTGSM_1 Waiting for the second data pattern write. 0x1 RSTGSM_2 The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed, this machine returns to the idle (waiting for first data pattern write) state. The 01 state persists for only one clock cycle. Software cannot observe this state. 0x2 RSTGSM_3 This state encoding is never used and therefore reserved. 0x3 RSTGTN RSTGTN 0 8 read-only RSTGT_W Reset Gate Write RSTGT 0x42 16 write-only n 0x0 0x0 RSTGDP RSTGDP 8 8 write-only RSTGTN RSTGTN 0 8 write-only SIM SIM SIM 0x0 0x0 0x74 registers n CHIPCTRL Chip Control Register 0x4 32 read-write n 0x0 0x0 FBSL FLEXBUS security level 8 2 read-write FBSL_0 All off-chip access(instruction and data) via the Flexbus or sdram are disallowed 0 FBSL_1 All off-chip access(instruction and data) via the Flexbus or sdram are disallowed 0x1 FBSL_2 off-chip instruction access are disallowed, data access are allowed 0x2 FBSL_3 off-chip instruction access and data access are allowed 0x3 FCFG1 Flash Configuration Register 1 0x4C 32 read-write n 0x0 0x0 CORE0_PFSIZE The flash size for core0 (CM4) 28 4 read-only CORE0_PFSIZE_12 CM4 has 1 MB flash size. 0xC CORE0_SRAMSIZE The SRAM size for core0 (CM4) 20 4 read-only CORE0_SRAMSIZE_10 CM4 has 256 KB SRAM 0xA CORE1_PFSIZE The flash size for core1 (CM0+) 24 4 read-only CORE1_PFSIZE_10 CM0+ has 256 KB flash size. 0xA CORE1_SRAMSIZE The SRAM size for core1 (CM0+) 16 4 read-only CORE1_SRAMSIZE_9 CM0+ has 128 KB SRAM 0x9 FLASHDIS Flash disable 0 1 read-write FLASHDIS_0 Flash is enabled 0 FLASHDIS_1 Flash is disabled 0x1 FLASHDOZE Flash Doze 1 1 read-write FLASHDOZE_0 Flash remains enabled during Doze mode 0 FLASHDOZE_1 Flash is disabled for the duration of Doze mode 0x1 FLSAUTODISEN Flash auto disable enabled. 2 1 read-write FLSAUTODISEN_0 Disable flash auto disable function 0 FLSAUTODISEN_1 Enable flash auto disable function 0x1 FLSAUTODISWD The clock counter for time period of flash auto disable. 3 11 read-write FCFG2 Flash Configuration Register 2 0x50 32 read-only n 0x0 0x0 MAXADDR01 Max Address lock 24 7 read-only MAXADDR2 Max Address lock 16 6 read-only SWAP SWAP 31 1 read-only SWAP_0 Logical P-flash Block 0 is located at relative address 0x0000 0 SWAP_1 Logical P-flash Block 1 is located at relative address 0x0000 0x1 MISC2 MISC2 Register 0x70 32 read-write n 0x0 0x0 systick_clk_en Systick clock enable 0 1 read-write systick_clk_en_0 Systick clock is disabled 0 systick_clk_en_1 Systick clock is enabled 0x1 RFADDRH RF MAC Address High 0x68 32 read-only n 0x0 0x0 MACADDR4 MACADDR4 0 8 read-only RFADDRL RF Mac Address Low 0x64 32 read-only n 0x0 0x0 MACADDR0 MACADDR0 0 8 read-only MACADDR1 MACADDR1 8 8 read-only MACADDR2 MACADDR2 16 8 read-only MACADDR3 MACADDR3 24 8 read-only SDID System Device Identification Register 0x24 32 read-only n 0x0 0x0 DIEID DIEID 7 5 read-only FAMID FAMID 28 4 read-only FAMID_0 K32W0 0 PINID PINID 0 4 read-only PINID_8 176-pin 0x8 PINID_13 191-pin 0xD REVID REVID 12 4 read-only SERIESID SERIESID 20 4 read-only SUBFAMID SUBFAMID 24 4 read-only SUBFAMID_2 02 0x2 SUBFAMID_3 03 0x3 SUBFAMID_4 04 0x4 UIDH Unique Identification Register High 0x58 32 read-only n 0x0 0x0 UID Unique Identification 0 16 read-only UIDL Unique Identification Register Mid Low 0x60 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only UIDM Unique Identification Register Mid Middle 0x5C 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only SMC0 crr_cmc0 SMC0 0x0 0x0 0x68 registers n CMC0 18 FM Force Mode Register 0x50 32 read-write n 0x0 0x0 FORCECFG Boot Configuration 0 2 read-write FORCECFG_0 No effect. 0 FORCECFG_1 Assert corresponding bit in Mode Register on next system reset. 0x1 MR Mode Register 0x40 32 read-write n 0x0 0x0 BOOTCFG Boot Configuration 0 2 read-write oneToClear BOOTCFG_0 Boot from Flash. 0 BOOTCFG_1 Boot from ROM due to BOOTCFG0 pin assertion. 0x1 BOOTCFG_2 Boot from ROM due to FOPT configuration. 0x2 BOOTCFG_3 Boot from ROM due to both BOOTCFG0 pin assertion and FOPT configuration. 0x3 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 PWRD_INDPT Power Domains Independent 0 1 read-only PMCTRL Power Mode Control register 0x10 32 read-write n 0x0 0x0 PSTOPO Partial Stop Option 16 2 read-write PSTOPO_0 STOP - Normal Stop mode 0 PSTOPO_1 PSTOP1 - Partial Stop with system and bus clock disabled 0x1 PSTOPO_2 PSTOP2 - Partial Stop with system clock disabled and bus clock enabled 0x2 PSTOPO_3 PSTOP3 - Partial Stop with system clock enabled and bus clock enabled 0x3 RUNM Run Mode Control 8 2 read-write RUNM_0 Normal Run mode (RUN) 0 RUNM_2 Very-Low-Power Run mode (VLPR) 0x2 RUNM_3 High Speed Run mode (HSRUN) 0x3 STOPM Stop Mode Control 0 3 read-write STOPM_0 Normal Stop (STOP) 0 STOPM_2 Very-Low-Power Stop (VLPS) 0x2 STOPM_3 Low-Leakage Stop (LLS) 0x3 STOPM_4 Very-Low-Leakage Stop with SRAM retention(VLLS2/3) 0x4 STOPM_6 Very-Low-Leakage Stop without SRAM retention (VLLS0/1) 0x6 PMPROT Power Mode Protection register 0x8 32 read-write n 0x0 0x0 AHSRUN Allow High Speed Run mode 7 1 read-write AHSRUN_0 HSRUN is not allowed 0 AHSRUN_1 HSRUN is allowed 0x1 ALLS Allow Low-Leakage Stop Mode 3 1 read-write ALLS_0 LLS is not allowed 0 ALLS_1 LLS is allowed 0x1 AVLLS Allow Very-Low-Leakage Stop Mode 0 2 read-write AVLLS_0 VLLS mode is not allowed 0 AVLLS_1 VLLS0/1 mode is allowed 0x1 AVLLS_2 VLLS2/3 mode is allowed 0x2 AVLLS_3 VLLS0/1/2/3 mode is allowed 0x3 AVLP Allow Very-Low-Power Modes 5 1 read-write AVLP_0 VLPR, VLPW, and VLPS are not allowed. 0 AVLP_1 VLPR, VLPW, and VLPS are allowed. 0x1 PMSTAT Power Mode Status register 0x18 32 read-write n 0x0 0x0 PMSTAT Power Mode Status 0 8 read-only PMSTAT_1 Current power mode is RUN. 0x1 PMSTAT_2 Current power mode is any STOP mode. 0x2 PMSTAT_4 Current power mode is VLPR. 0x4 PMSTAT_128 Current power mode is HSRUN 0x80 STOPSTAT Stop Entry Status 24 8 read-write RPC Reset Pin Control 0x24 32 read-write n 0x0 0x0 FILTCFG Reset Filter Configuration 0 5 read-write FILTEN Filter Enable 8 1 read-write FILTEN_0 Slow clock reset pin filter disabled. 0 FILTEN_1 Slow clock reset pin filter enabled in Run modes. 0x1 LPOFEN LPO Filter Enable 9 1 read-write LPOFEN_0 LPO clock reset pin filter disabled. 0 LPOFEN_1 LPO clock reset pin filter enabled in all modes. 0x1 SRAMDSR SRAM Deep Sleep Register 0x64 32 read-write n 0x0 0x0 DSE Deep Sleep Enable 0 32 read-write SRAMLPR SRAM Low Power Register 0x60 32 read-write n 0x0 0x0 LPE Low Power Enable 0 32 read-write SRIE System Reset Interrupt Enable 0x2C 32 read-write n 0x0 0x0 CORE1 Core1 Reset 17 1 read-write CORE1_0 Interrupt disabled. 0 CORE1_1 Interrupt enabled. 0x1 LOCKUP Lockup Reset 15 1 read-write LOCKUP_0 Interrupt disabled. 0 LOCKUP_1 Interrupt enabled. 0x1 MDM MDM Reset 9 1 read-write MDM_0 Interrupt disabled. 0 MDM_1 Interrupt enabled. 0x1 PIN Pin Reset 8 1 read-write PIN_0 Interrupt disabled. 0 PIN_1 Interrupt enabled. 0x1 STOPACK Stop Timeout Reset 11 1 read-write STOPACK_0 Interrupt disabled. 0 STOPACK_1 Interrupt enabled. 0x1 SW Software Reset 14 1 read-write SW_0 Interrupt disabled. 0 SW_1 Interrupt enabled. 0x1 WDOG Watchdog Reset 13 1 read-write WDOG_0 Interrupt disabled. 0 WDOG_1 Interrupt enabled. 0x1 SRIF System Reset Interrupt Flag 0x30 32 read-write n 0x0 0x0 CORE1 Core1 Reset 17 1 read-write oneToClear CORE1_0 Reset source not pending. 0 CORE1_1 Reset source pending. 0x1 LOCKUP Lockup Reset 15 1 read-write oneToClear LOCKUP_0 Reset source not pending. 0 LOCKUP_1 Reset source pending. 0x1 MDM MDM Reset 9 1 read-write oneToClear MDM_0 Reset source not pending. 0 MDM_1 Reset source pending. 0x1 PIN Pin Reset 8 1 read-write oneToClear PIN_0 Reset source not pending. 0 PIN_1 Reset source pending. 0x1 STOPACK Stop Timeout Reset 11 1 read-write oneToClear STOPACK_0 Reset source not pending. 0 STOPACK_1 Reset source pending. 0x1 SW Software Reset 14 1 read-write oneToClear SW_0 Reset source not pending. 0 SW_1 Reset source pending. 0x1 WDOG Watchdog Reset 13 1 read-write oneToClear WDOG_0 Reset source not pending. 0 WDOG_1 Reset source pending. 0x1 SRS System Reset Status 0x20 32 read-only n 0x0 0x0 CORE Core Reset 7 1 read-only CORE_0 Reset source was not core only reset. 0 CORE_1 Reset source was core reset and reset the core only. 0x1 CORE1 Core1 System Reset 17 1 read-only CORE1_0 Reset not generated from Core1 system reset source. 0 CORE1_1 Reset generated from Core1 system reset source. 0x1 FATAL Fatal Reset 5 1 read-only FATAL_0 Reset was not generated by a fatal reset source. 0 FATAL_1 Reset was generated by a fatal reset source. 0x1 HVD HVD Reset 3 1 read-only HVD_0 Reset not generated by HVD. 0 HVD_1 Reset generated by HVD. 0x1 JTAG JTAG System Reset 28 1 read-only JTAG_0 Reset not generated by JTAG system reset. 0 JTAG_1 Reset generated by JTAG system reset. 0x1 LOCKUP Lockup Reset 15 1 read-only LOCKUP_0 Reset not generated by core lockup or exception. 0 LOCKUP_1 Reset generated by core lockup or exception. 0x1 LVD LVD Reset 2 1 read-only LVD_0 Reset not generated by LVD. 0 LVD_1 Reset generated by LVD. 0x1 MDM MDM Reset 9 1 read-only MDM_0 Reset was not generated from the MDM reset request. 0 MDM_1 Reset was generated from the MDM reset request. 0x1 PIN Pin Reset 8 1 read-only PIN_0 Reset was not generated from the assertion of RESET_B pin. 0 PIN_1 Reset was generated from the assertion of RESET_B pin. 0x1 POR POR Reset 1 1 read-only POR_0 Reset not generated by POR. 0 POR_1 Reset generated by POR. 0x1 RSTACK Reset Timeout 10 1 read-only RSTACK_0 Reset not generated from Reset Controller Timeout. 0 RSTACK_1 Reset generated from Reset Controller Timeout. 0x1 SCG SCG Reset 12 1 read-only SCG_0 Reset is not generated from an SCG loss of lock or loss of clock. 0 SCG_1 Reset is generated from an SCG loss of lock or loss of clock. 0x1 STOPACK Stop Timeout Reset 11 1 read-only STOPACK_0 Reset not generated by Stop Controller Timeout. 0 STOPACK_1 Reset generated by Stop Controller Timeout. 0x1 SW Software Reset 14 1 read-only SW_0 Reset not generated by software request from core. 0 SW_1 Reset generated by software request from core. 0x1 WAKEUP Wakeup Reset 0 1 read-only WAKEUP_0 Reset not generated by wakeup from VLLS mode. 0 WAKEUP_1 Reset generated by wakeup from VLLS mode. 0x1 WARM Warm Reset 4 1 read-only WARM_0 Reset not generated by Warm Reset source. 0 WARM_1 Reset generated by Warm Reset source. 0x1 WDOG Watchdog Reset 13 1 read-only WDOG_0 Reset is not generated from the WatchDog timeout. 0 WDOG_1 Reset is generated from the WatchDog timeout. 0x1 SSRS Sticky System Reset Status 0x28 32 read-write n 0x0 0x0 CORE1 Core1 Reset 17 1 read-write oneToClear CORE1_0 Reset not generated from Core1 reset source. 0 CORE1_1 Reset generated from Core1 reset source. 0x1 FATAL Fatal Reset 5 1 read-write oneToClear FATAL_0 Reset was not generated by a fatal reset source. 0 FATAL_1 Reset was generated by a fatal reset source. 0x1 HVD HVD Reset 3 1 read-write oneToClear HVD_0 Reset not generated by HVD. 0 HVD_1 Reset generated by HVD. 0x1 JTAG JTAG System Reset 28 1 read-write oneToClear JTAG_0 Reset not generated by JTAG system reset. 0 JTAG_1 Reset generated by JTAG system reset. 0x1 LOCKUP Lockup Reset 15 1 read-write oneToClear LOCKUP_0 Reset not generated by core lockup. 0 LOCKUP_1 Reset generated by core lockup. 0x1 LVD LVD Reset 2 1 read-write oneToClear LVD_0 Reset not generated by LVD. 0 LVD_1 Reset generated by LVD. 0x1 MDM MDM Reset 9 1 read-write oneToClear MDM_0 Reset was not generated from the MDM reset request. 0 MDM_1 Reset was generated from the MDM reset request. 0x1 PIN Pin Reset 8 1 read-write oneToClear PIN_0 Reset was not generated from the RESET_B pin. 0 PIN_1 Reset was generated from the RESET_B pin. 0x1 POR POR Reset 1 1 read-write oneToClear POR_0 Reset not generated by POR. 0 POR_1 Reset generated by POR. 0x1 RSTACK Reset Timeout 10 1 read-write oneToClear RSTACK_0 Reset not generated from Reset Controller Timeout. 0 RSTACK_1 Reset generated from Reset Controller Timeout. 0x1 SCG SCG Reset 12 1 read-write oneToClear SCG_0 Reset is not generated from an SCG loss of lock or loss of clock. 0 SCG_1 Reset is generated from an SCG loss of lock or loss of clock. 0x1 STOPACK Stop Timeout Reset 11 1 read-write oneToClear STOPACK_0 Reset not generated by Stop Controller Timeout. 0 STOPACK_1 Reset generated by Stop Controller Timeout. 0x1 SW Software Reset 14 1 read-write oneToClear SW_0 Reset not generated by software request from core. 0 SW_1 Reset generated by software request from core. 0x1 WAKEUP Wakeup Reset 0 1 read-write oneToClear WAKEUP_0 Reset not generated by wakeup from VLLS mode. 0 WAKEUP_1 Reset generated by wakeup from VLLS mode. 0x1 WARM Warm Reset 4 1 read-write oneToClear WARM_0 Reset not generated by system reset source. 0 WARM_1 Reset generated by system reset source. 0x1 WDOG Watchdog Reset 13 1 read-write oneToClear WDOG_0 Reset is not generated from the WatchDog timeout. 0 WDOG_1 Reset is generated from the WatchDog timeout. 0x1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only FEATURE_171 Default features supported 0xAB MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only SMC1 crr_cmc1 SMC1 0x0 0x0 0x68 registers n FM Force Mode Register 0x50 32 read-write n 0x0 0x0 FORCECFG Boot Configuration 0 2 read-write FORCECFG_0 No effect. 0 FORCECFG_1 Assert corresponding bit in Mode Register on next system reset. 0x1 MR Mode Register 0x40 32 read-write n 0x0 0x0 BOOTCFG Boot Configuration 0 2 read-write oneToClear BOOTCFG_0 Boot from Flash. 0 BOOTCFG_1 Boot from ROM due to BOOTCFG0 pin assertion. 0x1 BOOTCFG_2 Boot from ROM due to FOPT configuration. 0x2 BOOTCFG_3 Boot from ROM due to both BOOTCFG0 pin assertion and FOPT configuration. 0x3 PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 PWRD_INDPT Power Domains Independent 0 1 read-only PMCTRL Power Mode Control register 0x10 32 read-write n 0x0 0x0 PSTOPO Partial Stop Option 16 2 read-write PSTOPO_0 STOP - Normal Stop mode 0 PSTOPO_1 PSTOP1 - Partial Stop with system and bus clock disabled 0x1 PSTOPO_2 PSTOP2 - Partial Stop with system clock disabled and bus clock enabled 0x2 PSTOPO_3 PSTOP3 - Partial Stop with system clock enabled and bus clock enabled 0x3 RUNM Run Mode Control 8 2 read-write RUNM_0 Normal Run mode (RUN) 0 RUNM_2 Very-Low-Power Run mode (VLPR) 0x2 RUNM_3 High Speed Run mode (HSRUN) 0x3 STOPM Stop Mode Control 0 3 read-write STOPM_0 Normal Stop (STOP) 0 STOPM_2 Very-Low-Power Stop (VLPS) 0x2 STOPM_3 Low-Leakage Stop (LLS) 0x3 STOPM_4 Very-Low-Leakage Stop with SRAM retention(VLLS2/3) 0x4 STOPM_6 Very-Low-Leakage Stop without SRAM retention (VLLS0/1) 0x6 PMPROT Power Mode Protection register 0x8 32 read-write n 0x0 0x0 AHSRUN Allow High Speed Run mode 7 1 read-write AHSRUN_0 HSRUN is not allowed 0 AHSRUN_1 HSRUN is allowed 0x1 ALLS Allow Low-Leakage Stop Mode 3 1 read-write ALLS_0 LLS is not allowed 0 ALLS_1 LLS is allowed 0x1 AVLLS Allow Very-Low-Leakage Stop Mode 0 2 read-write AVLLS_0 VLLS mode is not allowed 0 AVLLS_1 VLLS0/1 mode is allowed 0x1 AVLLS_2 VLLS2/3 mode is allowed 0x2 AVLLS_3 VLLS0/1/2/3 mode is allowed 0x3 AVLP Allow Very-Low-Power Modes 5 1 read-write AVLP_0 VLPR, VLPW, and VLPS are not allowed. 0 AVLP_1 VLPR, VLPW, and VLPS are allowed. 0x1 PMSTAT Power Mode Status register 0x18 32 read-write n 0x0 0x0 PMSTAT Power Mode Status 0 8 read-only PMSTAT_1 Current power mode is RUN. 0x1 PMSTAT_2 Current power mode is any STOP mode. 0x2 PMSTAT_4 Current power mode is VLPR. 0x4 PMSTAT_128 Current power mode is HSRUN 0x80 STOPSTAT Stop Entry Status 24 8 read-write SRAMDSR SRAM Deep Sleep Register 0x64 32 read-write n 0x0 0x0 DSE Deep Sleep Enable 0 32 read-write SRAMLPR SRAM Low Power Register 0x60 32 read-write n 0x0 0x0 LPE Low Power Enable 0 32 read-write SRIE System Reset Interrupt Enable 0x2C 32 read-write n 0x0 0x0 CORE0 Core0 Reset 16 1 read-write CORE0_0 Interrupt disabled. 0 CORE0_1 Interrupt enabled. 0x1 LOCKUP Lockup Reset 15 1 read-write LOCKUP_0 Interrupt disabled. 0 LOCKUP_1 Interrupt enabled. 0x1 MDM MDM Reset 9 1 read-write MDM_0 Interrupt disabled. 0 MDM_1 Interrupt enabled. 0x1 PIN Pin Reset 8 1 read-write PIN_0 Interrupt disabled. 0 PIN_1 Interrupt enabled. 0x1 STOPACK Stop Timeout Reset 11 1 read-write STOPACK_0 Interrupt disabled. 0 STOPACK_1 Interrupt enabled. 0x1 SW Software Reset 14 1 read-write SW_0 Interrupt disabled. 0 SW_1 Interrupt enabled. 0x1 WDOG Watchdog Reset 13 1 read-write WDOG_0 Interrupt disabled. 0 WDOG_1 Interrupt enabled. 0x1 SRIF System Reset Interrupt Flag 0x30 32 read-write n 0x0 0x0 CORE0 Core0 Reset 16 1 read-write oneToClear CORE0_0 Reset source not pending. 0 CORE0_1 Reset source pending. 0x1 LOCKUP Lockup Reset 15 1 read-write oneToClear LOCKUP_0 Reset source not pending. 0 LOCKUP_1 Reset source pending. 0x1 MDM MDM Reset 9 1 read-write oneToClear MDM_0 Reset source not pending. 0 MDM_1 Reset source pending. 0x1 PIN Pin Reset 8 1 read-write oneToClear PIN_0 Reset source not pending. 0 PIN_1 Reset source pending. 0x1 STOPACK Stop Timeout Reset 11 1 read-write oneToClear STOPACK_0 Reset source not pending. 0 STOPACK_1 Reset source pending. 0x1 SW Software Reset 14 1 read-write oneToClear SW_0 Reset source not pending. 0 SW_1 Reset source pending. 0x1 WDOG Watchdog Reset 13 1 read-write oneToClear WDOG_0 Reset source not pending. 0 WDOG_1 Reset source pending. 0x1 SRS System Reset Status 0x20 32 read-only n 0x0 0x0 CORE Core Reset 7 1 read-only CORE_0 Reset source was not core only reset. 0 CORE_1 Reset source was core reset and reset the core only. 0x1 CORE0 Core0 System Reset 16 1 read-only CORE0_0 Reset not generated from Core0 system reset source. 0 CORE0_1 Reset generated from Core0 system reset source. 0x1 FATAL Fatal Reset 5 1 read-only FATAL_0 Reset was not generated by a fatal reset source. 0 FATAL_1 Reset was generated by a fatal reset source. 0x1 HVD HVD Reset 3 1 read-only HVD_0 Reset not generated by HVD. 0 HVD_1 Reset generated by HVD. 0x1 JTAG JTAG System Reset 28 1 read-only JTAG_0 Reset not generated by JTAG system reset. 0 JTAG_1 Reset generated by JTAG system reset. 0x1 LOCKUP Lockup Reset 15 1 read-only LOCKUP_0 Reset not generated by core lockup or exception. 0 LOCKUP_1 Reset generated by core lockup or exception. 0x1 LVD LVD Reset 2 1 read-only LVD_0 Reset not generated by LVD. 0 LVD_1 Reset generated by LVD. 0x1 MDM MDM Reset 9 1 read-only MDM_0 Reset was not generated from the MDM reset request. 0 MDM_1 Reset was generated from the MDM reset request. 0x1 PIN Pin Reset 8 1 read-only PIN_0 Reset was not generated from the assertion of RESET_B pin. 0 PIN_1 Reset was generated from the assertion of RESET_B pin. 0x1 POR POR Reset 1 1 read-only POR_0 Reset not generated by POR. 0 POR_1 Reset generated by POR. 0x1 RSTACK Reset Timeout 10 1 read-only RSTACK_0 Reset not generated from Reset Controller Timeout. 0 RSTACK_1 Reset generated from Reset Controller Timeout. 0x1 SCG SCG Reset 12 1 read-only SCG_0 Reset is not generated from an SCG loss of lock or loss of clock. 0 SCG_1 Reset is generated from an SCG loss of lock or loss of clock. 0x1 STOPACK Stop Timeout Reset 11 1 read-only STOPACK_0 Reset not generated by Stop Controller Timeout. 0 STOPACK_1 Reset generated by Stop Controller Timeout. 0x1 SW Software Reset 14 1 read-only SW_0 Reset not generated by software request from core. 0 SW_1 Reset generated by software request from core. 0x1 WAKEUP Wakeup Reset 0 1 read-only WAKEUP_0 Reset not generated by wakeup from VLLS mode. 0 WAKEUP_1 Reset generated by wakeup from VLLS mode. 0x1 WARM Warm Reset 4 1 read-only WARM_0 Reset not generated by Warm Reset source. 0 WARM_1 Reset generated by Warm Reset source. 0x1 WDOG Watchdog Reset 13 1 read-only WDOG_0 Reset is not generated from the WatchDog timeout. 0 WDOG_1 Reset is generated from the WatchDog timeout. 0x1 SSRS Sticky System Reset Status 0x28 32 read-write n 0x0 0x0 CORE0 Core0 Reset 16 1 read-write oneToClear CORE0_0 Reset not generated from Core0 reset source. 0 CORE0_1 Reset generated from Core0 reset source. 0x1 FATAL Fatal Reset 5 1 read-write oneToClear FATAL_0 Reset was not generated by a fatal reset source. 0 FATAL_1 Reset was generated by a fatal reset source. 0x1 HVD HVD Reset 3 1 read-write oneToClear HVD_0 Reset not generated by HVD. 0 HVD_1 Reset generated by HVD. 0x1 JTAG JTAG System Reset 28 1 read-write oneToClear JTAG_0 Reset not generated by JTAG system reset. 0 JTAG_1 Reset generated by JTAG system reset. 0x1 LOCKUP Lockup Reset 15 1 read-write oneToClear LOCKUP_0 Reset not generated by core lockup. 0 LOCKUP_1 Reset generated by core lockup. 0x1 LVD LVD Reset 2 1 read-write oneToClear LVD_0 Reset not generated by LVD. 0 LVD_1 Reset generated by LVD. 0x1 MDM MDM Reset 9 1 read-write oneToClear MDM_0 Reset was not generated from the MDM reset request. 0 MDM_1 Reset was generated from the MDM reset request. 0x1 PIN Pin Reset 8 1 read-write oneToClear PIN_0 Reset was not generated from the RESET_B pin. 0 PIN_1 Reset was generated from the RESET_B pin. 0x1 POR POR Reset 1 1 read-write oneToClear POR_0 Reset not generated by POR. 0 POR_1 Reset generated by POR. 0x1 RSTACK Reset Timeout 10 1 read-write oneToClear RSTACK_0 Reset not generated from Reset Controller Timeout. 0 RSTACK_1 Reset generated from Reset Controller Timeout. 0x1 SCG SCG Reset 12 1 read-write oneToClear SCG_0 Reset is not generated from an SCG loss of lock or loss of clock. 0 SCG_1 Reset is generated from an SCG loss of lock or loss of clock. 0x1 STOPACK Stop Timeout Reset 11 1 read-write oneToClear STOPACK_0 Reset not generated by Stop Controller Timeout. 0 STOPACK_1 Reset generated by Stop Controller Timeout. 0x1 SW Software Reset 14 1 read-write oneToClear SW_0 Reset not generated by software request from core. 0 SW_1 Reset generated by software request from core. 0x1 WAKEUP Wakeup Reset 0 1 read-write oneToClear WAKEUP_0 Reset not generated by wakeup from VLLS mode. 0 WAKEUP_1 Reset generated by wakeup from VLLS mode. 0x1 WARM Warm Reset 4 1 read-write oneToClear WARM_0 Reset not generated by system reset source. 0 WARM_1 Reset generated by system reset source. 0x1 WDOG Watchdog Reset 13 1 read-write oneToClear WDOG_0 Reset is not generated from the WatchDog timeout. 0 WDOG_1 Reset is generated from the WatchDog timeout. 0x1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only FEATURE_171 Default features supported 0xAB MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only SPM SPM SPM 0x0 0x0 0x410 registers n SPM 24 CORELPCNFG CORE LDO Low Power Configuration register 0x104 32 read-write n 0x0 0x0 ALLREFEN All Reference Enable. This bit only has an affect in VLLS0/1. 15 1 read-write ALLREFEN_0 All references are disabled in VLLS. 0 ALLREFEN_1 All references are enabled in VLLS0/1. 0x1 BGBDS Bandgap Buffer Drive Select 4 1 read-write BGBDS_0 Low Drive 0 BGBDS_1 High Drive 0x1 BGBEN Bandgap Buffer Enable 3 1 read-write BGBEN_0 Bandgap buffer not enabled 0 BGBEN_1 Bandgap buffer enabled BGEN must be set when this bit is also set. 0x1 BGEN Bandgap Enable In Low Power Mode Operation 2 1 read-write BGEN_0 Bandgap is disabled in STOP/VLP/LLS and VLLS modes. 0 BGEN_1 Bandgap remains enabled in STOP/VLP/LLS and VLLS modes. 0x1 LPHIDRIVE LPHIDRIVE 14 1 read-write LPHIDRIVE_0 High Drive disabled. 0 LPHIDRIVE_1 High Drive enabled. 0x1 LPOEN LPO Enabled 7 1 read-write LPOEN_0 LPO is disabled in VLLS modes. 0 LPOEN_1 LPO remains enabled in VLLS modes. 0x1 LPSEL LPSEL 1 1 read-write LPSEL_0 Core LDO enters low power state in VLP/Stop modes. 0 LPSEL_1 Core LDO remains in high power state in VLP/Stop modes. If LPSEL = 1 in a low power mode then BGEN must also be set to 1. 0x1 LVDEN LVD Enabled 9 1 read-write LVDEN_0 LVD/HVD is disabled in low power modes. 0 LVDEN_1 LVD/HVD remains enabled in low power modes. BGEN must be set when this bit is also set. 0x1 POREN POR Enabled 8 1 read-write POREN_0 POR brownout is disabled in VLLS0/1 mode. 0 POREN_1 POR brownout remains enabled in VLLS0/1 mode. 0x1 RTCVDDMEN RTCVDDMEN 18 1 read-write RTCVDDMEN_0 RTC voltage monitor disabled in lp modes. 0 RTCVDDMEN_1 RTC voltage monitor enabled in lp modes. Note: voltage monitor is always disabled in VLLS0/1 modes. 0x1 USBVDDMEN USBVDDMEN 17 1 read-write USBVDDMEN_0 USB voltage monitor disabled in lp modes. 0 USBVDDMEN_1 USB voltage monitor enabled in lp modes. Note: voltage monitor is always disabled in VLLS0/1 modes. 0x1 VDDIOVDDMEN VDDIOVDDMEN 16 1 read-write VDDIOVDDMEN_0 VDDIO voltage monitor disabled in lp modes. 0 VDDIOVDDMEN_1 VDDIO voltage monitor enabled in lp modes. Note: voltage monitor is always disabled in VLLS0/1 modes. 0x1 CORERCNFG CORE LDO RUN Configuration Register 0x100 32 read-write n 0x0 0x0 RTCVDDMEN RTCVDDMEN 18 1 read-write RTCVDDMEN_0 RTC voltage monitor disabled in run modes. 0 RTCVDDMEN_1 RTC voltage monitor enabled in run modes. 0x1 USBVDDMEN USBVDDMEN 17 1 read-write USBVDDMEN_0 USB voltage monitor disabled in run modes. 0 USBVDDMEN_1 USB voltage monitor enabled in run modes. 0x1 VDDIOVDDMEN VDDIOVDDMEN 16 1 read-write VDDIOVDDMEN_0 VDDIO voltage monitor disabled in run modes. 0 VDDIOVDDMEN_1 VDDIO voltage monitor enabled in run modes. 0x1 CORESC Core LDO Status And Control register 0x108 32 read-write n 0x0 0x0 ACKISO Acknowledge Isolation 3 1 read-write oneToClear ACKISO_0 Peripherals and I/O pads are in normal run state. 0 ACKISO_1 Certain peripherals and I/O pads are in a isolated and latched state. 0x1 REGONS CORE LDO Regulator in Run Regulation Status 2 1 read-only REGONS_0 Regulator is in low power state or in transition to/from it. 0 REGONS_1 Regulator is in high power state. 0x1 RTCOVRIDE RTCOVRIDE 18 1 read-write RTCOVRIDE_0 RTCVDDOK status set to 1'b0. 0 RTCOVRIDE_1 RTCVDDOK status set to 1'b1. 0x1 RTCVDDOK RTCVDDOK 26 1 read-only TRIM Core LDO Regulator TRIM value 8 6 read-only USBOVRIDE USBOVRIDE 17 1 read-write USBOVRIDE_0 USBVDDOK status set to 1'b0. 0 USBOVRIDE_1 USBVDDOK status set to 1'b1. 0x1 USBVDDOK USBVDDOK 25 1 read-only VDDIOOK VDDIOOK 24 1 read-only VDDIOOVRIDE VDDIOOVRIDE 16 1 read-write VDDIOOVRIDE_0 VDDIOOK status set to 1'b0. 0 VDDIOOVRIDE_1 VDDIOOK status set to 1'b1. 0x1 DCDCC1 DCDC Control Register 1 0x30C 32 read-write n 0x0 0x0 DCDC_LOOPCTRL_EN_CM_HYST DCDC_LOOPCTRL_EN_CM_HYST 26 1 read-write DCDC_LOOPCTRL_EN_DF_HYST DCDC_LOOPCTRL_EN_DF_HYST 27 1 read-write POSLIMIT_BUCK_IN POSLIMIT_BUCK_IN 0 7 read-write DCDCC2 DCDC Control Register 2 0x310 32 read-write n 0x0 0x0 DCDC_BATTMONITOR_BATT_VAL DCDC_BATTMONITOR_BATT_VAL 16 10 read-write DCDC_BATTMONITOR_EN_BATADJ DCDC_BATTMONITOR_EN_BATADJ 15 1 read-write DCDC_LOOPCTRL_HYST_SIGN DCDC_LOOPCTRL_HYST_SIGN 13 1 read-write DCDCC3 DCDC Control Register 3 0x314 32 read-write n 0x0 0x0 DCDC_BYPASS_ADC_MEAS DCDC_BYPASS_ADC_MEAS 0 1 read-write DCDC_MINPWR_DC_HALFCLK DCDC_MINPWR_DC_HALFCLK 24 1 read-write DCDC_MINPWR_DOUBLE_FETS DCDC_MINPWR_DOUBLE_FETS 26 1 read-write DCDC_MINPWR_EXTRA_DOUBLE_FETS DCDC_MINPWR_EXTRA_DOUBLE_FETS 25 1 read-write DCDC_MINPWR_HALF_FETS DCDC_MINPWR_HALF_FETS 27 1 read-write DCDC_VBAT_VALUE DCDC_VBAT_VALUE 2 3 read-write DCDC_VDD1P2CTRL_ADJTN DCDC_VDD1P2CTRL_ADJTN 16 4 read-write DCDC_VDD1P2CTRL_DISABLE_STEP DCDC_VDD1P2CTRL_DISABLE_STEP 30 1 read-write DCDC_VDD1P8CTRL_DISABLE_STEP DCDC_VDD1P8CTRL_DISABLE_STEP 31 1 read-write DCDCC4 DCDC Control Register 4 0x318 32 read-write n 0x0 0x0 INTEGRATOR_VALUE INTEGRATOR VALUE 0 19 read-write INTEGRATOR_VALUE_SELECT INTEGRATOR VALUE SELECT 19 1 read-write INTEGRATOR_VALUE_SELECT_0 Select the saved value in hardware 0 INTEGRATOR_VALUE_SELECT_1 Select the integrator value in this register 0x1 PULSE_RUN_SPEEDUP PULSE RUN SPEEDUP 20 1 read-write DCDCC6 DCDC Control Register 6 0x320 32 read-write n 0x0 0x0 DCDC_HSVDD_TRIM DCDC_HSVDD_TRIM 24 4 read-write DCDC_VDD1P2CTRL_TRG_BUCK DCDC_VDD1P2CTRL_TRG_BUCK 8 4 read-write DCDC_VDD1P8CTRL_TRG DCDC_VDD1P8CTRL_TRG 0 5 read-write DCDCSC DCDC Status Control Register 0x304 32 read-write n 0x0 0x0 CLKFLT_FAULT DCDC CLKFLT Fault Status Flag 30 1 read-write oneToClear DCDC_DISABLE_AUTO_CLK_SWITCH DCDC_DISABLE_AUTO_CLK_SWITCH 1 1 read-write DCDC_LESS_I DCDC_LESS_I 25 1 read-write DCDC_PWD_OSC_INT DCDC_PWD_OSC_INT 3 1 read-write DCDC_SEL_CLK DCDC_SEL_CLK 2 1 read-write DCDC_STS_DC_OK DCDC_STS_DC_OK 31 1 read-only DCDC_VBAT_DIV_CTRL DCDC_VBAT_DIV_CTRL 10 2 read-write DCDC_VBAT_DIV_CTRL_0 OFF 0 DCDC_VBAT_DIV_CTRL_1 VBAT 0x1 DCDC_VBAT_DIV_CTRL_2 VBAT / 2 0x2 DCDC_VBAT_DIV_CTRL_3 VBAT / 4 0x3 PWD_CMP_OFFSET PWD_CMP_OFFSET 26 1 read-write HVDSC1 High Voltage Detect Status And Control 1 register 0x114 32 read-write n 0x0 0x0 VDD_HVDACK VDD High-Voltage Detect Acknowledge 22 1 write-only VDD_HVDF VDD High-Voltage Detect Flag 23 1 read-only VDD_HVDF_0 Vdd High-voltage event not detected 0 VDD_HVDF_1 Vdd High-voltage event detected 0x1 VDD_HVDIE VDD High-Voltage Detect Interrupt Enable 21 1 read-write VDD_HVDIE_0 Hardware interrupt disabled (use polling) 0 VDD_HVDIE_1 Request a hardware interrupt when HVDF = 1 0x1 VDD_HVDRE VDD High-Voltage Detect Reset Enable 20 1 read-write VDD_HVDRE_0 VDD HVDF does not generate hardware resets 0 VDD_HVDRE_1 Force an MCU reset when VDD_HVDF = 1 0x1 VDD_HVDV VDD High-Voltage Detect Voltage Select 16 1 read-write VDD_HVDV_0 no description available 0 VDD_HVDV_1 no description available 0x1 LPCTRL Low Power Control Register 0x14 32 read-write n 0x0 0x0 REGSEL REGSEL 0 3 read-write LPREQPINCNTRL LP Request Pin Control Register 0x40C 32 read-write n 0x0 0x0 LPREQOE Low Power Request Output Enable Register 0 1 read-write LPREQOE_0 Low Power request output pin not enabled. 0 LPREQOE_1 Low Power request output pin enabled. 0x1 POLARITY Low Power Request Output Pin Polarity Control Register 1 1 read-write POLARITY_0 High true polarity. 0 POLARITY_1 Low true polarity. 0x1 LVDSC1 Low Voltage Detect Status and Control 1 register 0x10C 32 read-write n 0x0 0x0 COREVDD_LVDACK Low-Voltage Detect Acknowledge 6 1 write-only COREVDD_LVDF Low-Voltage Detect Flag 7 1 read-only COREVDD_LVDF_0 Low-voltage event not detected 0 COREVDD_LVDF_1 Low-voltage event detected 0x1 COREVDD_LVDIE Low-Voltage Detect Interrupt Enable 5 1 read-write COREVDD_LVDIE_0 Hardware interrupt disabled (use polling) 0 COREVDD_LVDIE_1 Request a hardware interrupt when LVDF = 1 0x1 COREVDD_LVDRE Core Low-Voltage Detect Reset Enable 4 1 read-write COREVDD_LVDRE_0 COREVDD_LVDF does not generate hardware resets 0 COREVDD_LVDRE_1 Force an MCU reset when CORE_LVDF = 1 0x1 VDD_LVDACK VDD Low-Voltage Detect Acknowledge 22 1 write-only VDD_LVDF VDD Low-Voltage Detect Flag 23 1 read-only VDD_LVDF_0 Low-voltage event not detected 0 VDD_LVDF_1 Low-voltage event detected 0x1 VDD_LVDIE VDD Low-Voltage Detect Interrupt Enable 21 1 read-write VDD_LVDIE_0 Hardware interrupt disabled (use polling) 0 VDD_LVDIE_1 Request a hardware interrupt when VDD_LVDF = 1 0x1 VDD_LVDRE VDD Low-Voltage Detect Reset Enable 20 1 read-write VDD_LVDRE_0 VDD_LVDF does not generate hardware resets 0 VDD_LVDRE_1 Force an MCU reset when VDD_LVDF = 1 0x1 VDD_LVDV VDD Low-Voltage Detect Voltage Select 16 2 read-write VDD_LVDV_0 no description available 0 VDD_LVDV_1 no description available 0x1 LVDSC2 Low Voltage Detect Status and Control 2 register 0x110 32 read-write n 0x0 0x0 VDD_LVWACK VDD Low-Voltage Warning Acknowledge 22 1 write-only VDD_LVWF VDD Low-Voltage Warning Flag 23 1 read-only VDD_LVWF_0 Low-voltage warning event not detected 0 VDD_LVWF_1 Low-voltage warning event detected 0x1 VDD_LVWIE VDD Low-Voltage Warning Interrupt Enable 21 1 read-write VDD_LVWIE_0 Hardware interrupt disabled (use polling) 0 VDD_LVWIE_1 Request a hardware interrupt when VDD_LVWF = 1 0x1 VDD_LVWV VDD Low-Voltage Warning Voltage Select 16 2 read-write VDD_LVWV_0 no description available 0 VDD_LVWV_1 no description available 0x1 VDD_LVWV_2 no description available 0x2 VDD_LVWV_3 no description available 0x3 RCTRL Run Control Register 0x10 32 read-write n 0x0 0x0 REGSEL REGSEL 0 3 read-write RFLDOLPCNFG RF LDO Low Power Configuration register 0x200 32 read-write n 0x0 0x0 LPSEL LPSEL 1 1 read-write LPSEL_0 RF LDO regulator enters low power state in VLP/Stop modes. 0 LPSEL_1 RF LDO regulator remains in high power state in VLP/Stop modes. 0x1 RFLDOSC RF LDO Status And Control register 0x204 32 read-write n 0x0 0x0 IOREGVSEL IO Regulator Voltage Select 0 1 read-write IOREGVSEL_0 Regulate to 1.8V. 0 IOREGVSEL_1 Regulate to 1.5V. 0x1 IOSPARE_OUT IO Spare Outputs 26 2 read-write IOSSSEL IO 1.8 Reg Soft Start Select 16 3 read-write IOSSSEL_0 Soft Start duration set to 110us. 0 IOSSSEL_1 Soft Start duration set to 95us. 0x1 IOSSSEL_2 Soft Start duration set to 60us. 0x2 IOSSSEL_3 Soft Start duration set to 48us. 0x3 IOSSSEL_4 Soft Start duration set to 38us. 0x4 IOSSSEL_5 Soft Start duration set to 30us. 0x5 IOSSSEL_6 Soft Start duration set to 24us. 0x6 IOSSSEL_7 Soft Start duration set to 17us. 0x7 IOTRIM IO Regulator TRIM value 8 5 read-only ISINKEN ISINKEN 5 1 read-write ISINKEN_0 Disable current sink feature of low power regulator. 0 ISINKEN_1 Enable current sink feature of low power regulator. 0x1 SSDONE IO Soft Start Done Status Registers 24 1 read-only VDD1P8SEL VDD 1p8 SNS Pin Select 4 1 read-write VDD1P8SEL_0 VDD1p8_SNS0 selected. 0 VDD1P8SEL_1 VDD1p8_SNS1 selected. 0x1 RSR Regulator Status Register 0x8 32 read-only n 0x0 0x0 MCUPMSTAT MCU Power Mode Status 16 5 read-only MCUPMSTAT_1 Last Low Power mode is STOP. 0x1 MCUPMSTAT_16 Last Low Power mode is VLLS01. 0x10 MCUPMSTAT_2 Last Low Power mode is VLPS. 0x2 MCUPMSTAT_4 Last Low Power mode is LLS. 0x4 MCUPMSTAT_8 Last Low Power mode is VLLS23. 0x8 REGSEL REGSEL 0 3 read-only RFPMSTAT RADIO Power Mode Status 24 3 read-only RFPMSTAT_1 Current Power mode is VLPS. 0x1 RFPMSTAT_2 Current Power mode is LLS. 0x2 RFPMSTAT_4 Current Power mode is VLLS. 0x4 RFRUNFORCE RADIO Run Force Power Mode Status 27 1 read-only RFRUNFORCE_0 Radio Run Force Regulator Off 0 RFRUNFORCE_1 Radio Run Force Regulator On. 0x1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Specification Number 0 16 read-only FEATURE_0 Standard features implemented. 0 MAJOR MAJOR 24 8 read-only MINOR MINOR 16 8 read-only TPM0 TPM TPM0 0x0 0x0 0x88 registers n TPM0 31 CHANNEL[0]-CSC Channel (n) Status and Control 0x20 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHANNEL[0]-CV Channel (n) Value 0x24 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CHANNEL[1]-CHANNEL[0]-CSC Channel (n) Status and Control 0x48 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHANNEL[1]-CHANNEL[0]-CV Channel (n) Value 0x4C 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CSC Channel (n) Status and Control 0x78 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CV Channel (n) Value 0x7C 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CSC Channel (n) Status and Control 0xB0 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CV Channel (n) Value 0xB4 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CSC Channel (n) Status and Control 0xF0 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CV Channel (n) Value 0xF4 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CSC Channel (n) Status and Control 0x138 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CV Channel (n) Value 0x13C 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CNT Counter 0x14 32 read-write n 0x0 0x0 COUNT Counter value 0 16 read-write COMBINE Combine Channel Register 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels 0 and 1 0 1 read-write COMBINE0_0 Channels 0 and 1 are independent. 0 COMBINE0_1 Channels 0 and 1 are combined. 0x1 COMBINE1 Combine Channels 2 and 3 8 1 read-write COMBINE1_0 Channels 2 and 3 are independent. 0 COMBINE1_1 Channels 2 and 3 are combined. 0x1 COMBINE2 Combine Channels 4 and 5 16 1 read-write COMBINE2_0 Channels 4 and 5 are independent. 0 COMBINE2_1 Channels 4 and 5 are combined. 0x1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write COMSWAP0_0 Even channel is used for input capture and 1st compare. 0 COMSWAP0_1 Odd channel is used for input capture and 1st compare. 0x1 COMSWAP1 Combine Channels 2 and 3 Swap 9 1 read-write COMSWAP1_0 Even channel is used for input capture and 1st compare. 0 COMSWAP1_1 Odd channel is used for input capture and 1st compare. 0x1 COMSWAP2 Combine Channels 4 and 5 Swap 17 1 read-write COMSWAP2_0 Even channel is used for input capture and 1st compare. 0 COMSWAP2_1 Odd channel is used for input capture and 1st compare. 0x1 CONF Configuration 0x84 32 read-write n 0x0 0x0 CPOT Counter Pause On Trigger 19 1 read-write CROT Counter Reload On Trigger 18 1 read-write CROT_0 Counter is not reloaded due to a rising edge on the selected input trigger 0 CROT_1 Counter is reloaded when a rising edge is detected on the selected input trigger 0x1 CSOO Counter Stop On Overflow 17 1 read-write CSOO_0 no description available 0 CSOO_1 no description available 0x1 CSOT Counter Start on Trigger 16 1 read-write CSOT_0 no description available 0 CSOT_1 no description available 0x1 DBGMODE Debug Mode 6 2 read-write DBGMODE_0 no description available 0 DBGMODE_3 no description available 0x3 DOZEEN Doze Enable 5 1 read-write DOZEEN_0 no description available 0 DOZEEN_1 no description available 0x1 GTBEEN Global time base enable 9 1 read-write GTBEEN_0 no description available 0 GTBEEN_1 All channels use an externally generated global timebase as their timebase 0x1 GTBSYNC Global Time Base Synchronization 8 1 read-write GTBSYNC_0 Global timebase synchronization disabled. 0 GTBSYNC_1 Global timebase synchronization enabled. 0x1 TRGPOL Trigger Polarity 22 1 read-write TRGPOL_0 Trigger is active high. 0 TRGPOL_1 Trigger is active low. 0x1 TRGSEL Trigger Select 24 2 read-write TRGSEL_1 Channel 0 pin input capture 0x1 TRGSEL_2 Channel 1 pin input capture 0x2 TRGSEL_3 Channel 0 or Channel 1 pin input capture 0x3 TRGSRC Trigger Source 23 1 read-write TRGSRC_0 Trigger source selected by TRGSEL is external. 0 TRGSRC_1 Trigger source selected by TRGSEL is internal (channel pin input capture). 0x1 CSC Channel (n) Status and Control 0x0 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CV Channel (n) Value 0x4 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write FILTER Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write CH2FVAL Channel 2 Filter Value 8 4 read-write CH3FVAL Channel 3 Filter Value 12 4 read-write CH4FVAL Channel 4 Filter Value 16 4 read-write CH5FVAL Channel 5 Filter Value 20 4 read-write GLOBAL TPM Global Register 0x8 32 read-write n 0x0 0x0 NOUPDATE No Update 0 1 read-write NOUPDATE_0 Internal double buffered registers update as normal. 0 NOUPDATE_1 Internal double buffered registers do not update. 0x1 RST Software Reset 1 1 read-write RST_0 Module is not reset. 0 RST_1 Module is reset. 0x1 MOD Modulo 0x18 32 read-write n 0x0 0x0 MOD Modulo value 0 16 read-write PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 CHAN Channel Count 0 8 read-only TRIG Trigger Count 8 8 read-only WIDTH Counter Width 16 8 read-only POL Channel Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write POL0_0 The channel polarity is active high. 0 POL0_1 The channel polarity is active low. 0x1 POL1 Channel 1 Polarity 1 1 read-write POL1_0 The channel polarity is active high. 0 POL1_1 The channel polarity is active low. 0x1 POL2 Channel 2 Polarity 2 1 read-write POL2_0 The channel polarity is active high. 0 POL2_1 The channel polarity is active low. 0x1 POL3 Channel 3 Polarity 3 1 read-write POL3_0 The channel polarity is active high. 0 POL3_1 The channel polarity is active low. 0x1 POL4 Channel 4 Polarity 4 1 read-write POL4_0 The channel polarity is active high 0 POL4_1 The channel polarity is active low. 0x1 POL5 Channel 5 Polarity 5 1 read-write POL5_0 The channel polarity is active high. 0 POL5_1 The channel polarity is active low. 0x1 QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write n 0x0 0x0 QUADEN QUADEN 0 1 read-write QUADEN_0 Quadrature decoder mode is disabled. 0 QUADEN_1 Quadrature decoder mode is enabled. 0x1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only QUADIR_0 Counter direction is decreasing (counter decrement). 0 QUADIR_1 Counter direction is increasing (counter increment). 0x1 QUADMODE Quadrature Decoder Mode 3 1 read-write QUADMODE_0 Phase encoding mode. 0 QUADMODE_1 Count and direction encoding mode. 0x1 TOFDIR TOFDIR 1 1 read-only TOFDIR_0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). 0 TOFDIR_1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). 0x1 SC Status and Control 0x10 32 read-write n 0x0 0x0 CMOD Clock Mode Selection 3 2 read-write CMOD_0 TPM counter is disabled 0 CMOD_1 TPM counter increments on every TPM counter clock 0x1 CMOD_2 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock 0x2 CMOD_3 no description available 0x3 CPWMS Center-Aligned PWM Select 5 1 read-write CPWMS_0 no description available 0 CPWMS_1 no description available 0x1 DMA DMA Enable 8 1 read-write DMA_0 Disables DMA transfers. 0 DMA_1 Enables DMA transfers. 0x1 PS Prescale Factor Selection 0 3 read-write PS_0 Divide by 1 0 PS_1 Divide by 2 0x1 PS_2 Divide by 4 0x2 PS_3 Divide by 8 0x3 PS_4 Divide by 16 0x4 PS_5 Divide by 32 0x5 PS_6 Divide by 64 0x6 PS_7 Divide by 128 0x7 TOF Timer Overflow Flag 7 1 read-write oneToClear TOF_0 no description available 0 TOF_1 no description available 0x1 TOIE Timer Overflow Interrupt Enable 6 1 read-write TOIE_0 no description available 0 TOIE_1 Enable TOF interrupts. An interrupt is generated when TOF equals one. 0x1 STATUS Capture and Compare Status 0x1C 32 read-write n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-write oneToClear CH0F_0 No channel event has occurred. 0 CH0F_1 A channel event has occurred. 0x1 CH1F Channel 1 Flag 1 1 read-write oneToClear CH1F_0 No channel event has occurred. 0 CH1F_1 A channel event has occurred. 0x1 CH2F Channel 2 Flag 2 1 read-write oneToClear CH2F_0 No channel event has occurred. 0 CH2F_1 A channel event has occurred. 0x1 CH3F Channel 3 Flag 3 1 read-write oneToClear CH3F_0 No channel event has occurred. 0 CH3F_1 A channel event has occurred. 0x1 CH4F Channel 4 Flag 4 1 read-write oneToClear CH4F_0 No channel event has occurred. 0 CH4F_1 A channel event has occurred. 0x1 CH5F Channel 5 Flag 5 1 read-write oneToClear CH5F_0 No channel event has occurred. 0 CH5F_1 A channel event has occurred. 0x1 TOF Timer Overflow Flag 8 1 read-write oneToClear TOF_0 no description available 0 TOF_1 no description available 0x1 TRIG Channel Trigger 0x6C 32 read-write n 0x0 0x0 TRIG0 Channel 0 Trigger 0 1 read-write TRIG0_0 No effect. 0 TRIG0_1 Configures trigger input 0 to be used by channel 0. 0x1 TRIG1 Channel 1 Trigger 1 1 read-write TRIG1_0 No effect. 0 TRIG1_1 Configures trigger input 1 to be used by channel 1. 0x1 TRIG2 Channel 2 Trigger 2 1 read-write TRIG2_0 No effect. 0 TRIG2_1 Configures trigger input 0 to be used by channel 2. 0x1 TRIG3 Channel 3 Trigger 3 1 read-write TRIG3_0 No effect. 0 TRIG3_1 Configures trigger input 1 to be used by channel 3. 0x1 TRIG4 Channel 4 Trigger 4 1 read-write TRIG4_0 No effect. 0 TRIG4_1 Configures trigger input 0 to be used by channel 4. 0x1 TRIG5 Channel 5 Trigger 5 1 read-write TRIG5_0 No effect. 0 TRIG5_1 Configures trigger input 1 to be used by channel 5. 0x1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Identification Number 0 16 read-only FEATURE_1 Standard feature set. 0x1 FEATURE_3 Standard feature set with Filter and Combine registers implemented. 0x3 FEATURE_7 Standard feature set with Filter, Combine and Quadrature registers implemented. 0x7 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only TPM1 TPM TPM1 0x0 0x0 0x88 registers n TPM1 32 CHANNEL[0]-CSC Channel (n) Status and Control 0x20 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHANNEL[0]-CV Channel (n) Value 0x24 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CHANNEL[1]-CHANNEL[0]-CSC Channel (n) Status and Control 0x48 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHANNEL[1]-CHANNEL[0]-CV Channel (n) Value 0x4C 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CNT Counter 0x14 32 read-write n 0x0 0x0 COUNT Counter value 0 16 read-write COMBINE Combine Channel Register 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels 0 and 1 0 1 read-write COMBINE0_0 Channels 0 and 1 are independent. 0 COMBINE0_1 Channels 0 and 1 are combined. 0x1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write COMSWAP0_0 Even channel is used for input capture and 1st compare. 0 COMSWAP0_1 Odd channel is used for input capture and 1st compare. 0x1 CONF Configuration 0x84 32 read-write n 0x0 0x0 CPOT Counter Pause On Trigger 19 1 read-write CROT Counter Reload On Trigger 18 1 read-write CROT_0 Counter is not reloaded due to a rising edge on the selected input trigger 0 CROT_1 Counter is reloaded when a rising edge is detected on the selected input trigger 0x1 CSOO Counter Stop On Overflow 17 1 read-write CSOO_0 no description available 0 CSOO_1 no description available 0x1 CSOT Counter Start on Trigger 16 1 read-write CSOT_0 no description available 0 CSOT_1 no description available 0x1 DBGMODE Debug Mode 6 2 read-write DBGMODE_0 no description available 0 DBGMODE_3 no description available 0x3 DOZEEN Doze Enable 5 1 read-write DOZEEN_0 no description available 0 DOZEEN_1 no description available 0x1 GTBEEN Global time base enable 9 1 read-write GTBEEN_0 no description available 0 GTBEEN_1 All channels use an externally generated global timebase as their timebase 0x1 GTBSYNC Global Time Base Synchronization 8 1 read-write GTBSYNC_0 Global timebase synchronization disabled. 0 GTBSYNC_1 Global timebase synchronization enabled. 0x1 TRGPOL Trigger Polarity 22 1 read-write TRGPOL_0 Trigger is active high. 0 TRGPOL_1 Trigger is active low. 0x1 TRGSEL Trigger Select 24 2 read-write TRGSEL_1 Channel 0 pin input capture 0x1 TRGSEL_2 Channel 1 pin input capture 0x2 TRGSEL_3 Channel 0 or Channel 1 pin input capture 0x3 TRGSRC Trigger Source 23 1 read-write TRGSRC_0 Trigger source selected by TRGSEL is external. 0 TRGSRC_1 Trigger source selected by TRGSEL is internal (channel pin input capture). 0x1 CSC Channel (n) Status and Control 0x0 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CV Channel (n) Value 0x4 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write FILTER Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write GLOBAL TPM Global Register 0x8 32 read-write n 0x0 0x0 NOUPDATE No Update 0 1 read-write NOUPDATE_0 Internal double buffered registers update as normal. 0 NOUPDATE_1 Internal double buffered registers do not update. 0x1 RST Software Reset 1 1 read-write RST_0 Module is not reset. 0 RST_1 Module is reset. 0x1 MOD Modulo 0x18 32 read-write n 0x0 0x0 MOD Modulo value 0 16 read-write PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 CHAN Channel Count 0 8 read-only TRIG Trigger Count 8 8 read-only WIDTH Counter Width 16 8 read-only POL Channel Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write POL0_0 The channel polarity is active high. 0 POL0_1 The channel polarity is active low. 0x1 POL1 Channel 1 Polarity 1 1 read-write POL1_0 The channel polarity is active high. 0 POL1_1 The channel polarity is active low. 0x1 QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write n 0x0 0x0 QUADEN QUADEN 0 1 read-write QUADEN_0 Quadrature decoder mode is disabled. 0 QUADEN_1 Quadrature decoder mode is enabled. 0x1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only QUADIR_0 Counter direction is decreasing (counter decrement). 0 QUADIR_1 Counter direction is increasing (counter increment). 0x1 QUADMODE Quadrature Decoder Mode 3 1 read-write QUADMODE_0 Phase encoding mode. 0 QUADMODE_1 Count and direction encoding mode. 0x1 TOFDIR TOFDIR 1 1 read-only TOFDIR_0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). 0 TOFDIR_1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). 0x1 SC Status and Control 0x10 32 read-write n 0x0 0x0 CMOD Clock Mode Selection 3 2 read-write CMOD_0 TPM counter is disabled 0 CMOD_1 TPM counter increments on every TPM counter clock 0x1 CMOD_2 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock 0x2 CMOD_3 no description available 0x3 CPWMS Center-Aligned PWM Select 5 1 read-write CPWMS_0 no description available 0 CPWMS_1 no description available 0x1 DMA DMA Enable 8 1 read-write DMA_0 Disables DMA transfers. 0 DMA_1 Enables DMA transfers. 0x1 PS Prescale Factor Selection 0 3 read-write PS_0 Divide by 1 0 PS_1 Divide by 2 0x1 PS_2 Divide by 4 0x2 PS_3 Divide by 8 0x3 PS_4 Divide by 16 0x4 PS_5 Divide by 32 0x5 PS_6 Divide by 64 0x6 PS_7 Divide by 128 0x7 TOF Timer Overflow Flag 7 1 read-write oneToClear TOF_0 no description available 0 TOF_1 no description available 0x1 TOIE Timer Overflow Interrupt Enable 6 1 read-write TOIE_0 no description available 0 TOIE_1 Enable TOF interrupts. An interrupt is generated when TOF equals one. 0x1 STATUS Capture and Compare Status 0x1C 32 read-write n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-write oneToClear CH0F_0 No channel event has occurred. 0 CH0F_1 A channel event has occurred. 0x1 CH1F Channel 1 Flag 1 1 read-write oneToClear CH1F_0 No channel event has occurred. 0 CH1F_1 A channel event has occurred. 0x1 TOF Timer Overflow Flag 8 1 read-write oneToClear TOF_0 no description available 0 TOF_1 no description available 0x1 TRIG Channel Trigger 0x6C 32 read-write n 0x0 0x0 TRIG0 Channel 0 Trigger 0 1 read-write TRIG0_0 No effect. 0 TRIG0_1 Configures trigger input 0 to be used by channel 0. 0x1 TRIG1 Channel 1 Trigger 1 1 read-write TRIG1_0 No effect. 0 TRIG1_1 Configures trigger input 1 to be used by channel 1. 0x1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Identification Number 0 16 read-only FEATURE_1 Standard feature set. 0x1 FEATURE_3 Standard feature set with Filter and Combine registers implemented. 0x3 FEATURE_7 Standard feature set with Filter, Combine and Quadrature registers implemented. 0x7 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only TPM2 TPM TPM2 0x0 0x0 0x88 registers n TPM2 33 CHANNEL[0]-CSC Channel (n) Status and Control 0x20 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHANNEL[0]-CV Channel (n) Value 0x24 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CHANNEL[1]-CHANNEL[0]-CSC Channel (n) Status and Control 0x48 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHANNEL[1]-CHANNEL[0]-CV Channel (n) Value 0x4C 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CSC Channel (n) Status and Control 0x78 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CV Channel (n) Value 0x7C 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CSC Channel (n) Status and Control 0xB0 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CV Channel (n) Value 0xB4 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CSC Channel (n) Status and Control 0xF0 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CV Channel (n) Value 0xF4 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CSC Channel (n) Status and Control 0x138 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CV Channel (n) Value 0x13C 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CNT Counter 0x14 32 read-write n 0x0 0x0 COUNT Counter value 0 16 read-write COMBINE Combine Channel Register 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels 0 and 1 0 1 read-write COMBINE0_0 Channels 0 and 1 are independent. 0 COMBINE0_1 Channels 0 and 1 are combined. 0x1 COMBINE1 Combine Channels 2 and 3 8 1 read-write COMBINE1_0 Channels 2 and 3 are independent. 0 COMBINE1_1 Channels 2 and 3 are combined. 0x1 COMBINE2 Combine Channels 4 and 5 16 1 read-write COMBINE2_0 Channels 4 and 5 are independent. 0 COMBINE2_1 Channels 4 and 5 are combined. 0x1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write COMSWAP0_0 Even channel is used for input capture and 1st compare. 0 COMSWAP0_1 Odd channel is used for input capture and 1st compare. 0x1 COMSWAP1 Combine Channels 2 and 3 Swap 9 1 read-write COMSWAP1_0 Even channel is used for input capture and 1st compare. 0 COMSWAP1_1 Odd channel is used for input capture and 1st compare. 0x1 COMSWAP2 Combine Channels 4 and 5 Swap 17 1 read-write COMSWAP2_0 Even channel is used for input capture and 1st compare. 0 COMSWAP2_1 Odd channel is used for input capture and 1st compare. 0x1 CONF Configuration 0x84 32 read-write n 0x0 0x0 CPOT Counter Pause On Trigger 19 1 read-write CROT Counter Reload On Trigger 18 1 read-write CROT_0 Counter is not reloaded due to a rising edge on the selected input trigger 0 CROT_1 Counter is reloaded when a rising edge is detected on the selected input trigger 0x1 CSOO Counter Stop On Overflow 17 1 read-write CSOO_0 no description available 0 CSOO_1 no description available 0x1 CSOT Counter Start on Trigger 16 1 read-write CSOT_0 no description available 0 CSOT_1 no description available 0x1 DBGMODE Debug Mode 6 2 read-write DBGMODE_0 no description available 0 DBGMODE_3 no description available 0x3 DOZEEN Doze Enable 5 1 read-write DOZEEN_0 no description available 0 DOZEEN_1 no description available 0x1 GTBEEN Global time base enable 9 1 read-write GTBEEN_0 no description available 0 GTBEEN_1 All channels use an externally generated global timebase as their timebase 0x1 GTBSYNC Global Time Base Synchronization 8 1 read-write GTBSYNC_0 Global timebase synchronization disabled. 0 GTBSYNC_1 Global timebase synchronization enabled. 0x1 TRGPOL Trigger Polarity 22 1 read-write TRGPOL_0 Trigger is active high. 0 TRGPOL_1 Trigger is active low. 0x1 TRGSEL Trigger Select 24 2 read-write TRGSEL_1 Channel 0 pin input capture 0x1 TRGSEL_2 Channel 1 pin input capture 0x2 TRGSEL_3 Channel 0 or Channel 1 pin input capture 0x3 TRGSRC Trigger Source 23 1 read-write TRGSRC_0 Trigger source selected by TRGSEL is external. 0 TRGSRC_1 Trigger source selected by TRGSEL is internal (channel pin input capture). 0x1 CSC Channel (n) Status and Control 0x0 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CV Channel (n) Value 0x4 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write FILTER Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write CH2FVAL Channel 2 Filter Value 8 4 read-write CH3FVAL Channel 3 Filter Value 12 4 read-write CH4FVAL Channel 4 Filter Value 16 4 read-write CH5FVAL Channel 5 Filter Value 20 4 read-write GLOBAL TPM Global Register 0x8 32 read-write n 0x0 0x0 NOUPDATE No Update 0 1 read-write NOUPDATE_0 Internal double buffered registers update as normal. 0 NOUPDATE_1 Internal double buffered registers do not update. 0x1 RST Software Reset 1 1 read-write RST_0 Module is not reset. 0 RST_1 Module is reset. 0x1 MOD Modulo 0x18 32 read-write n 0x0 0x0 MOD Modulo value 0 16 read-write PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 CHAN Channel Count 0 8 read-only TRIG Trigger Count 8 8 read-only WIDTH Counter Width 16 8 read-only POL Channel Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write POL0_0 The channel polarity is active high. 0 POL0_1 The channel polarity is active low. 0x1 POL1 Channel 1 Polarity 1 1 read-write POL1_0 The channel polarity is active high. 0 POL1_1 The channel polarity is active low. 0x1 POL2 Channel 2 Polarity 2 1 read-write POL2_0 The channel polarity is active high. 0 POL2_1 The channel polarity is active low. 0x1 POL3 Channel 3 Polarity 3 1 read-write POL3_0 The channel polarity is active high. 0 POL3_1 The channel polarity is active low. 0x1 POL4 Channel 4 Polarity 4 1 read-write POL4_0 The channel polarity is active high 0 POL4_1 The channel polarity is active low. 0x1 POL5 Channel 5 Polarity 5 1 read-write POL5_0 The channel polarity is active high. 0 POL5_1 The channel polarity is active low. 0x1 QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write n 0x0 0x0 QUADEN QUADEN 0 1 read-write QUADEN_0 Quadrature decoder mode is disabled. 0 QUADEN_1 Quadrature decoder mode is enabled. 0x1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only QUADIR_0 Counter direction is decreasing (counter decrement). 0 QUADIR_1 Counter direction is increasing (counter increment). 0x1 QUADMODE Quadrature Decoder Mode 3 1 read-write QUADMODE_0 Phase encoding mode. 0 QUADMODE_1 Count and direction encoding mode. 0x1 TOFDIR TOFDIR 1 1 read-only TOFDIR_0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). 0 TOFDIR_1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). 0x1 SC Status and Control 0x10 32 read-write n 0x0 0x0 CMOD Clock Mode Selection 3 2 read-write CMOD_0 TPM counter is disabled 0 CMOD_1 TPM counter increments on every TPM counter clock 0x1 CMOD_2 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock 0x2 CMOD_3 no description available 0x3 CPWMS Center-Aligned PWM Select 5 1 read-write CPWMS_0 no description available 0 CPWMS_1 no description available 0x1 DMA DMA Enable 8 1 read-write DMA_0 Disables DMA transfers. 0 DMA_1 Enables DMA transfers. 0x1 PS Prescale Factor Selection 0 3 read-write PS_0 Divide by 1 0 PS_1 Divide by 2 0x1 PS_2 Divide by 4 0x2 PS_3 Divide by 8 0x3 PS_4 Divide by 16 0x4 PS_5 Divide by 32 0x5 PS_6 Divide by 64 0x6 PS_7 Divide by 128 0x7 TOF Timer Overflow Flag 7 1 read-write oneToClear TOF_0 no description available 0 TOF_1 no description available 0x1 TOIE Timer Overflow Interrupt Enable 6 1 read-write TOIE_0 no description available 0 TOIE_1 Enable TOF interrupts. An interrupt is generated when TOF equals one. 0x1 STATUS Capture and Compare Status 0x1C 32 read-write n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-write oneToClear CH0F_0 No channel event has occurred. 0 CH0F_1 A channel event has occurred. 0x1 CH1F Channel 1 Flag 1 1 read-write oneToClear CH1F_0 No channel event has occurred. 0 CH1F_1 A channel event has occurred. 0x1 CH2F Channel 2 Flag 2 1 read-write oneToClear CH2F_0 No channel event has occurred. 0 CH2F_1 A channel event has occurred. 0x1 CH3F Channel 3 Flag 3 1 read-write oneToClear CH3F_0 No channel event has occurred. 0 CH3F_1 A channel event has occurred. 0x1 CH4F Channel 4 Flag 4 1 read-write oneToClear CH4F_0 No channel event has occurred. 0 CH4F_1 A channel event has occurred. 0x1 CH5F Channel 5 Flag 5 1 read-write oneToClear CH5F_0 No channel event has occurred. 0 CH5F_1 A channel event has occurred. 0x1 TOF Timer Overflow Flag 8 1 read-write oneToClear TOF_0 no description available 0 TOF_1 no description available 0x1 TRIG Channel Trigger 0x6C 32 read-write n 0x0 0x0 TRIG0 Channel 0 Trigger 0 1 read-write TRIG0_0 No effect. 0 TRIG0_1 Configures trigger input 0 to be used by channel 0. 0x1 TRIG1 Channel 1 Trigger 1 1 read-write TRIG1_0 No effect. 0 TRIG1_1 Configures trigger input 1 to be used by channel 1. 0x1 TRIG2 Channel 2 Trigger 2 1 read-write TRIG2_0 No effect. 0 TRIG2_1 Configures trigger input 0 to be used by channel 2. 0x1 TRIG3 Channel 3 Trigger 3 1 read-write TRIG3_0 No effect. 0 TRIG3_1 Configures trigger input 1 to be used by channel 3. 0x1 TRIG4 Channel 4 Trigger 4 1 read-write TRIG4_0 No effect. 0 TRIG4_1 Configures trigger input 0 to be used by channel 4. 0x1 TRIG5 Channel 5 Trigger 5 1 read-write TRIG5_0 No effect. 0 TRIG5_1 Configures trigger input 1 to be used by channel 5. 0x1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Identification Number 0 16 read-only FEATURE_1 Standard feature set. 0x1 FEATURE_3 Standard feature set with Filter and Combine registers implemented. 0x3 FEATURE_7 Standard feature set with Filter, Combine and Quadrature registers implemented. 0x7 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only TPM3 TPM LPTPM3 0x0 0x0 0x88 registers n TPM3 60 CHANNEL[0]-CSC Channel (n) Status and Control 0x20 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHANNEL[0]-CV Channel (n) Value 0x24 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CHANNEL[1]-CHANNEL[0]-CSC Channel (n) Status and Control 0x48 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CHANNEL[1]-CHANNEL[0]-CV Channel (n) Value 0x4C 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write CNT Counter 0x14 32 read-write n 0x0 0x0 COUNT Counter value 0 16 read-write COMBINE Combine Channel Register 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels 0 and 1 0 1 read-write COMBINE0_0 Channels 0 and 1 are independent. 0 COMBINE0_1 Channels 0 and 1 are combined. 0x1 COMSWAP0 Combine Channel 0 and 1 Swap 1 1 read-write COMSWAP0_0 Even channel is used for input capture and 1st compare. 0 COMSWAP0_1 Odd channel is used for input capture and 1st compare. 0x1 CONF Configuration 0x84 32 read-write n 0x0 0x0 CPOT Counter Pause On Trigger 19 1 read-write CROT Counter Reload On Trigger 18 1 read-write CROT_0 Counter is not reloaded due to a rising edge on the selected input trigger 0 CROT_1 Counter is reloaded when a rising edge is detected on the selected input trigger 0x1 CSOO Counter Stop On Overflow 17 1 read-write CSOO_0 no description available 0 CSOO_1 no description available 0x1 CSOT Counter Start on Trigger 16 1 read-write CSOT_0 no description available 0 CSOT_1 no description available 0x1 DBGMODE Debug Mode 6 2 read-write DBGMODE_0 no description available 0 DBGMODE_3 no description available 0x3 DOZEEN Doze Enable 5 1 read-write DOZEEN_0 no description available 0 DOZEEN_1 no description available 0x1 GTBEEN Global time base enable 9 1 read-write GTBEEN_0 no description available 0 GTBEEN_1 All channels use an externally generated global timebase as their timebase 0x1 GTBSYNC Global Time Base Synchronization 8 1 read-write GTBSYNC_0 Global timebase synchronization disabled. 0 GTBSYNC_1 Global timebase synchronization enabled. 0x1 TRGPOL Trigger Polarity 22 1 read-write TRGPOL_0 Trigger is active high. 0 TRGPOL_1 Trigger is active low. 0x1 TRGSEL Trigger Select 24 2 read-write TRGSEL_1 Channel 0 pin input capture 0x1 TRGSEL_2 Channel 1 pin input capture 0x2 TRGSEL_3 Channel 0 or Channel 1 pin input capture 0x3 TRGSRC Trigger Source 23 1 read-write TRGSRC_0 Trigger source selected by TRGSEL is external. 0 TRGSRC_1 Trigger source selected by TRGSEL is internal (channel pin input capture). 0x1 CSC Channel (n) Status and Control 0x0 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-write oneToClear CHF_0 No channel event has occurred. 0 CHF_1 A channel event has occurred. 0x1 CHIE Channel Interrupt Enable 6 1 read-write CHIE_0 Disable channel interrupts. 0 CHIE_1 Enable channel interrupts. 0x1 DMA DMA Enable 0 1 read-write DMA_0 Disable DMA transfers. 0 DMA_1 Enable DMA transfers. 0x1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write CV Channel (n) Value 0x4 32 read-write n 0x0 0x0 VAL Channel Value 0 16 read-write FILTER Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Filter Value 0 4 read-write CH1FVAL Channel 1 Filter Value 4 4 read-write GLOBAL TPM Global Register 0x8 32 read-write n 0x0 0x0 NOUPDATE No Update 0 1 read-write NOUPDATE_0 Internal double buffered registers update as normal. 0 NOUPDATE_1 Internal double buffered registers do not update. 0x1 RST Software Reset 1 1 read-write RST_0 Module is not reset. 0 RST_1 Module is reset. 0x1 MOD Modulo 0x18 32 read-write n 0x0 0x0 MOD Modulo value 0 16 read-write PARAM Parameter Register 0x4 32 read-only n 0x0 0x0 CHAN Channel Count 0 8 read-only TRIG Trigger Count 8 8 read-only WIDTH Counter Width 16 8 read-only POL Channel Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write POL0_0 The channel polarity is active high. 0 POL0_1 The channel polarity is active low. 0x1 POL1 Channel 1 Polarity 1 1 read-write POL1_0 The channel polarity is active high. 0 POL1_1 The channel polarity is active low. 0x1 QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write n 0x0 0x0 QUADEN QUADEN 0 1 read-write QUADEN_0 Quadrature decoder mode is disabled. 0 QUADEN_1 Quadrature decoder mode is enabled. 0x1 QUADIR Counter Direction in Quadrature Decode Mode 2 1 read-only QUADIR_0 Counter direction is decreasing (counter decrement). 0 QUADIR_1 Counter direction is increasing (counter increment). 0x1 QUADMODE Quadrature Decoder Mode 3 1 read-write QUADMODE_0 Phase encoding mode. 0 QUADMODE_1 Count and direction encoding mode. 0x1 TOFDIR TOFDIR 1 1 read-only TOFDIR_0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register). 0 TOFDIR_1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero). 0x1 SC Status and Control 0x10 32 read-write n 0x0 0x0 CMOD Clock Mode Selection 3 2 read-write CMOD_0 TPM counter is disabled 0 CMOD_1 TPM counter increments on every TPM counter clock 0x1 CMOD_2 TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock 0x2 CMOD_3 no description available 0x3 CPWMS Center-Aligned PWM Select 5 1 read-write CPWMS_0 no description available 0 CPWMS_1 no description available 0x1 DMA DMA Enable 8 1 read-write DMA_0 Disables DMA transfers. 0 DMA_1 Enables DMA transfers. 0x1 PS Prescale Factor Selection 0 3 read-write PS_0 Divide by 1 0 PS_1 Divide by 2 0x1 PS_2 Divide by 4 0x2 PS_3 Divide by 8 0x3 PS_4 Divide by 16 0x4 PS_5 Divide by 32 0x5 PS_6 Divide by 64 0x6 PS_7 Divide by 128 0x7 TOF Timer Overflow Flag 7 1 read-write oneToClear TOF_0 no description available 0 TOF_1 no description available 0x1 TOIE Timer Overflow Interrupt Enable 6 1 read-write TOIE_0 no description available 0 TOIE_1 Enable TOF interrupts. An interrupt is generated when TOF equals one. 0x1 STATUS Capture and Compare Status 0x1C 32 read-write n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-write oneToClear CH0F_0 No channel event has occurred. 0 CH0F_1 A channel event has occurred. 0x1 CH1F Channel 1 Flag 1 1 read-write oneToClear CH1F_0 No channel event has occurred. 0 CH1F_1 A channel event has occurred. 0x1 TOF Timer Overflow Flag 8 1 read-write oneToClear TOF_0 no description available 0 TOF_1 no description available 0x1 TRIG Channel Trigger 0x6C 32 read-write n 0x0 0x0 TRIG0 Channel 0 Trigger 0 1 read-write TRIG0_0 No effect. 0 TRIG0_1 Configures trigger input 0 to be used by channel 0. 0x1 TRIG1 Channel 1 Trigger 1 1 read-write TRIG1_0 No effect. 0 TRIG1_1 Configures trigger input 1 to be used by channel 1. 0x1 VERID Version ID Register 0x0 32 read-only n 0x0 0x0 FEATURE Feature Identification Number 0 16 read-only FEATURE_1 Standard feature set. 0x1 FEATURE_3 Standard feature set with Filter and Combine registers implemented. 0x3 FEATURE_7 Standard feature set with Filter, Combine and Quadrature registers implemented. 0x7 MAJOR Major Version Number 24 8 read-only MINOR Minor Version Number 16 8 read-only TRGMUX0 TRGMUX TRGMUX0 0x0 0x0 0x64 registers n ADC0 TRGMUX ADC0 Register 0x3C 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write DAC0 TRGMUX DAC0 Register 0x44 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write DMAMUX0 TRGMUX DMAMUX0 Register 0x0 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write DMAMUX1 TRGMUX DMAMUX1 Register 0x48 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write FLEXIO0 TRGMUX FLEXIO0 Register 0x14 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LPCMP0 TRGMUX LPCMP0 Register 0x40 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPCMP1 TRGMUX LPCMP1 Register 0x60 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPI2C0 TRGMUX LPI2C0 Register 0x18 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPI2C1 TRGMUX LPI2C1 Register 0x1C 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPI2C2 TRGMUX LPI2C2 Register 0x20 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPI2C3 TRGMUX LPI2C3 Register 0x54 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPIT0 TRGMUX LPIT0 Register 0x4 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LPIT1 TRGMUX LPIT1 Register 0x4C 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LPSPI0 TRGMUX LPSPI0 Register 0x24 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPSPI1 TRGMUX LPSPI1 Register 0x28 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPSPI2 TRGMUX LPSPI2 Register 0x2C 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPSPI3 TRGMUX LPSPI3 Register 0x58 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPUART0 TRGMUX LPUART0 Register 0x30 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPUART1 TRGMUX LPUART1 Register 0x34 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPUART2 TRGMUX LPUART2 Register 0x38 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPUART3 TRGMUX LPUART3 Register 0x5C 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write TPM0 TRGMUX TPM0 Register 0x8 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write TPM1 TRGMUX TPM1 Register 0xC 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write TPM2 TRGMUX TPM2 Register 0x10 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write TPM3 TRGMUX TPM3 Register 0x50 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write TRGMUX1 TRGMUX TRGMUX1 0x0 0x0 0x64 registers n ADC0 TRGMUX ADC0 Register 0x58 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write DMAMUX0 TRGMUX DMAMUX0 Register 0x1C 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write DMAMUX1 TRGMUX DMAMUX1 Register 0x0 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write FLEXIO0 TRGMUX FLEXIO0 Register 0x30 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LPCMP0 TRGMUX LPCMP0 Register 0x5C 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPCMP1 TRGMUX LPCMP1 Register 0x18 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPDAC0 TRGMUX LPDAC0 Register 0x60 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPI2C0 TRGMUX LPI2C0 Register 0x34 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPI2C1 TRGMUX LPI2C1 Register 0x38 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPI2C2 TRGMUX LPI2C2 Register 0x3C 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPI2C3 TRGMUX LPI2C3 Register 0xC 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPIT0 TRGMUX LPIT0 Register 0x20 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LPIT1 TRGMUX LPIT1 Register 0x4 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write SEL3 Trigger MUX Input 3 Source Select 24 6 read-write LPSPI0 TRGMUX LPSPI0 Register 0x40 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPSPI1 TRGMUX LPSPI1 Register 0x44 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPSPI2 TRGMUX LPSPI2 Register 0x48 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPSPI3 TRGMUX LPSPI3 Register 0x10 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPUART0 TRGMUX LPUART0 Register 0x4C 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPUART1 TRGMUX LPUART1 Register 0x50 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPUART2 TRGMUX LPUART2 Register 0x54 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write LPUART3 TRGMUX LPUART3 Register 0x14 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write TPM0 TRGMUX TPM0 Register 0x24 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write TPM1 TRGMUX TPM1 Register 0x28 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write TPM2 TRGMUX TPM2 Register 0x2C 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write TPM3 TRGMUX TPM3 Register 0x8 32 read-write n 0x0 0x0 LK TRGMUX register lock. 31 1 read-write UNLOCKED Register can be written. 0 LOCKED Register cannot be written until the next system Reset. 0x1 SEL0 Trigger MUX Input 0 Source Select 0 6 read-write SEL1 Trigger MUX Input 1 Source Select 8 6 read-write SEL2 Trigger MUX Input 2 Source Select 16 6 read-write TRNG TRNG TRNG 0x0 0x0 0xF8 registers n TRNG 57 ENT0 Entropy Read Register 0x40 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT1 Entropy Read Register 0x44 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT10 Entropy Read Register 0x68 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT11 Entropy Read Register 0x6C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT12 Entropy Read Register 0x70 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT13 Entropy Read Register 0x74 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT14 Entropy Read Register 0x78 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT15 Entropy Read Register 0x7C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT2 Entropy Read Register 0x48 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT3 Entropy Read Register 0x4C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT4 Entropy Read Register 0x50 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT5 Entropy Read Register 0x54 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT6 Entropy Read Register 0x58 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT7 Entropy Read Register 0x5C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT8 Entropy Read Register 0x60 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT9 Entropy Read Register 0x64 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT[0] Entropy Read Register 0x80 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT[10] Entropy Read Register 0x3DC 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT[11] Entropy Read Register 0x448 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT[12] Entropy Read Register 0x4B8 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT[13] Entropy Read Register 0x52C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT[14] Entropy Read Register 0x5A4 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT[15] Entropy Read Register 0x620 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT[1] Entropy Read Register 0xC4 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT[2] Entropy Read Register 0x10C 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT[3] Entropy Read Register 0x158 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT[4] Entropy Read Register 0x1A8 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT[5] Entropy Read Register 0x1FC 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT[6] Entropy Read Register 0x254 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT[7] Entropy Read Register 0x2B0 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT[8] Entropy Read Register 0x310 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only ENT[9] Entropy Read Register 0x374 32 read-only n 0x0 0x0 ENT Entropy Value 0 32 read-only FRQCNT Frequency Count Register MAX_CNT 0x1C 32 read-only n 0x0 0x0 FRQ_CT Frequency Count 0 22 read-only FRQMAX Frequency Count Maximum Limit Register MAX_CNT 0x1C 32 read-write n 0x0 0x0 FRQ_MAX Frequency Counter Maximum Limit 0 22 read-write FRQMIN Frequency Count Minimum Limit Register 0x18 32 read-write n 0x0 0x0 FRQ_MIN Frequency Count Minimum Limit 0 22 read-write INT_CTRL Interrupt Control Register 0xA4 32 read-write n 0x0 0x0 ENT_VAL Same behavior as bit 0 of this register. 1 1 read-write ENT_VAL_0 Same behavior as bit 0 of this register. 0 ENT_VAL_1 Same behavior as bit 0 of this register. 0x1 FRQ_CT_FAIL Same behavior as bit 0 of this register. 2 1 read-write FRQ_CT_FAIL_0 Same behavior as bit 0 of this register. 0 FRQ_CT_FAIL_1 Same behavior as bit 0 of this register. 0x1 HW_ERR Bit position that can be cleared if corresponding bit of INT_STATUS register has been asserted. 0 1 read-write HW_ERR_0 Corresponding bit of INT_STATUS register cleared. 0 HW_ERR_1 Corresponding bit of INT_STATUS register active. 0x1 UNUSED Reserved but writeable. 3 29 read-write INT_MASK Mask Register 0xA8 32 read-write n 0x0 0x0 ENT_VAL Same behavior as bit 0 of this register. 1 1 read-write ENT_VAL_0 Same behavior as bit 0 of this register. 0 ENT_VAL_1 Same behavior as bit 0 of this register. 0x1 FRQ_CT_FAIL Same behavior as bit 0 of this register. 2 1 read-write FRQ_CT_FAIL_0 Same behavior as bit 0 of this register. 0 FRQ_CT_FAIL_1 Same behavior as bit 0 of this register. 0x1 HW_ERR Bit position that can be cleared if corresponding bit of INT_STATUS has been asserted. 0 1 read-write HW_ERR_0 Corresponding interrupt of INT_STATUS is masked. 0 HW_ERR_1 Corresponding bit of INT_STATUS is active. 0x1 INT_STATUS Interrupt Status Register 0xAC 32 read-only n 0x0 0x0 ENT_VAL Read only: Entropy Valid 1 1 read-only ENT_VAL_0 Busy generation entropy. Any value read is invalid. 0 ENT_VAL_1 TRNG can be stopped and entropy is valid if read. 0x1 FRQ_CT_FAIL Read only: Frequency Count Fail 2 1 read-only FRQ_CT_FAIL_0 No hardware nor self test frequency errors. 0 FRQ_CT_FAIL_1 The frequency counter has detected a failure. 0x1 HW_ERR Read: Error status 0 1 read-only HW_ERR_0 no error 0 HW_ERR_1 error detected. 0x1 MCTL Miscellaneous Control Register 0x0 32 read-write n 0x0 0x0 ENT_VAL Read only: Entropy Valid 10 1 read-only ERR Read: Error status 12 1 read-write oneToClear FCT_FAIL Read only: Frequency Count Fail 8 1 read-only FCT_VAL Read only: Frequency Count Valid. Indicates that a valid frequency count may be read from FRQCNT. 9 1 read-only FOR_SCLK Force System Clock 7 1 read-write OSC_DIV Oscillator Divide 2 2 read-write OSC_DIV_0 use ring oscillator with no divide 0 OSC_DIV_1 use ring oscillator divided-by-2 0x1 OSC_DIV_2 use ring oscillator divided-by-4 0x2 OSC_DIV_3 use ring oscillator divided-by-8 0x3 PRGM Programming Mode Select 16 1 read-write RST_DEF Reset Defaults 6 1 write-only SAMP_MODE Sample Mode 0 2 read-write SAMP_MODE_0 use Von Neumann data into both Entropy shifter and Statistical Checker 0 SAMP_MODE_1 use raw data into both Entropy shifter and Statistical Checker 0x1 SAMP_MODE_2 use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker 0x2 SAMP_MODE_3 undefined/reserved. 0x3 TRNG_ACC TRNG Access Mode 5 1 read-write TSTOP_OK TRNG_OK_TO_STOP 13 1 read-only TST_OUT Read only: Test point inside ring oscillator. 11 1 read-only UNUSED4 This bit is unused. Always reads zero. 4 1 read-only PKRCNT10 Statistical Check Poker Count 1 and 0 Register 0x80 32 read-only n 0x0 0x0 PKR_0_CT Poker 0h Count 0 16 read-only PKR_1_CT Poker 1h Count 16 16 read-only PKRCNT32 Statistical Check Poker Count 3 and 2 Register 0x84 32 read-only n 0x0 0x0 PKR_2_CT Poker 2h Count 0 16 read-only PKR_3_CT Poker 3h Count 16 16 read-only PKRCNT54 Statistical Check Poker Count 5 and 4 Register 0x88 32 read-only n 0x0 0x0 PKR_4_CT Poker 4h Count 0 16 read-only PKR_5_CT Poker 5h Count 16 16 read-only PKRCNT76 Statistical Check Poker Count 7 and 6 Register 0x8C 32 read-only n 0x0 0x0 PKR_6_CT Poker 6h Count 0 16 read-only PKR_7_CT Poker 7h Count 16 16 read-only PKRCNT98 Statistical Check Poker Count 9 and 8 Register 0x90 32 read-only n 0x0 0x0 PKR_8_CT Poker 8h Count 0 16 read-only PKR_9_CT Poker 9h Count 16 16 read-only PKRCNTBA Statistical Check Poker Count B and A Register 0x94 32 read-only n 0x0 0x0 PKR_A_CT Poker Ah Count 0 16 read-only PKR_B_CT Poker Bh Count 16 16 read-only PKRCNTDC Statistical Check Poker Count D and C Register 0x98 32 read-only n 0x0 0x0 PKR_C_CT Poker Ch Count 0 16 read-only PKR_D_CT Poker Dh Count 16 16 read-only PKRCNTFE Statistical Check Poker Count F and E Register 0x9C 32 read-only n 0x0 0x0 PKR_E_CT Poker Eh Count 0 16 read-only PKR_F_CT Poker Fh Count 16 16 read-only PKRMAX Poker Maximum Limit Register MAX_SQ 0xC 32 read-write n 0x0 0x0 PKR_MAX Poker Maximum Limit. 0 24 read-write PKRRNG Poker Range Register 0x8 32 read-write n 0x0 0x0 PKR_RNG Poker Range 0 16 read-write PKRSQ Poker Square Calculation Result Register MAX_SQ 0xC 32 read-only n 0x0 0x0 PKR_SQ Poker Square Calculation Result. 0 24 read-only SBLIM Sparse Bit Limit Register SBLIM_TOTSAM 0x14 32 read-write n 0x0 0x0 SB_LIM Sparse Bit Limit 0 10 read-write SCMC Statistical Check Monobit Count Register SCML_MC 0x20 32 read-only n 0x0 0x0 MONO_CT Monobit Count 0 16 read-only SCMISC Statistical Check Miscellaneous Register 0x4 32 read-write n 0x0 0x0 LRUN_MAX LONG RUN MAX LIMIT 0 8 read-write RTY_CT RETRY COUNT 16 4 read-write SCML Statistical Check Monobit Limit Register SCML_MC 0x20 32 read-write n 0x0 0x0 MONO_MAX Monobit Maximum Limit 0 16 read-write MONO_RNG Monobit Range 16 16 read-write SCR1C Statistical Check Run Length 1 Count Register SCR1L_1C 0x24 32 read-only n 0x0 0x0 R1_0_CT Runs of Zero, Length 1 Count 0 15 read-only R1_1_CT Runs of One, Length 1 Count 16 15 read-only SCR1L Statistical Check Run Length 1 Limit Register SCR1L_1C 0x24 32 read-write n 0x0 0x0 RUN1_MAX Run Length 1 Maximum Limit 0 15 read-write RUN1_RNG Run Length 1 Range 16 15 read-write SCR2C Statistical Check Run Length 2 Count Register SCR2L_2C 0x28 32 read-only n 0x0 0x0 R2_0_CT Runs of Zero, Length 2 Count 0 14 read-only R2_1_CT Runs of One, Length 2 Count 16 14 read-only SCR2L Statistical Check Run Length 2 Limit Register SCR2L_2C 0x28 32 read-write n 0x0 0x0 RUN2_MAX Run Length 2 Maximum Limit 0 14 read-write RUN2_RNG Run Length 2 Range 16 14 read-write SCR3C Statistical Check Run Length 3 Count Register SCR3L_3C 0x2C 32 read-only n 0x0 0x0 R3_0_CT Runs of Zeroes, Length 3 Count 0 13 read-only R3_1_CT Runs of Ones, Length 3 Count 16 13 read-only SCR3L Statistical Check Run Length 3 Limit Register SCR3L_3C 0x2C 32 read-write n 0x0 0x0 RUN3_MAX Run Length 3 Maximum Limit 0 13 read-write RUN3_RNG Run Length 3 Range 16 13 read-write SCR4C Statistical Check Run Length 4 Count Register SCR4L_4C 0x30 32 read-only n 0x0 0x0 R4_0_CT Runs of Zero, Length 4 Count 0 12 read-only R4_1_CT Runs of One, Length 4 Count 16 12 read-only SCR4L Statistical Check Run Length 4 Limit Register SCR4L_4C 0x30 32 read-write n 0x0 0x0 RUN4_MAX Run Length 4 Maximum Limit 0 12 read-write RUN4_RNG Run Length 4 Range 16 12 read-write SCR5C Statistical Check Run Length 5 Count Register SCR5L_5C 0x34 32 read-only n 0x0 0x0 R5_0_CT Runs of Zero, Length 5 Count 0 11 read-only R5_1_CT Runs of One, Length 5 Count 16 11 read-only SCR5L Statistical Check Run Length 5 Limit Register SCR5L_5C 0x34 32 read-write n 0x0 0x0 RUN5_MAX Run Length 5 Maximum Limit 0 11 read-write RUN5_RNG Run Length 5 Range 16 11 read-write SCR6PC Statistical Check Run Length 6+ Count Register SCR6PL_PC 0x38 32 read-only n 0x0 0x0 R6P_0_CT Runs of Zero, Length 6+ Count 0 11 read-only R6P_1_CT Runs of One, Length 6+ Count 16 11 read-only SCR6PL Statistical Check Run Length 6+ Limit Register SCR6PL_PC 0x38 32 read-write n 0x0 0x0 RUN6P_MAX Run Length 6+ Maximum Limit 0 11 read-write RUN6P_RNG Run Length 6+ Range 16 11 read-write SDCTL Seed Control Register 0x10 32 read-write n 0x0 0x0 ENT_DLY Entropy Delay 16 16 read-write SAMP_SIZE Sample Size 0 16 read-write SEC_CFG Security Configuration Register 0xA0 32 read-write n 0x0 0x0 NO_PRGM If set, the TRNG registers cannot be programmed 1 1 read-write NO_PRGM_0 Programability of registers controlled only by the Miscellaneous Control Register's access mode bit. 0 NO_PRGM_1 Overides Miscellaneous Control Register access mode and prevents TRNG register programming. 0x1 UNUSED0 This bit is unused. Ignore. 0 1 read-write UNUSED2 This bit is unused. Ignore. 2 1 read-write STATUS Status Register 0x3C 32 read-only n 0x0 0x0 RETRY_CT RETRY COUNT 16 4 read-only TF1BR0 Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s Test has failed. 0 1 read-only TF1BR1 Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s Test has failed. 1 1 read-only TF2BR0 Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s Test has failed. 2 1 read-only TF2BR1 Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s Test has failed. 3 1 read-only TF3BR0 Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s Test has failed. 4 1 read-only TF3BR1 Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s Test has failed. 5 1 read-only TF4BR0 Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s Test has failed. 6 1 read-only TF4BR1 Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s Test has failed. 7 1 read-only TF5BR0 Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s Test has failed. 8 1 read-only TF5BR1 Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s Test has failed. 9 1 read-only TF6PBR0 Test Fail, 6 Plus Bit Run, Sampling 0s 10 1 read-only TF6PBR1 Test Fail, 6 Plus Bit Run, Sampling 1s 11 1 read-only TFLR Test Fail, Long Run. If TFLR=1, the Long Run Test has failed. 13 1 read-only TFMB Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed. 15 1 read-only TFP Test Fail, Poker. If TFP=1, the Poker Test has failed. 14 1 read-only TFSB Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed. 12 1 read-only TOTSAM Total Samples Register SBLIM_TOTSAM 0x14 32 read-only n 0x0 0x0 TOT_SAM Total Samples 0 20 read-only VID1 Version ID Register (MS) 0xF0 32 read-only n 0x0 0x0 IP_ID Shows the IP ID. 16 16 read-only IP_ID_48 ID for TRNG. 0x30 MAJ_REV Shows the IP's Major revision of the TRNG. 8 8 read-only MAJ_REV_1 Major revision number for TRNG. 0x1 MIN_REV Shows the IP's Minor revision of the TRNG. 0 8 read-only MIN_REV_0 Minor revision number for TRNG. 0 VID2 Version ID Register (LS) 0xF4 32 read-only n 0x0 0x0 CONFIG_OPT Shows the IP's Configuaration options for the TRNG. 0 8 read-only CONFIG_OPT_0 TRNG_CONFIG_OPT for TRNG. 0 ECO_REV Shows the IP's ECO revision of the TRNG. 8 8 read-only ECO_REV_0 TRNG_ECO_REV for TRNG. 0 ERA Shows the compile options for the TRNG. 24 8 read-only ERA_0 COMPILE_OPT for TRNG. 0 INTG_OPT Shows the integration options for the TRNG. 16 8 read-only INTG_OPT_0 INTG_OPT for TRNG. 0 TSTMRA TSTMRA TSTMR 0x0 0x0 0x8 registers n HIGH Time Stamp Timer Register High 0x4 32 read-only n 0x0 0x0 VALUE Time Stamp Timer High 0 24 read-only LOW Time Stamp Timer Register Low 0x0 32 read-only n 0x0 0x0 VALUE Time Stamp Timer Low 0 32 read-only USB0 USB USB 0x0 0x0 0x15D registers n USB0 47 ADDINFO Peripheral Additional Info register 0xC 8 read-only n 0x0 0x0 IEHOST Host mode enable bit 0 1 read-only ADDR Address register 0x98 8 read-write n 0x0 0x0 ADDR USB Address 0 7 read-write BDTPAGE1 BDT Page register 1 0x9C 8 read-write n 0x0 0x0 BDTBA BDTBA 1 7 read-write BDTPAGE2 BDT Page Register 2 0xB0 8 read-write n 0x0 0x0 BDTBA BDTBA 0 8 read-write BDTPAGE3 BDT Page Register 3 0xB4 8 read-write n 0x0 0x0 BDTBA BDTBA 0 8 read-write CLK_RECOVER_CTRL USB Clock recovery control 0x140 8 read-write n 0x0 0x0 CLOCK_RECOVER_EN Crystal-less USB enable 7 1 read-write CLOCK_RECOVER_EN_0 Disable clock recovery block (default) 0 CLOCK_RECOVER_EN_1 Enable clock recovery block 0x1 RESET_RESUME_ROUGH_EN Reset/resume to rough phase enable 6 1 read-write RESET_RESUME_ROUGH_EN_0 Always works in tracking phase after the first time rough phase, to track transition (default). 0 RESET_RESUME_ROUGH_EN_1 Go back to rough stage whenever a bus reset or bus resume occurs. 0x1 RESTART_IFRTRIM_EN Restart from IFR trim value 5 1 read-write RESTART_IFRTRIM_EN_0 Trim fine adjustment always works based on the previous updated trim fine value (default). 0 RESTART_IFRTRIM_EN_1 Trim fine restarts from the IFR trim value, whenever bus_reset/bus_resume is detected or module enable is desasserted. 0x1 CLK_RECOVER_INT_EN Clock recovery combined interrupt enable 0x154 8 read-write n 0x0 0x0 OVF_ERROR_EN OVF_ERROR_EN 4 1 read-write OVF_ERROR_EN_0 The interrupt will be masked 0 OVF_ERROR_EN_1 The interrupt will be enabled (default) 0x1 CLK_RECOVER_INT_STATUS Clock recovery separated interrupt status 0x15C 8 read-write n 0x0 0x0 OVF_ERROR OVF_ERROR 4 1 read-write oneToClear OVF_ERROR_0 No interrupt is reported 0 OVF_ERROR_1 Unmasked interrupt has been generated 0x1 CLK_RECOVER_IRC_EN IRC48MFIRC oscillator enable register 0x144 8 read-write n 0x0 0x0 IRC_EN IRC_EN 1 1 read-write IRC_EN_0 no description available 0 IRC_EN_1 no description available 0x1 REG_EN Regulator enable 0 1 read-write REG_EN_0 no description available 0 REG_EN_1 no description available 0x1 CONTROL USB OTG Control register 0x108 8 read-write n 0x0 0x0 DPPULLUPNONOTG DPPULLUPNONOTG 4 1 read-write DPPULLUPNONOTG_0 DP Pullup in non-OTG Device mode is not enabled. 0 DPPULLUPNONOTG_1 DP Pullup in non-OTG Device mode is enabled. 0x1 CTL Control register 0x94 8 read-write n 0x0 0x0 HOSTMODEEN Host mode enable 3 1 read-write HOSTMODEEN_0 USB Module operates in Device mode. 0 HOSTMODEEN_1 USB Module operates in Host mode. In Host mode, the USB module performs USB transactions under the programmed control of the host processor. 0x1 JSTATE Live USB differential receiver JSTATE signal 7 1 read-write ODDRST ODDRST 1 1 read-write RESUME Resume 2 1 read-write SE0 Live USB Single-Ended Zero signal 6 1 read-write TXSUSPENDTOKENBUSY TXSUSPEND or TOKENBUSY 5 1 read-write USBENSOFEN USB Enable 0 1 read-write USBENSOFEN_0 Disables the USB Module. 0 USBENSOFEN_1 Enables the USB Module. 0x1 ENDPOINT[0]-ENDPT Endpoint Control register 0xC0 8 read-write n 0x0 0x0 EPCTLDIS Control (SETUP) transfer disable 4 1 read-write EPHSHK Endpoint handshaking enable 0 1 read-write EPRXEN Endpoint for RX transfers enable 3 1 read-write EPSTALL Endpoint stalled 1 1 read-write EPTXEN Endpoint for TX transfers enable 2 1 read-write ENDPOINT[10]-ENDPOINT[9]-ENDPOINT[8]-ENDPOINT[7]-ENDPOINT[6]-ENDPOINT[5]-ENDPOINT[4]-ENDPOINT[3]-ENDPOINT[2]-ENDPOINT[1]-ENDPOINT[0]-ENDPT Endpoint Control register 0x91C 8 read-write n 0x0 0x0 EPCTLDIS Control (SETUP) transfer disable 4 1 read-write EPHSHK Endpoint handshaking enable 0 1 read-write EPRXEN Endpoint for RX transfers enable 3 1 read-write EPSTALL Endpoint stalled 1 1 read-write EPTXEN Endpoint for TX transfers enable 2 1 read-write ENDPOINT[11]-ENDPOINT[10]-ENDPOINT[9]-ENDPOINT[8]-ENDPOINT[7]-ENDPOINT[6]-ENDPOINT[5]-ENDPOINT[4]-ENDPOINT[3]-ENDPOINT[2]-ENDPOINT[1]-ENDPOINT[0]-ENDPT Endpoint Control register 0xA08 8 read-write n 0x0 0x0 EPCTLDIS Control (SETUP) transfer disable 4 1 read-write EPHSHK Endpoint handshaking enable 0 1 read-write EPRXEN Endpoint for RX transfers enable 3 1 read-write EPSTALL Endpoint stalled 1 1 read-write EPTXEN Endpoint for TX transfers enable 2 1 read-write ENDPOINT[12]-ENDPOINT[11]-ENDPOINT[10]-ENDPOINT[9]-ENDPOINT[8]-ENDPOINT[7]-ENDPOINT[6]-ENDPOINT[5]-ENDPOINT[4]-ENDPOINT[3]-ENDPOINT[2]-ENDPOINT[1]-ENDPOINT[0]-ENDPT Endpoint Control register 0xAF8 8 read-write n 0x0 0x0 EPCTLDIS Control (SETUP) transfer disable 4 1 read-write EPHSHK Endpoint handshaking enable 0 1 read-write EPRXEN Endpoint for RX transfers enable 3 1 read-write EPSTALL Endpoint stalled 1 1 read-write EPTXEN Endpoint for TX transfers enable 2 1 read-write ENDPOINT[13]-ENDPOINT[12]-ENDPOINT[11]-ENDPOINT[10]-ENDPOINT[9]-ENDPOINT[8]-ENDPOINT[7]-ENDPOINT[6]-ENDPOINT[5]-ENDPOINT[4]-ENDPOINT[3]-ENDPOINT[2]-ENDPOINT[1]-ENDPOINT[0]-ENDPT Endpoint Control register 0xBEC 8 read-write n 0x0 0x0 EPCTLDIS Control (SETUP) transfer disable 4 1 read-write EPHSHK Endpoint handshaking enable 0 1 read-write EPRXEN Endpoint for RX transfers enable 3 1 read-write EPSTALL Endpoint stalled 1 1 read-write EPTXEN Endpoint for TX transfers enable 2 1 read-write ENDPOINT[14]-ENDPOINT[13]-ENDPOINT[12]-ENDPOINT[11]-ENDPOINT[10]-ENDPOINT[9]-ENDPOINT[8]-ENDPOINT[7]-ENDPOINT[6]-ENDPOINT[5]-ENDPOINT[4]-ENDPOINT[3]-ENDPOINT[2]-ENDPOINT[1]-ENDPOINT[0]-ENDPT Endpoint Control register 0xCE4 8 read-write n 0x0 0x0 EPCTLDIS Control (SETUP) transfer disable 4 1 read-write EPHSHK Endpoint handshaking enable 0 1 read-write EPRXEN Endpoint for RX transfers enable 3 1 read-write EPSTALL Endpoint stalled 1 1 read-write EPTXEN Endpoint for TX transfers enable 2 1 read-write ENDPOINT[15]-ENDPOINT[14]-ENDPOINT[13]-ENDPOINT[12]-ENDPOINT[11]-ENDPOINT[10]-ENDPOINT[9]-ENDPOINT[8]-ENDPOINT[7]-ENDPOINT[6]-ENDPOINT[5]-ENDPOINT[4]-ENDPOINT[3]-ENDPOINT[2]-ENDPOINT[1]-ENDPOINT[0]-ENDPT Endpoint Control register 0xDE0 8 read-write n 0x0 0x0 EPCTLDIS Control (SETUP) transfer disable 4 1 read-write EPHSHK Endpoint handshaking enable 0 1 read-write EPRXEN Endpoint for RX transfers enable 3 1 read-write EPSTALL Endpoint stalled 1 1 read-write EPTXEN Endpoint for TX transfers enable 2 1 read-write ENDPOINT[1]-ENDPOINT[0]-ENDPT Endpoint Control register 0x184 8 read-write n 0x0 0x0 EPCTLDIS Control (SETUP) transfer disable 4 1 read-write EPHSHK Endpoint handshaking enable 0 1 read-write EPRXEN Endpoint for RX transfers enable 3 1 read-write EPSTALL Endpoint stalled 1 1 read-write EPTXEN Endpoint for TX transfers enable 2 1 read-write ENDPOINT[2]-ENDPOINT[1]-ENDPOINT[0]-ENDPT Endpoint Control register 0x24C 8 read-write n 0x0 0x0 EPCTLDIS Control (SETUP) transfer disable 4 1 read-write EPHSHK Endpoint handshaking enable 0 1 read-write EPRXEN Endpoint for RX transfers enable 3 1 read-write EPSTALL Endpoint stalled 1 1 read-write EPTXEN Endpoint for TX transfers enable 2 1 read-write ENDPOINT[3]-ENDPOINT[2]-ENDPOINT[1]-ENDPOINT[0]-ENDPT Endpoint Control register 0x318 8 read-write n 0x0 0x0 EPCTLDIS Control (SETUP) transfer disable 4 1 read-write EPHSHK Endpoint handshaking enable 0 1 read-write EPRXEN Endpoint for RX transfers enable 3 1 read-write EPSTALL Endpoint stalled 1 1 read-write EPTXEN Endpoint for TX transfers enable 2 1 read-write ENDPOINT[4]-ENDPOINT[3]-ENDPOINT[2]-ENDPOINT[1]-ENDPOINT[0]-ENDPT Endpoint Control register 0x3E8 8 read-write n 0x0 0x0 EPCTLDIS Control (SETUP) transfer disable 4 1 read-write EPHSHK Endpoint handshaking enable 0 1 read-write EPRXEN Endpoint for RX transfers enable 3 1 read-write EPSTALL Endpoint stalled 1 1 read-write EPTXEN Endpoint for TX transfers enable 2 1 read-write ENDPOINT[5]-ENDPOINT[4]-ENDPOINT[3]-ENDPOINT[2]-ENDPOINT[1]-ENDPOINT[0]-ENDPT Endpoint Control register 0x4BC 8 read-write n 0x0 0x0 EPCTLDIS Control (SETUP) transfer disable 4 1 read-write EPHSHK Endpoint handshaking enable 0 1 read-write EPRXEN Endpoint for RX transfers enable 3 1 read-write EPSTALL Endpoint stalled 1 1 read-write EPTXEN Endpoint for TX transfers enable 2 1 read-write ENDPOINT[6]-ENDPOINT[5]-ENDPOINT[4]-ENDPOINT[3]-ENDPOINT[2]-ENDPOINT[1]-ENDPOINT[0]-ENDPT Endpoint Control register 0x594 8 read-write n 0x0 0x0 EPCTLDIS Control (SETUP) transfer disable 4 1 read-write EPHSHK Endpoint handshaking enable 0 1 read-write EPRXEN Endpoint for RX transfers enable 3 1 read-write EPSTALL Endpoint stalled 1 1 read-write EPTXEN Endpoint for TX transfers enable 2 1 read-write ENDPOINT[7]-ENDPOINT[6]-ENDPOINT[5]-ENDPOINT[4]-ENDPOINT[3]-ENDPOINT[2]-ENDPOINT[1]-ENDPOINT[0]-ENDPT Endpoint Control register 0x670 8 read-write n 0x0 0x0 EPCTLDIS Control (SETUP) transfer disable 4 1 read-write EPHSHK Endpoint handshaking enable 0 1 read-write EPRXEN Endpoint for RX transfers enable 3 1 read-write EPSTALL Endpoint stalled 1 1 read-write EPTXEN Endpoint for TX transfers enable 2 1 read-write ENDPOINT[8]-ENDPOINT[7]-ENDPOINT[6]-ENDPOINT[5]-ENDPOINT[4]-ENDPOINT[3]-ENDPOINT[2]-ENDPOINT[1]-ENDPOINT[0]-ENDPT Endpoint Control register 0x750 8 read-write n 0x0 0x0 EPCTLDIS Control (SETUP) transfer disable 4 1 read-write EPHSHK Endpoint handshaking enable 0 1 read-write EPRXEN Endpoint for RX transfers enable 3 1 read-write EPSTALL Endpoint stalled 1 1 read-write EPTXEN Endpoint for TX transfers enable 2 1 read-write ENDPOINT[9]-ENDPOINT[8]-ENDPOINT[7]-ENDPOINT[6]-ENDPOINT[5]-ENDPOINT[4]-ENDPOINT[3]-ENDPOINT[2]-ENDPOINT[1]-ENDPOINT[0]-ENDPT Endpoint Control register 0x834 8 read-write n 0x0 0x0 EPCTLDIS Control (SETUP) transfer disable 4 1 read-write EPHSHK Endpoint handshaking enable 0 1 read-write EPRXEN Endpoint for RX transfers enable 3 1 read-write EPSTALL Endpoint stalled 1 1 read-write EPTXEN Endpoint for TX transfers enable 2 1 read-write ENDPT Endpoint Control register 0x0 8 read-write n 0x0 0x0 EPCTLDIS Control (SETUP) transfer disable 4 1 read-write EPHSHK Endpoint handshaking enable 0 1 read-write EPRXEN Endpoint for RX transfers enable 3 1 read-write EPSTALL Endpoint stalled 1 1 read-write EPTXEN Endpoint for TX transfers enable 2 1 read-write ERREN Error Interrupt Enable register 0x8C 8 read-write n 0x0 0x0 BTOERREN BTOERR Interrupt Enable 4 1 read-write BTOERREN_0 Disables the BTOERR interrupt. 0 BTOERREN_1 Enables the BTOERR interrupt. 0x1 BTSERREN BTSERR Interrupt Enable 7 1 read-write BTSERREN_0 Disables the BTSERR interrupt. 0 BTSERREN_1 Enables the BTSERR interrupt. 0x1 CRC16EN CRC16 Interrupt Enable 2 1 read-write CRC16EN_0 Disables the CRC16 interrupt. 0 CRC16EN_1 Enables the CRC16 interrupt. 0x1 CRC5EOFEN CRC5/EOF Interrupt Enable 1 1 read-write CRC5EOFEN_0 Disables the CRC5/EOF interrupt. 0 CRC5EOFEN_1 Enables the CRC5/EOF interrupt. 0x1 DFN8EN DFN8 Interrupt Enable 3 1 read-write DFN8EN_0 Disables the DFN8 interrupt. 0 DFN8EN_1 Enables the DFN8 interrupt. 0x1 DMAERREN DMAERR Interrupt Enable 5 1 read-write DMAERREN_0 Disables the DMAERR interrupt. 0 DMAERREN_1 Enables the DMAERR interrupt. 0x1 OWNERREN OWNERR Interrupt Enable 6 1 read-write OWNERREN_0 Disables the OWNERR interrupt. 0 OWNERREN_1 Enables the OWNERR interrupt. 0x1 PIDERREN PIDERR Interrupt Enable 0 1 read-write PIDERREN_0 Disables the PIDERR interrupt. 0 PIDERREN_1 Enters the PIDERR interrupt. 0x1 ERRSTAT Error Interrupt Status register 0x88 8 read-write n 0x0 0x0 BTOERR Bus turnaround timeout error 4 1 read-write oneToClear BTSERR Bit stuff error 7 1 read-write oneToClear CRC16 CRC16 error 2 1 read-write oneToClear CRC5EOF CRC5 error or end of frame error 1 1 read-write oneToClear DFN8 Data field not 8 bits (in length) 3 1 read-write oneToClear DMAERR DMAERR 5 1 read-write oneToClear OWNERR OWNERR 6 1 read-write oneToClear PIDERR PID error 0 1 read-write oneToClear FRMNUMH Frame Number register High 0xA4 8 read-write n 0x0 0x0 FRM FRM 0 3 read-write FRMNUML Frame Number register Low 0xA0 8 read-write n 0x0 0x0 FRM FRM 0 8 read-write IDCOMP Peripheral ID Complement register 0x4 8 read-only n 0x0 0x0 NID NID 0 6 read-only INTEN Interrupt Enable register 0x84 8 read-write n 0x0 0x0 ERROREN ERROR Interrupt Enable 1 1 read-write ERROREN_0 Disables the ERROR interrupt. 0 ERROREN_1 Enables the ERROR interrupt. 0x1 RESUMEEN RESUME Interrupt Enable 5 1 read-write RESUMEEN_0 Disables the RESUME interrupt. 0 RESUMEEN_1 Enables the RESUME interrupt. 0x1 SLEEPEN SLEEP Interrupt Enable 4 1 read-write SLEEPEN_0 Disables the SLEEP interrupt. 0 SLEEPEN_1 Enables the SLEEP interrupt. 0x1 SOFTOKEN SOFTOK Interrupt Enable 2 1 read-write SOFTOKEN_0 Disbles the SOFTOK interrupt. 0 SOFTOKEN_1 Enables the SOFTOK interrupt. 0x1 STALLEN STALL Interrupt Enable 7 1 read-write STALLEN_0 Diasbles the STALL interrupt. 0 STALLEN_1 Enables the STALL interrupt. 0x1 TOKDNEEN TOKDNE Interrupt Enable 3 1 read-write TOKDNEEN_0 Disables the TOKDNE interrupt. 0 TOKDNEEN_1 Enables the TOKDNE interrupt. 0x1 USBRSTEN USBRST Interrupt Enable 0 1 read-write USBRSTEN_0 Disables the USBRST interrupt. 0 USBRSTEN_1 Enables the USBRST interrupt. 0x1 ISTAT Interrupt Status register 0x80 8 read-write n 0x0 0x0 ERROR Error 1 1 read-write oneToClear RESUME RESUME 5 1 read-write oneToClear SLEEP Sleep 4 1 read-write oneToClear SOFTOK Start Of Frame (SOF) token 2 1 read-write oneToClear STALL Stall Interrupt 7 1 read-write oneToClear TOKDNE Current token processing 3 1 read-write oneToClear USBRST USB Reset 0 1 read-write oneToClear KEEP_ALIVE_CTRL Keep Alive mode control 0x124 8 read-write n 0x0 0x0 KEEP_ALIVE_EN Keep Alive mode enable 0 1 read-write KEEP_ALIVE_STS Keep Alive Status 6 1 read-only KEEP_ALIVE_STS_0 USB is not in Keep Alive mode. 0 KEEP_ALIVE_STS_1 USB is in Keep Alive mode. 0x1 OWN_OVERRD_EN OWN bit override enable 1 1 read-write STOP_ACK_DLY_EN STOP_ACK_DLY_EN 2 1 read-write STOP_ACK_DLY_EN_0 Enter KEEP_ALIVE mode until the USB core is idle and there is no USB AHB transfer. 0 STOP_ACK_DLY_EN_1 Enter KEEP_ALIVE mode immediately when there is no USB AHB transfer. 0x1 WAKE_INT_EN Wakeup Interrupt Enable 4 1 read-write WAKE_INT_STS Wakeup Interrupt Status 7 1 read-only WAKE_REQ_EN WAKE_REQ_EN 3 1 read-write WAKE_REQ_EN_0 USB bus wakeup request is disabled 0 WAKE_REQ_EN_1 USB bus wakeup request is enabled 0x1 KEEP_ALIVE_WKCTRL Keep Alive mode wakeup control 0x128 8 read-write n 0x0 0x0 WAKE_ENDPT WAKE_ENDPT 4 4 read-only WAKE_ON_THIS WAKE_ON_THIS 0 4 read-write WAKE_ON_THIS_1 Wake up after receiving OUT/SETUP token packet. 0x1 WAKE_ON_THIS_13 no description available 0xD MISCCTRL Miscellaneous Control register 0x12C 8 read-write n 0x0 0x0 OWNERRISODIS OWN Error Detect for ISO IN / ISO OUT Disable 2 1 read-write OWNERRISODIS_0 OWN error detect for ISO IN / ISO OUT is not disabled. 0 OWNERRISODIS_1 OWN error detect for ISO IN / ISO OUT is disabled. 0x1 SOFBUSSET SOF_TOK Interrupt Generation Mode Select 1 1 read-write SOFBUSSET_0 SOF_TOK interrupt is set according to SOF threshold value. 0 SOFBUSSET_1 SOF_TOK interrupt is set when SOF counter reaches 0. 0x1 SOFDYNTHLD Dynamic SOF Threshold Compare mode 0 1 read-write SOFDYNTHLD_0 SOF_TOK interrupt is set when byte times SOF threshold is reached. 0 SOFDYNTHLD_1 SOF_TOK interrupt is set when 8 byte times SOF threshold is reached or overstepped. 0x1 STL_ADJ_EN USB Peripheral mode Stall Adjust Enable 7 1 read-write STL_ADJ_EN_0 If USB_ENDPTn[END_STALL] = 1, both IN and OUT directions for the associated endpoint will be stalled 0 STL_ADJ_EN_1 If USB_ENDPTn[END_STALL] = 1, the USB_STALL_xx_DIS registers control which directions for the associated endpoint will be stalled. 0x1 VFEDG_EN VREGIN Falling Edge Interrupt Enable 4 1 read-write VFEDG_EN_0 VREGIN falling edge interrupt disabled. 0 VFEDG_EN_1 VREGIN falling edge interrupt enabled. 0x1 VREDG_EN VREGIN Rising Edge Interrupt Enable 3 1 read-write VREDG_EN_0 VREGIN rising edge interrupt disabled. 0 VREDG_EN_1 VREGIN rising edge interrupt enabled. 0x1 OBSERVE USB OTG Observe register 0x104 8 read-only n 0x0 0x0 DMPD DMPD 4 1 read-only DMPD_0 D- pulldown is disabled. 0 DMPD_1 D- pulldown is enabled. 0x1 DPPD DPPD 6 1 read-only DPPD_0 D+ pulldown is disabled. 0 DPPD_1 D+ pulldown is enabled. 0x1 DPPU DPPU 7 1 read-only DPPU_0 D+ pullup disabled. 0 DPPU_1 D+ pullup enabled. 0x1 OTGCTL OTG Control register 0x1C 8 read-write n 0x0 0x0 DPHIGH D+ Data Line pullup resistor enable 7 1 read-write DPHIGH_0 D+ pullup resistor is not enabled 0 DPHIGH_1 D+ pullup resistor is enabled 0x1 PERID Peripheral ID register 0x0 8 read-only n 0x0 0x0 ID Peripheral Identification 0 6 read-only REV Peripheral Revision register 0x8 8 read-only n 0x0 0x0 REV Revision 0 8 read-only STALL_IH_DIS Peripheral mode stall disable for endpoints 15 to 8 in IN direction 0x134 8 read-write n 0x0 0x0 STALL_I_DIS10 STALL_I_DIS10 2 1 read-write STALL_I_DIS10_0 Endpoint 10 IN direction stall is enabled. 0 STALL_I_DIS10_1 Endpoint 10 IN direction stall is disabled. 0x1 STALL_I_DIS11 STALL_I_DIS11 3 1 read-write STALL_I_DIS11_0 Endpoint 11 IN direction stall is enabled. 0 STALL_I_DIS11_1 Endpoint 11 IN direction stall is disabled. 0x1 STALL_I_DIS12 STALL_I_DIS12 4 1 read-write STALL_I_DIS12_0 Endpoint 12 IN direction stall is enabled. 0 STALL_I_DIS12_1 Endpoint 12 IN direction stall is disabled. 0x1 STALL_I_DIS13 STALL_I_DIS13 5 1 read-write STALL_I_DIS13_0 Endpoint 13 IN direction stall is enabled. 0 STALL_I_DIS13_1 Endpoint 13 IN direction stall is disabled. 0x1 STALL_I_DIS14 STALL_I_DIS14 6 1 read-write STALL_I_DIS14_0 Endpoint 14 IN direction stall is enabled. 0 STALL_I_DIS14_1 Endpoint 14 IN direction stall is disabled. 0x1 STALL_I_DIS15 STALL_I_DIS15 7 1 read-write STALL_I_DIS15_0 Endpoint 15 IN direction stall is enabled. 0 STALL_I_DIS15_1 Endpoint 15 IN direction stall is disabled. 0x1 STALL_I_DIS8 STALL_I_DIS8 0 1 read-write STALL_I_DIS8_0 Endpoint 8 IN direction stall is enabled. 0 STALL_I_DIS8_1 Endpoint 8 IN direction stall is disabled. 0x1 STALL_I_DIS9 STALL_I_DIS9 1 1 read-write STALL_I_DIS9_0 Endpoint 9 IN direction stall is enabled. 0 STALL_I_DIS9_1 Endpoint 9 IN direction stall is disabled. 0x1 STALL_IL_DIS Peripheral mode stall disable for endpoints 7 to 0 in IN direction 0x130 8 read-write n 0x0 0x0 STALL_I_DIS0 STALL_I_DIS0 0 1 read-write STALL_I_DIS0_0 Endpoint 0 IN direction stall is enabled. 0 STALL_I_DIS0_1 Endpoint 0 IN direction stall is disabled. 0x1 STALL_I_DIS1 STALL_I_DIS1 1 1 read-write STALL_I_DIS1_0 Endpoint 1 IN direction stall is enabled. 0 STALL_I_DIS1_1 Endpoint 1 IN direction stall is disabled. 0x1 STALL_I_DIS2 STALL_I_DIS2 2 1 read-write STALL_I_DIS2_0 Endpoint 2 IN direction stall is enabled. 0 STALL_I_DIS2_1 Endpoint 2 IN direction stall is disabled. 0x1 STALL_I_DIS3 STALL_I_DIS3 3 1 read-write STALL_I_DIS3_0 Endpoint 3 IN direction stall is enabled. 0 STALL_I_DIS3_1 Endpoint 3 IN direction stall is disabled. 0x1 STALL_I_DIS4 STALL_I_DIS4 4 1 read-write STALL_I_DIS4_0 Endpoint 4 IN direction stall is enabled. 0 STALL_I_DIS4_1 Endpoint 4 IN direction stall is disabled. 0x1 STALL_I_DIS5 STALL_I_DIS5 5 1 read-write STALL_I_DIS5_0 Endpoint 5 IN direction stall is enabled. 0 STALL_I_DIS5_1 Endpoint 5 IN direction stall is disabled. 0x1 STALL_I_DIS6 STALL_I_DIS6 6 1 read-write STALL_I_DIS6_0 Endpoint 6 IN direction stall is enabled. 0 STALL_I_DIS6_1 Endpoint 6 IN direction stall is disabled. 0x1 STALL_I_DIS7 STALL_I_DIS7 7 1 read-write STALL_I_DIS7_0 Endpoint 7 IN direction stall is enabled. 0 STALL_I_DIS7_1 Endpoint 7 IN direction stall is disabled. 0x1 STALL_OH_DIS Peripheral mode stall disable for endpoints 15 to 8 in OUT direction 0x13C 8 read-write n 0x0 0x0 STALL_O_DIS10 STALL_O_DIS10 2 1 read-write STALL_O_DIS10_0 Endpoint 10 OUT direction stall is enabled. 0 STALL_O_DIS10_1 Endpoint 10 OUT direction stall is disabled. 0x1 STALL_O_DIS11 STALL_O_DIS11 3 1 read-write STALL_O_DIS11_0 Endpoint 11 OUT direction stall is enabled. 0 STALL_O_DIS11_1 Endpoint 11 OUT direction stall is disabled. 0x1 STALL_O_DIS12 STALL_O_DIS12 4 1 read-write STALL_O_DIS12_0 Endpoint 12 OUT direction stall is enabled. 0 STALL_O_DIS12_1 Endpoint 12 OUT direction stall is disabled. 0x1 STALL_O_DIS13 STALL_O_DIS13 5 1 read-write STALL_O_DIS13_0 Endpoint 13 OUT direction stall is enabled. 0 STALL_O_DIS13_1 Endpoint 13 OUT direction stall is disabled. 0x1 STALL_O_DIS14 STALL_O_DIS14 6 1 read-write STALL_O_DIS14_0 Endpoint 14 OUT direction stall is enabled. 0 STALL_O_DIS14_1 Endpoint 14 OUT direction stall is disabled. 0x1 STALL_O_DIS15 STALL_O_DIS15 7 1 read-write STALL_O_DIS15_0 Endpoint 15 OUT direction stall is enabled. 0 STALL_O_DIS15_1 Endpoint 15 OUT direction stall is disabled. 0x1 STALL_O_DIS8 STALL_O_DIS8 0 1 read-write STALL_O_DIS8_0 Endpoint 8 OUT direction stall is enabled. 0 STALL_O_DIS8_1 Endpoint 8 OUT direction stall is disabled. 0x1 STALL_O_DIS9 STALL_O_DIS9 1 1 read-write STALL_O_DIS9_0 Endpoint 9 OUT direction stall is enabled. 0 STALL_O_DIS9_1 Endpoint 9 OUT direction stall is disabled. 0x1 STALL_OL_DIS Peripheral mode stall disable for endpoints 7 to 0 in OUT direction 0x138 8 read-write n 0x0 0x0 STALL_O_DIS0 STALL_O_DIS0 0 1 read-write STALL_O_DIS0_0 Endpoint 0 OUT direction stall is enabled. 0 STALL_O_DIS0_1 Endpoint 0 OUT direction stall is disabled. 0x1 STALL_O_DIS1 STALL_O_DIS1 1 1 read-write STALL_O_DIS1_0 Endpoint 1 OUT direction stall is enabled. 0 STALL_O_DIS1_1 Endpoint 1 OUT direction stall is disabled. 0x1 STALL_O_DIS2 STALL_O_DIS2 2 1 read-write STALL_O_DIS2_0 Endpoint 2 OUT direction stall is enabled. 0 STALL_O_DIS2_1 Endpoint 2 OUT direction stall is disabled. 0x1 STALL_O_DIS3 STALL_O_DIS3 3 1 read-write STALL_O_DIS3_0 Endpoint 3 OUT direction stall is enabled. 0 STALL_O_DIS3_1 Endpoint 3 OUT direction stall is disabled. 0x1 STALL_O_DIS4 STALL_O_DIS4 4 1 read-write STALL_O_DIS4_0 Endpoint 4 OUT direction stall is enabled. 0 STALL_O_DIS4_1 Endpoint 4 OUT direction stall is disabled. 0x1 STALL_O_DIS5 STALL_O_DIS5 5 1 read-write STALL_O_DIS5_0 Endpoint 5 OUT direction stall is enabled. 0 STALL_O_DIS5_1 Endpoint 5 OUT direction stall is disabled. 0x1 STALL_O_DIS6 STALL_O_DIS6 6 1 read-write STALL_O_DIS6_0 Endpoint 6 OUT direction stall is enabled. 0 STALL_O_DIS6_1 Endpoint 6 OUT direction stall is disabled. 0x1 STALL_O_DIS7 STALL_O_DIS7 7 1 read-write STALL_O_DIS7_0 Endpoint 7 OUT direction stall is enabled. 0 STALL_O_DIS7_1 Endpoint 7 OUT direction stall is disabled. 0x1 STAT Status register 0x90 8 read-only n 0x0 0x0 ENDP ENDP 4 4 read-only ODD Odd bank 2 1 read-only TX Transmit Indicator 3 1 read-only TX_0 The most recent transaction was a receive operation. 0 TX_1 The most recent transaction was a transmit operation. 0x1 USBCTRL USB Control register 0x100 8 read-write n 0x0 0x0 PDE Pulldown enable 6 1 read-write PDE_0 Weak pulldowns are disabled on D+ and D-. 0 PDE_1 Weak pulldowns are enabled on D+ and D-. 0x1 SUSP Suspend 7 1 read-write SUSP_0 USB transceiver is not in the Suspend state. 0 SUSP_1 USB transceiver is in the Suspend state. 0x1 UARTCHLS UART Signal Channel Select 5 1 read-write UARTCHLS_0 USB DP/DM signals are used as UART TX/RX. 0 UARTCHLS_1 USB DP/DM signals are used as UART RX/TX. 0x1 UARTSEL UART Select 4 1 read-write UARTSEL_0 USB signals are not used as UART signals. 0 UARTSEL_1 USB signals are used as UART signals. 0x1 USBTRC0 USB Transceiver Control register 0 0x10C 8 read-write n 0x0 0x0 SYNC_DET Synchronous USB Interrupt Detect 1 1 read-only SYNC_DET_0 Synchronous interrupt has not been detected. 0 SYNC_DET_1 Synchronous interrupt has been detected. 0x1 USBRESET USB Reset 7 1 write-only USBRESET_0 Normal USB module operation. 0 USBRESET_1 Returns the USB module to its reset state. 0x1 USBRESMEN Asynchronous Resume Interrupt Enable 5 1 read-write USBRESMEN_0 USB asynchronous wakeup from Suspend mode is disabled. 0 USBRESMEN_1 USB asynchronous wakeup from Suspend mode is enabled. 0x1 USB_CLK_RECOVERY_INT Combined USB Clock Recovery interrupt status 2 1 read-only USB_RESUME_INT USB Asynchronous Interrupt 0 1 read-only USB_RESUME_INT_0 No interrupt was generated. 0 USB_RESUME_INT_1 Interrupt was generated because of the USB asynchronous interrupt. 0x1 VFEDG_DET VREGIN Falling Edge Interrupt Detect 4 1 read-only VFEDG_DET_0 VREGIN falling edge interrupt has not been detected. 0 VFEDG_DET_1 VREGIN falling edge interrupt has been detected. 0x1 VREDG_DET VREGIN Rising Edge Interrupt Detect 3 1 read-only VREDG_DET_0 VREGIN rising edge interrupt has not been detected. 0 VREDG_DET_1 VREGIN rising edge interrupt has been detected. 0x1 VREGIN_STS VREGIN_STS 6 1 read-only USBVREG USBVREG USBVREG 0x0 0x0 0x8 registers n CFGCTRL USB VREG Configuration Control Register 0x4 32 read-write n 0x0 0x0 URWE USB Voltage Regulator Enable Write Enable 24 1 read-write URWE_0 CTRL[EN] can not be written. 0 URWE_1 CTRL[EN] can be written. 0x1 USSWE USB Voltage Rregulator Stop Standby Write Enable 26 1 read-write USSWE_0 CTRL[SSTBY] field cannot be written. 0 USSWE_1 CTRL[SSTBY] can be written. 0x1 UVSWE USB Voltage Regulator VLP Standby Write Enable 25 1 read-write UVSWE_0 CTRL[VSTBY] cannot be written. 0 UVSWE_1 CTRL[VSTBY] can be written. 0x1 CTRL USB VREG Control Register 0x0 32 read-write n 0x0 0x0 EN USB Voltage Regulator Enable 31 1 read-write EN_0 USB voltage regulator is disabled. 0 EN_1 USB voltage regulator is enabled. 0x1 SSTBY USB Voltage Regulator in Standby Mode during Stop, VLPS, LLS and VLLS Modes 30 1 read-write SSTBY_0 USB voltage regulator is not in standby during Stop,VLPS,LLS and VLLS modes. 0 SSTBY_1 USB voltage regulator is in standby during Stop,VLPS,LLS and VLLS modes. 0x1 VSTBY USB Voltage Regulator in Standby Mode during VLPR and VLPW modes 29 1 read-write VSTBY_0 USB voltage regulator is not in standby during VLPR and VLPW modes. 0 VSTBY_1 USB voltage regulator in standby during VLPR and VLPW modes. 0x1 USDHC0 uSDHC USDHC0 0x0 0x0 0xCC registers n USDHC0 40 ADMA_ERR_STATUS ADMA Error Status Register 0x54 32 read-only n 0x0 0x0 ADMADCE ADMA Descriptor Error 3 1 read-only ADMADCE_0 No Error 0 ADMADCE_1 Error 0x1 ADMAES ADMA Error State (when ADMA Error is occurred) 0 2 read-only ADMALME ADMA Length Mismatch Error 2 1 read-only ADMALME_0 No Error 0 ADMALME_1 Error 0x1 ADMA_SYS_ADDR ADMA System Address 0x58 32 read-write n 0x0 0x0 ADS_ADDR ADMA System Address 2 30 read-write AUTOCMD12_ERR_STATUS Auto CMD12 Error Status 0x3C 32 read-only n 0x0 0x0 AC12CE Auto CMD12 / 23 CRC Error 3 1 read-only AC12CE_0 No CRC error 0 AC12CE_1 CRC Error Met in Auto CMD12/23 Response 0x1 AC12EBE Auto CMD12 / 23 End Bit Error 2 1 read-only AC12EBE_0 No error 0 AC12EBE_1 End Bit Error Generated 0x1 AC12IE Auto CMD12 / 23 Index Error 4 1 read-only AC12IE_0 No error 0 AC12IE_1 Error, the CMD index in response is not CMD12/23 0x1 AC12NE Auto CMD12 Not Executed 0 1 read-only AC12NE_0 Executed 0 AC12NE_1 Not executed 0x1 AC12TOE Auto CMD12 / 23 Timeout Error 1 1 read-only AC12TOE_0 No error 0 AC12TOE_1 Time out 0x1 CNIBAC12E Command Not Issued By Auto CMD12 Error 7 1 read-only CNIBAC12E_0 No error 0 CNIBAC12E_1 Not Issued 0x1 BLK_ATT Block Attributes 0x4 32 read-write n 0x0 0x0 BLKCNT Block Count 16 16 read-write BLKCNT_0 Stop Count 0 BLKCNT_1 1 block 0x1 BLKCNT_2 2 blocks 0x2 BLKCNT_65535 65535 blocks 0xFFFF BLKSIZE Block Size 0 13 read-write BLKSIZE_0 No data transfer 0 BLKSIZE_1 1 Byte 0x1 BLKSIZE_4096 4096 Bytes 0x1000 BLKSIZE_511 511 Bytes 0x1FF BLKSIZE_2 2 Bytes 0x2 BLKSIZE_512 512 Bytes 0x200 BLKSIZE_3 3 Bytes 0x3 BLKSIZE_4 4 Bytes 0x4 BLKSIZE_2048 2048 Bytes 0x800 CMD_ARG Command Argument 0x8 32 read-write n 0x0 0x0 CMDARG Command Argument 0 32 read-write CMD_RSP0 Command Response0 0x10 32 read-only n 0x0 0x0 CMDRSP0 Command Response 0 0 32 read-only CMD_RSP1 Command Response1 0x14 32 read-only n 0x0 0x0 CMDRSP1 Command Response 1 0 32 read-only CMD_RSP2 Command Response2 0x18 32 read-only n 0x0 0x0 CMDRSP2 Command Response 2 0 32 read-only CMD_RSP3 Command Response3 0x1C 32 read-only n 0x0 0x0 CMDRSP3 Command Response 3 0 32 read-only CMD_XFR_TYP Command Transfer Type 0xC 32 read-write n 0x0 0x0 CCCEN Command CRC Check Enable 19 1 read-write CCCEN_0 Disable 0 CCCEN_1 Enable 0x1 CICEN Command Index Check Enable 20 1 read-write CICEN_0 Disable 0 CICEN_1 Enable 0x1 CMDINX Command Index 24 6 read-write CMDTYP Command Type 22 2 read-write CMDTYP_0 Normal Other commands 0 CMDTYP_1 Suspend CMD52 for writing Bus Suspend in CCCR 0x1 CMDTYP_2 Resume CMD52 for writing Function Select in CCCR 0x2 CMDTYP_3 Abort CMD12, CMD52 for writing I/O Abort in CCCR 0x3 DPSEL Data Present Select 21 1 read-write DPSEL_0 No Data Present 0 DPSEL_1 Data Present 0x1 RSPTYP Response Type Select 16 2 read-write RSPTYP_0 No Response 0 RSPTYP_1 Response Length 136 0x1 RSPTYP_2 Response Length 48 0x2 RSPTYP_3 Response Length 48, check Busy after response 0x3 DATA_BUFF_ACC_PORT Data Buffer Access Port 0x20 32 read-write n 0x0 0x0 DATCONT Data Content 0 32 read-write DS_ADDR DMA System Address 0x0 32 read-write n 0x0 0x0 DS_ADDR DS_ADDR 0 32 read-write FORCE_EVENT Force Event 0x50 32 read-write n 0x0 0x0 FEVTAC12CE Force Event Auto Command 12 CRC Error 2 1 write-only FEVTAC12E Force Event Auto Command 12 Error 24 1 write-only FEVTAC12EBE Force Event Auto Command 12 End Bit Error 3 1 write-only FEVTAC12IE Force Event Auto Command 12 Index Error 4 1 write-only FEVTAC12NE Force Event Auto Command 12 Not Executed 0 1 write-only FEVTAC12TOE Force Event Auto Command 12 Time Out Error 1 1 write-only FEVTCCE Force Event Command CRC Error 17 1 write-only FEVTCEBE Force Event Command End Bit Error 18 1 write-only FEVTCIE Force Event Command Index Error 19 1 write-only FEVTCINT Force Event Card Interrupt 31 1 write-only FEVTCNIBAC12E Force Event Command Not Executed By Auto Command 12 Error 7 1 write-only FEVTCTOE Force Event Command Time Out Error 16 1 write-only FEVTDCE Force Event Data CRC Error 21 1 write-only FEVTDEBE Force Event Data End Bit Error 22 1 write-only FEVTDMAE Force Event DMA Error 28 1 write-only FEVTDTOE Force Event Data Time Out Error 20 1 write-only HOST_CTRL_CAP Host Controller Capabilities 0x40 32 read-only n 0x0 0x0 ADMAS ADMA Support 20 1 read-only ADMAS_0 Advanced DMA Not supported 0 ADMAS_1 Advanced DMA Supported 0x1 DDR50_SUPPORT DDR50 support 2 1 read-only DMAS DMA Support 22 1 read-only DMAS_0 DMA not supported 0 DMAS_1 DMA Supported 0x1 HSS High Speed Support 21 1 read-only HSS_0 High Speed Not Supported 0 HSS_1 High Speed Supported 0x1 MBL Max Block Length 16 3 read-only MBL_0 512 bytes 0 MBL_1 1024 bytes 0x1 MBL_2 2048 bytes 0x2 MBL_3 4096 bytes 0x3 SRS Suspend / Resume Support 23 1 read-only SRS_0 Not supported 0 SRS_1 Supported 0x1 VS18 Voltage Support 1.8 V 26 1 read-only VS18_0 1.8V not supported 0 VS18_1 1.8V supported 0x1 VS30 Voltage Support 3.0 V 25 1 read-only VS30_0 3.0V not supported 0 VS30_1 3.0V supported 0x1 VS33 Voltage Support 3.3V 24 1 read-only VS33_0 3.3V not supported 0 VS33_1 3.3V supported 0x1 INT_SIGNAL_EN Interrupt Signal Enable 0x38 32 read-write n 0x0 0x0 AC12EIEN Auto CMD12 Error Interrupt Enable 24 1 read-write AC12EIEN_0 Masked 0 AC12EIEN_1 Enabled 0x1 BGEIEN Block Gap Event Interrupt Enable 2 1 read-write BGEIEN_0 Masked 0 BGEIEN_1 Enabled 0x1 BRRIEN Buffer Read Ready Interrupt Enable 5 1 read-write BRRIEN_0 Masked 0 BRRIEN_1 Enabled 0x1 BWRIEN Buffer Write Ready Interrupt Enable 4 1 read-write BWRIEN_0 Masked 0 BWRIEN_1 Enabled 0x1 CCEIEN Command CRC Error Interrupt Enable 17 1 read-write CCEIEN_0 Masked 0 CCEIEN_1 Enabled 0x1 CCIEN Command Complete Interrupt Enable 0 1 read-write CCIEN_0 Masked 0 CCIEN_1 Enabled 0x1 CEBEIEN Command End Bit Error Interrupt Enable 18 1 read-write CEBEIEN_0 Masked 0 CEBEIEN_1 Enabled 0x1 CIEIEN Command Index Error Interrupt Enable 19 1 read-write CIEIEN_0 Masked 0 CIEIEN_1 Enabled 0x1 CINSIEN Card Insertion Interrupt Enable 6 1 read-write CINSIEN_0 Masked 0 CINSIEN_1 Enabled 0x1 CINTIEN Card Interrupt Interrupt Enable 8 1 read-write CINTIEN_0 Masked 0 CINTIEN_1 Enabled 0x1 CRMIEN Card Removal Interrupt Enable 7 1 read-write CRMIEN_0 Masked 0 CRMIEN_1 Enabled 0x1 CTOEIEN Command Timeout Error Interrupt Enable 16 1 read-write CTOEIEN_0 Masked 0 CTOEIEN_1 Enabled 0x1 DCEIEN Data CRC Error Interrupt Enable 21 1 read-write DCEIEN_0 Masked 0 DCEIEN_1 Enabled 0x1 DEBEIEN Data End Bit Error Interrupt Enable 22 1 read-write DEBEIEN_0 Masked 0 DEBEIEN_1 Enabled 0x1 DINTIEN DMA Interrupt Enable 3 1 read-write DINTIEN_0 Masked 0 DINTIEN_1 Enabled 0x1 DMAEIEN DMA Error Interrupt Enable 28 1 read-write DMAEIEN_0 Masked 0 DMAEIEN_1 Enable 0x1 DTOEIEN Data Timeout Error Interrupt Enable 20 1 read-write DTOEIEN_0 Masked 0 DTOEIEN_1 Enabled 0x1 TCIEN Transfer Complete Interrupt Enable 1 1 read-write TCIEN_0 Masked 0 TCIEN_1 Enabled 0x1 INT_STATUS Interrupt Status 0x30 32 read-write n 0x0 0x0 AC12E Auto CMD12 Error 24 1 read-write oneToClear AC12E_0 No Error 0 AC12E_1 Error 0x1 BGE Block Gap Event 2 1 read-write oneToClear BGE_0 No block gap event 0 BGE_1 Transaction stopped at block gap 0x1 BRR Buffer Read Ready 5 1 read-write oneToClear BRR_0 Not ready to read buffer 0 BRR_1 Ready to read buffer 0x1 BWR Buffer Write Ready 4 1 read-write oneToClear BWR_0 Not ready to write buffer 0 BWR_1 Ready to write buffer: 0x1 CC Command Complete 0 1 read-write oneToClear CC_0 Command not complete 0 CC_1 Command complete 0x1 CCE Command CRC Error 17 1 read-write oneToClear CCE_0 No Error 0 CCE_1 CRC Error Generated. 0x1 CEBE Command End Bit Error 18 1 read-write oneToClear CEBE_0 No Error 0 CEBE_1 End Bit Error Generated 0x1 CIE Command Index Error 19 1 read-write oneToClear CIE_0 No Error 0 CIE_1 Error 0x1 CINS Card Insertion 6 1 read-write oneToClear CINS_0 Card state unstable or removed 0 CINS_1 Card inserted 0x1 CINT Card Interrupt 8 1 read-write oneToClear CINT_0 No Card Interrupt 0 CINT_1 Generate Card Interrupt 0x1 CRM Card Removal 7 1 read-write oneToClear CRM_0 Card state unstable or inserted 0 CRM_1 Card removed 0x1 CTOE Command Timeout Error 16 1 read-write oneToClear CTOE_0 No Error 0 CTOE_1 Time out 0x1 DCE Data CRC Error 21 1 read-write oneToClear DCE_0 No Error 0 DCE_1 Error 0x1 DEBE Data End Bit Error 22 1 read-write oneToClear DEBE_0 No Error 0 DEBE_1 Error 0x1 DINT DMA Interrupt 3 1 read-write oneToClear DINT_0 No DMA Interrupt 0 DINT_1 DMA Interrupt is generated 0x1 DMAE DMA Error 28 1 read-write oneToClear DMAE_0 No Error 0 DMAE_1 Error 0x1 DTOE Data Timeout Error 20 1 read-write oneToClear DTOE_0 No Error 0 DTOE_1 Time out 0x1 TC Transfer Complete 1 1 read-write oneToClear TC_0 Transfer not complete 0 TC_1 Transfer complete 0x1 INT_STATUS_EN Interrupt Status Enable 0x34 32 read-write n 0x0 0x0 AC12ESEN Auto CMD12 Error Status Enable 24 1 read-write AC12ESEN_0 Masked 0 AC12ESEN_1 Enabled 0x1 BGESEN Block Gap Event Status Enable 2 1 read-write BGESEN_0 Masked 0 BGESEN_1 Enabled 0x1 BRRSEN Buffer Read Ready Status Enable 5 1 read-write BRRSEN_0 Masked 0 BRRSEN_1 Enabled 0x1 BWRSEN Buffer Write Ready Status Enable 4 1 read-write BWRSEN_0 Masked 0 BWRSEN_1 Enabled 0x1 CCESEN Command CRC Error Status Enable 17 1 read-write CCESEN_0 Masked 0 CCESEN_1 Enabled 0x1 CCSEN Command Complete Status Enable 0 1 read-write CCSEN_0 Masked 0 CCSEN_1 Enabled 0x1 CEBESEN Command End Bit Error Status Enable 18 1 read-write CEBESEN_0 Masked 0 CEBESEN_1 Enabled 0x1 CIESEN Command Index Error Status Enable 19 1 read-write CIESEN_0 Masked 0 CIESEN_1 Enabled 0x1 CINSSEN Card Insertion Status Enable 6 1 read-write CINSSEN_0 Masked 0 CINSSEN_1 Enabled 0x1 CINTSEN Card Interrupt Status Enable 8 1 read-write CINTSEN_0 Masked 0 CINTSEN_1 Enabled 0x1 CRMSEN Card Removal Status Enable 7 1 read-write CRMSEN_0 Masked 0 CRMSEN_1 Enabled 0x1 CTOESEN Command Timeout Error Status Enable 16 1 read-write CTOESEN_0 Masked 0 CTOESEN_1 Enabled 0x1 DCESEN Data CRC Error Status Enable 21 1 read-write DCESEN_0 Masked 0 DCESEN_1 Enabled 0x1 DEBESEN Data End Bit Error Status Enable 22 1 read-write DEBESEN_0 Masked 0 DEBESEN_1 Enabled 0x1 DINTSEN DMA Interrupt Status Enable 3 1 read-write DINTSEN_0 Masked 0 DINTSEN_1 Enabled 0x1 DMAESEN DMA Error Status Enable 28 1 read-write DMAESEN_0 Masked 0 DMAESEN_1 Enabled 0x1 DTOESEN Data Timeout Error Status Enable 20 1 read-write DTOESEN_0 Masked 0 DTOESEN_1 Enabled 0x1 TCSEN Transfer Complete Status Enable 1 1 read-write TCSEN_0 Masked 0 TCSEN_1 Enabled 0x1 MIX_CTRL Mixer Control 0x48 32 read-write n 0x0 0x0 AC12EN Auto CMD12 Enable 2 1 read-write AC12EN_0 Disable 0 AC12EN_1 Enable 0x1 AC23EN Auto CMD23 Enable 7 1 read-write BCEN Block Count Enable 1 1 read-write BCEN_0 Disable 0 BCEN_1 Enable 0x1 DDR_EN Dual Data Rate mode selection 3 1 read-write DMAEN DMA Enable 0 1 read-write DMAEN_0 Disable 0 DMAEN_1 Enable 0x1 DTDSEL Data Transfer Direction Select 4 1 read-write DTDSEL_0 Write (Host to Card) 0 DTDSEL_1 Read (Card to Host) 0x1 MSBSEL Multi / Single Block Select 5 1 read-write MSBSEL_0 Single Block 0 MSBSEL_1 Multiple Blocks 0x1 NIBBLE_POS NIBBLE_POS 6 1 read-write MMC_BOOT MMC Boot Register 0xC4 32 read-write n 0x0 0x0 AUTO_SABG_EN AUTO_SABG_EN 7 1 read-write BOOT_ACK BOOT_ACK 4 1 read-write BOOT_ACK_0 No ack 0 BOOT_ACK_1 Ack 0x1 BOOT_BLK_CNT BOOT_BLK_CNT 16 16 read-write BOOT_EN BOOT_EN 6 1 read-write BOOT_EN_0 Fast boot disable 0 BOOT_EN_1 Fast boot enable 0x1 BOOT_MODE BOOT_MODE 5 1 read-write BOOT_MODE_0 Normal boot 0 BOOT_MODE_1 Alternative boot 0x1 DISABLE_TIME_OUT Disable Time Out 8 1 read-write DISABLE_TIME_OUT_0 Enable time out 0 DISABLE_TIME_OUT_1 Disable time out 0x1 DTOCV_ACK DTOCV_ACK 0 4 read-write DTOCV_ACK_0 SDCLK x 2^14 0 DTOCV_ACK_1 SDCLK x 2^15 0x1 DTOCV_ACK_2 SDCLK x 2^16 0x2 DTOCV_ACK_3 SDCLK x 2^17 0x3 DTOCV_ACK_4 SDCLK x 2^18 0x4 DTOCV_ACK_5 SDCLK x 2^19 0x5 DTOCV_ACK_6 SDCLK x 2^20 0x6 DTOCV_ACK_7 SDCLK x 2^21 0x7 DTOCV_ACK_14 SDCLK x 2^28 0xE DTOCV_ACK_15 SDCLK x 2^29 0xF PRES_STATE Present State 0x24 32 read-only n 0x0 0x0 BREN Buffer Read Enable 11 1 read-only BREN_0 Read disable 0 BREN_1 Read enable 0x1 BWEN Buffer Write Enable 10 1 read-only BWEN_0 Write disable 0 BWEN_1 Write enable 0x1 CDIHB Command Inhibit (DATA) 1 1 read-only CDIHB_0 Can issue command which uses the DATA line 0 CDIHB_1 Cannot issue command which uses the DATA line 0x1 CDPL Card Detect Pin Level 18 1 read-only CDPL_0 No card present (CD_B = 1) 0 CDPL_1 Card present (CD_B = 0) 0x1 CIHB Command Inhibit (CMD) 0 1 read-only CIHB_0 Can issue command using only CMD line 0 CIHB_1 Cannot issue command 0x1 CINST Card Inserted 16 1 read-only CINST_0 Power on Reset or No Card 0 CINST_1 Card Inserted 0x1 CLSL CMD Line Signal Level 23 1 read-only DLA Data Line Active 2 1 read-only DLA_0 DATA Line Inactive 0 DLA_1 DATA Line Active 0x1 DLSL DATA[7:0] Line Signal Level 24 8 read-only DATA0 Data 0 line signal level 0 DATA1 Data 1 line signal level 0x1 DATA2 Data 2 line signal level 0x2 DATA3 Data 3 line signal level 0x3 DATA4 Data 4 line signal level 0x4 DATA5 Data 5 line signal level 0x5 DATA6 Data 6 line signal level 0x6 DATA7 Data 7 line signal level 0x7 HCKOFF HCLK Gated Off Internally 5 1 read-only HCKOFF_0 HCLK is active. 0 HCKOFF_1 HCLK is gated off. 0x1 IPGOFF IPG_CLK Gated Off Internally 4 1 read-only IPGOFF_0 IPG_CLK is active. 0 IPGOFF_1 IPG_CLK is gated off. 0x1 PEROFF IPG_PERCLK Gated Off Internally 6 1 read-only PEROFF_0 IPG_PERCLK is active. 0 PEROFF_1 IPG_PERCLK is gated off. 0x1 RTA Read Transfer Active 9 1 read-only RTA_0 No valid data 0 RTA_1 Transferring data 0x1 SDOFF SD Clock Gated Off Internally 7 1 read-only SDOFF_0 SD Clock is active. 0 SDOFF_1 SD Clock is gated off. 0x1 SDSTB SD Clock Stable 3 1 read-only SDSTB_0 Clock is changing frequency and not stable. 0 SDSTB_1 Clock is stable. 0x1 WPSPL Write Protect Switch Pin Level 19 1 read-only WPSPL_0 Write protected (WP = 1) 0 WPSPL_1 Write enabled (WP = 0) 0x1 WTA Write Transfer Active 8 1 read-only WTA_0 No valid data 0 WTA_1 Transferring data 0x1 PROT_CTRL Protocol Control 0x28 32 read-write n 0x0 0x0 BURST_LEN_EN BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP 27 3 read-write BURST_LEN_EN_1 Burst length is enabled for INCR #xx1 CDSS Card Detect Signal Selection 7 1 read-write CDSS_0 Card Detection Level is selected (for normal purpose). 0 CDSS_1 Card Detection Test Level is selected (for test purpose). 0x1 CDTL Card Detect Test Level 6 1 read-write CDTL_0 Card Detect Test Level is 0, no card inserted 0 CDTL_1 Card Detect Test Level is 1, card inserted 0x1 CREQ Continue Request 17 1 read-write CREQ_0 No effect 0 CREQ_1 Restart 0x1 D3CD DATA3 as Card Detection Pin 3 1 read-write D3CD_0 DATA3 does not monitor Card Insertion 0 D3CD_1 DATA3 as Card Detection Pin 0x1 DMASEL DMA Select 8 2 read-write DMASEL_0 No DMA or Simple DMA is selected 0 DMASEL_1 ADMA1 is selected 0x1 DMASEL_2 ADMA2 is selected 0x2 DTW Data Transfer Width 1 2 read-write DTW_0 1-bit mode 0 DTW_1 4-bit mode 0x1 DTW_2 8-bit mode 0x2 EMODE Endian Mode 4 2 read-write EMODE_0 Big Endian Mode 0 EMODE_1 Half Word Big Endian Mode 0x1 EMODE_2 Little Endian Mode 0x2 IABG Interrupt At Block Gap 19 1 read-write IABG_0 Disabled 0 IABG_1 Enabled 0x1 LCTL LED Control 0 1 read-write LCTL_0 LED off 0 LCTL_1 LED on 0x1 NON_EXACT_BLK_RD NON_EXACT_BLK_RD 30 1 read-write NON_EXACT_BLK_RD_0 The block read is exact block read. Host driver doesn't need to issue abort command to terminate this multi-block read. 0 NON_EXACT_BLK_RD_1 The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read. 0x1 RD_DONE_NO_8CLK RD_DONE_NO_8CLK 20 1 read-write RWCTL Read Wait Control 18 1 read-write RWCTL_0 Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set 0 RWCTL_1 Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set 0x1 SABGREQ Stop At Block Gap Request 16 1 read-write SABGREQ_0 Transfer 0 SABGREQ_1 Stop 0x1 WECINS Wakeup Event Enable On SD Card Insertion 25 1 read-write WECINS_0 Disable 0 WECINS_1 Enable 0x1 WECINT Wakeup Event Enable On Card Interrupt 24 1 read-write WECINT_0 Disable 0 WECINT_1 Enable 0x1 WECRM Wakeup Event Enable On SD Card Removal 26 1 read-write WECRM_0 Disable 0 WECRM_1 Enable 0x1 SYS_CTRL System Control 0x2C 32 read-write n 0x0 0x0 DTOCV Data Timeout Counter Value 16 4 read-write DTOCV_0 no description available 0 DTOCV_1 no description available 0x1 DTOCV_13 no description available 0xD DTOCV_14 no description available 0xE DTOCV_15 no description available 0xF DVS Divisor 4 4 read-write DVS_0 Divide-by-1 0 DVS_1 Divide-by-2 0x1 DVS_14 Divide-by-15 0xE DVS_15 Divide-by-16 0xF INITA Initialization Active 27 1 read-write IPP_RST_N IPP_RST_N 23 1 read-write RSTA Software Reset For ALL 24 1 read-write RSTA_0 No Reset 0 RSTA_1 Reset 0x1 RSTC Software Reset For CMD Line 25 1 read-write RSTC_0 No Reset 0 RSTC_1 Reset 0x1 RSTD Software Reset For DATA Line 26 1 read-write RSTD_0 No Reset 0 RSTD_1 Reset 0x1 SDCLKFS SDCLK Frequency Select 8 8 read-write VEND_SPEC Vendor Specific Register 0xC0 32 read-write n 0x0 0x0 AC12_WR_CHKBUSY_EN AC12_WR_CHKBUSY_EN 3 1 read-write AC12_WR_CHKBUSY_EN_0 Do not check busy after auto CMD12 for write data packet 0 AC12_WR_CHKBUSY_EN_1 Check busy after auto CMD12 for write data packet 0x1 CMD_BYTE_EN CMD_BYTE_EN 31 1 read-write CMD_BYTE_EN_0 Disable 0 CMD_BYTE_EN_1 Enable 0x1 CONFLICT_CHK_EN Conflict check enable. 2 1 read-write CONFLICT_CHK_EN_0 Conflict check disable 0 CONFLICT_CHK_EN_1 Conflict check enable 0x1 CRC_CHK_DIS CRC Check Disable 15 1 read-write CRC_CHK_DIS_0 Check CRC16 for every read data packet and check CRC bits for every write data packet 0 CRC_CHK_DIS_1 Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet 0x1 FRC_SDCLK_ON FRC_SDCLK_ON 8 1 read-write FRC_SDCLK_ON_0 CLK active or inactive is fully controlled by the hardware. 0 FRC_SDCLK_ON_1 Force CLK active. 0x1 VSELECT Voltage Selection 1 1 read-write VSELECT_0 Change the voltage to high voltage range, around 3.0 V 0 VSELECT_1 Change the voltage to low voltage range, around 1.8 V 0x1 VEND_SPEC2 Vendor Specific 2 Register 0xC8 32 read-write n 0x0 0x0 ACMD23_ARGU2_EN Argument2 register enable for ACMD23 12 1 read-write ACMD23_ARGU2_EN_0 Disable 0 ACMD23_ARGU2_EN_1 Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enable. 0x1 AHB_RST AHB BUS reset 14 1 read-write CARD_INT_D3_TEST Card Interrupt Detection Test 3 1 read-write CARD_INT_D3_TEST_0 Check the card interrupt only when DATA3 is high. 0 CARD_INT_D3_TEST_1 Check the card interrupt by ignoring the status of DATA3. 0x1 WTMK_LVL Watermark Level 0x44 32 read-write n 0x0 0x0 RD_BRST_LEN Read Burst Length Due to system restriction, the actual burst length may not exceed 16. 8 5 read-write RD_WML Read Watermark Level 0 8 read-write WR_BRST_LEN Write Burst Length Due to system restriction, the actual burst length may not exceed 16. 24 5 read-write WR_WML Write Watermark Level 16 8 read-write VREF VREF VREF 0x0 0x0 0x6 registers n SC VREF Status and Control Register 0x1 8 read-write n 0x0 0x0 ICOMPEN Second order curvature compensation enable 5 1 read-write ICOMPEN_0 Disabled 0 ICOMPEN_1 Enabled 0x1 MODE_LV Buffer Mode selection 0 2 read-write MODE_LV_0 Bandgap on only, for stabilization and startup 0 MODE_LV_1 High power buffer mode enabled 0x1 MODE_LV_2 no description available 0x2 REGEN Regulator enable 6 1 read-write REGEN_0 Internal 1.75 V regulator is disabled. 0 REGEN_1 Internal 1.75 V regulator is enabled. 0x1 VREFEN Internal Voltage Reference enable 7 1 read-write VREFEN_0 The module is disabled. 0 VREFEN_1 The module is enabled. 0x1 VREFST Internal Voltage Reference stable 2 1 read-only VREFST_0 The module is disabled or not stable. 0 VREFST_1 The module is stable. 0x1 TRM VREF Trim Register 0x0 8 read-write n 0x0 0x0 CHOPEN Chop oscillator enable. When set, the internal chopping operation is enabled and the internal analog offset will be minimized. 6 1 read-write CHOPEN_0 Chop oscillator is disabled. 0 CHOPEN_1 Chop oscillator is enabled. 0x1 TRIM Trim bits 0 6 read-write TRIM_0 Min 0 TRIM_63 Max 0x3F TRM4 VREF Trim 2.1V Register 0x5 8 read-write n 0x0 0x0 TRIM2V1 VREF 2.1V Trim Bits 0 6 read-write TRIM2V1_0 Max 0 TRIM2V1_63 Min 0x3F VREF2V1_EN Internal Voltage Reference (2.1V) Enable 7 1 read-write VREF2V1_EN_0 VREF 2.1V is enabled 0 VREF2V1_EN_1 VREF 2.1V is disabled 0x1 WDOG0 WDOG WDOG0 0x0 0x0 0x10 registers n WDOG0 25 CNT Watchdog Counter Register 0x4 32 read-write n 0x0 0x0 CNTHIGH High byte of the Watchdog Counter 8 8 read-write CNTLOW Low byte of the Watchdog Counter 0 8 read-write CS Watchdog Control and Status Register 0x0 32 read-write n 0x0 0x0 CLK Watchdog Clock 8 2 read-write CLK_0 Bus clock 0 CLK_1 LPO clock 0x1 CLK_2 INTCLK (internal clock) 0x2 CLK_3 ERCLK (external reference clock) 0x3 CMD32EN Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words 13 1 read-write CMD32EN_0 Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. 0 CMD32EN_1 Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. 0x1 DBG Debug Enable 2 1 read-write DBG_0 Watchdog disabled in chip debug mode. 0 DBG_1 Watchdog enabled in chip debug mode. 0x1 EN Watchdog Enable 7 1 read-write EN_0 Watchdog disabled. 0 EN_1 Watchdog enabled. 0x1 FLG Watchdog Interrupt Flag 14 1 read-write oneToClear FLG_0 No interrupt occurred. 0 FLG_1 An interrupt occurred. 0x1 INT Watchdog Interrupt 6 1 read-write INT_0 Watchdog interrupts are disabled. Watchdog resets are not delayed. 0 INT_1 Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. 0x1 PRES Watchdog prescaler 12 1 read-write PRES_0 256 prescaler disabled. 0 PRES_1 256 prescaler enabled. 0x1 RCS Reconfiguration Success 10 1 read-only RCS_0 Reconfiguring WDOG. 0 RCS_1 Reconfiguration is successful. 0x1 STOP Stop Enable 0 1 read-write STOP_0 Watchdog disabled in chip stop mode. 0 STOP_1 Watchdog enabled in chip stop mode. 0x1 TST Watchdog Test 3 2 read-write TST_0 Watchdog test mode disabled. 0 TST_1 Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. 0x1 TST_2 Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. 0x2 TST_3 Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. 0x3 ULK Unlock status 11 1 read-only ULK_0 WDOG is locked. 0 ULK_1 WDOG is unlocked. 0x1 UPDATE Allow updates 5 1 read-write UPDATE_0 Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. 0 UPDATE_1 Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. 0x1 WAIT Wait Enable 1 1 read-write WAIT_0 Watchdog disabled in chip wait mode. 0 WAIT_1 Watchdog enabled in chip wait mode. 0x1 WIN Watchdog Window 15 1 read-write WIN_0 Window mode disabled. 0 WIN_1 Window mode enabled. 0x1 TOVAL Watchdog Timeout Value Register 0x8 32 read-write n 0x0 0x0 TOVALHIGH High byte of the timeout value 8 8 read-write TOVALLOW Low byte of the timeout value 0 8 read-write WIN Watchdog Window Register 0xC 32 read-write n 0x0 0x0 WINHIGH High byte of Watchdog Window 8 8 read-write WINLOW Low byte of Watchdog Window 0 8 read-write WDOG1 WDOG WDOG1 0x0 0x0 0x10 registers n CNT Watchdog Counter Register 0x4 32 read-write n 0x0 0x0 CNTHIGH High byte of the Watchdog Counter 8 8 read-write CNTLOW Low byte of the Watchdog Counter 0 8 read-write CS Watchdog Control and Status Register 0x0 32 read-write n 0x0 0x0 CLK Watchdog Clock 8 2 read-write CLK_0 Bus clock 0 CLK_1 LPO clock 0x1 CLK_2 INTCLK (internal clock) 0x2 CLK_3 ERCLK (external reference clock) 0x3 CMD32EN Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words 13 1 read-write CMD32EN_0 Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported. 0 CMD32EN_1 Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. 0x1 DBG Debug Enable 2 1 read-write DBG_0 Watchdog disabled in chip debug mode. 0 DBG_1 Watchdog enabled in chip debug mode. 0x1 EN Watchdog Enable 7 1 read-write EN_0 Watchdog disabled. 0 EN_1 Watchdog enabled. 0x1 FLG Watchdog Interrupt Flag 14 1 read-write oneToClear FLG_0 No interrupt occurred. 0 FLG_1 An interrupt occurred. 0x1 INT Watchdog Interrupt 6 1 read-write INT_0 Watchdog interrupts are disabled. Watchdog resets are not delayed. 0 INT_1 Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks from the interrupt vector fetch. 0x1 PRES Watchdog prescaler 12 1 read-write PRES_0 256 prescaler disabled. 0 PRES_1 256 prescaler enabled. 0x1 RCS Reconfiguration Success 10 1 read-only RCS_0 Reconfiguring WDOG. 0 RCS_1 Reconfiguration is successful. 0x1 STOP Stop Enable 0 1 read-write STOP_0 Watchdog disabled in chip stop mode. 0 STOP_1 Watchdog enabled in chip stop mode. 0x1 TST Watchdog Test 3 2 read-write TST_0 Watchdog test mode disabled. 0 TST_1 Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. 0x1 TST_2 Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW]. 0x2 TST_3 Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. 0x3 ULK Unlock status 11 1 read-only ULK_0 WDOG is locked. 0 ULK_1 WDOG is unlocked. 0x1 UPDATE Allow updates 5 1 read-write UPDATE_0 Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. 0 UPDATE_1 Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. 0x1 WAIT Wait Enable 1 1 read-write WAIT_0 Watchdog disabled in chip wait mode. 0 WAIT_1 Watchdog enabled in chip wait mode. 0x1 WIN Watchdog Window 15 1 read-write WIN_0 Window mode disabled. 0 WIN_1 Window mode enabled. 0x1 TOVAL Watchdog Timeout Value Register 0x8 32 read-write n 0x0 0x0 TOVALHIGH High byte of the timeout value 8 8 read-write TOVALLOW Low byte of the timeout value 0 8 read-write WIN Watchdog Window Register 0xC 32 read-write n 0x0 0x0 WINHIGH High byte of Watchdog Window 8 8 read-write WINLOW Low byte of Watchdog Window 0 8 read-write XRDC XRDC XRDC 0x0 0x0 0x22F4 registers n CR Control Register 0x0 32 read-write n 0x0 0x0 GVLDC Global Valid for MRCs 15 1 read-write GVLDC_0 XRDC MRCs are disabled. 0 GVLDC_1 XRDC MRCs are enabled. 0x1 GVLDM Global Valid MDACs(XRDC global enable/disable). 0 1 read-write GVLDM_0 XRDC MDACs are disabled. 0 GVLDM_1 XRDC MDACs are enabled. 0x1 GVLDP Global Valid for PACs/MSCs 14 1 read-write GVLDP_0 XRDC PACs/MSCs are disabled. 0 GVLDP_1 XRDC PACs/MSCs are enabled. 0x1 HRL Hardware Revision Level 1 4 read-only LK1 1-bit Lock 30 1 read-write LK1_0 Register can be written by any secure privileged write. 0 LK1_1 Register is locked (read-only) until the next reset. 0x1 VAW Virtualization aware 8 1 read-only VAW_0 Implementation is not virtualization aware. 0 VAW_1 Implementation is virtualization aware. 0x1 DERRLOC0 Domain Error Location Register 0x200 32 read-only n 0x0 0x0 MRCINST MRC instance 0 16 read-only PACINST PAC instance 16 4 read-only DERRLOC1 Domain Error Location Register 0x204 32 read-only n 0x0 0x0 MRCINST MRC instance 0 16 read-only PACINST PAC instance 16 4 read-only DERRLOC2 Domain Error Location Register 0x208 32 read-only n 0x0 0x0 MRCINST MRC instance 0 16 read-only PACINST PAC instance 16 4 read-only DERRLOC[0] Domain Error Location Register 0x400 32 read-only n 0x0 0x0 MRCINST MRC instance 0 16 read-only PACINST PAC instance 16 4 read-only DERRLOC[1] Domain Error Location Register 0x604 32 read-only n 0x0 0x0 MRCINST MRC instance 0 16 read-only PACINST PAC instance 16 4 read-only DERRLOC[2] Domain Error Location Register 0x80C 32 read-only n 0x0 0x0 MRCINST MRC instance 0 16 read-only PACINST PAC instance 16 4 read-only DERR_W0_0 Domain Error Word0 Register 0x400 32 read-only n 0x0 0x0 EADDR Error address 0 32 read-only DERR_W0_1 Domain Error Word0 Register 0x410 32 read-only n 0x0 0x0 EADDR Error address 0 32 read-only DERR_W0_16 Domain Error Word0 Register 0x500 32 read-only n 0x0 0x0 EADDR Error address 0 32 read-only DERR_W0_17 Domain Error Word0 Register 0x510 32 read-only n 0x0 0x0 EADDR Error address 0 32 read-only DERR_W0_18 Domain Error Word0 Register 0x520 32 read-only n 0x0 0x0 EADDR Error address 0 32 read-only DERR_W1_0 Domain Error Word1 Register 0x404 32 read-only n 0x0 0x0 EATR Error attributes 8 3 read-only EATR_0 Secure user mode, instruction fetch access. 0 EATR_1 Secure user mode, data access. 0x1 EATR_2 Secure privileged mode, instruction fetch access. 0x2 EATR_3 Secure privileged mode, data access. 0x3 EATR_4 Nonsecure user mode, instruction fetch access. 0x4 EATR_5 Nonsecure user mode, data access. 0x5 EATR_6 Nonsecure privileged mode, instruction fetch access. 0x6 EATR_7 Nonsecure privileged mode, data access. 0x7 EDID Error domain identifier 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only ERW_0 Read access 0 ERW_1 Write access 0x1 EST Error state 30 2 read-only EST_0 No access violation has been detected. 0 EST_1 No access violation has been detected. 0x1 EST_2 A single access violation has been detected. 0x2 EST_3 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. 0x3 DERR_W1_1 Domain Error Word1 Register 0x414 32 read-only n 0x0 0x0 EATR Error attributes 8 3 read-only EATR_0 Secure user mode, instruction fetch access. 0 EATR_1 Secure user mode, data access. 0x1 EATR_2 Secure privileged mode, instruction fetch access. 0x2 EATR_3 Secure privileged mode, data access. 0x3 EATR_4 Nonsecure user mode, instruction fetch access. 0x4 EATR_5 Nonsecure user mode, data access. 0x5 EATR_6 Nonsecure privileged mode, instruction fetch access. 0x6 EATR_7 Nonsecure privileged mode, data access. 0x7 EDID Error domain identifier 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only ERW_0 Read access 0 ERW_1 Write access 0x1 EST Error state 30 2 read-only EST_0 No access violation has been detected. 0 EST_1 No access violation has been detected. 0x1 EST_2 A single access violation has been detected. 0x2 EST_3 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. 0x3 DERR_W1_16 Domain Error Word1 Register 0x504 32 read-only n 0x0 0x0 EATR Error attributes 8 3 read-only EATR_0 Secure user mode, instruction fetch access. 0 EATR_1 Secure user mode, data access. 0x1 EATR_2 Secure privileged mode, instruction fetch access. 0x2 EATR_3 Secure privileged mode, data access. 0x3 EATR_4 Nonsecure user mode, instruction fetch access. 0x4 EATR_5 Nonsecure user mode, data access. 0x5 EATR_6 Nonsecure privileged mode, instruction fetch access. 0x6 EATR_7 Nonsecure privileged mode, data access. 0x7 EDID Error domain identifier 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only ERW_0 Read access 0 ERW_1 Write access 0x1 EST Error state 30 2 read-only EST_0 No access violation has been detected. 0 EST_1 No access violation has been detected. 0x1 EST_2 A single access violation has been detected. 0x2 EST_3 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. 0x3 DERR_W1_17 Domain Error Word1 Register 0x514 32 read-only n 0x0 0x0 EATR Error attributes 8 3 read-only EATR_0 Secure user mode, instruction fetch access. 0 EATR_1 Secure user mode, data access. 0x1 EATR_2 Secure privileged mode, instruction fetch access. 0x2 EATR_3 Secure privileged mode, data access. 0x3 EATR_4 Nonsecure user mode, instruction fetch access. 0x4 EATR_5 Nonsecure user mode, data access. 0x5 EATR_6 Nonsecure privileged mode, instruction fetch access. 0x6 EATR_7 Nonsecure privileged mode, data access. 0x7 EDID Error domain identifier 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only ERW_0 Read access 0 ERW_1 Write access 0x1 EST Error state 30 2 read-only EST_0 No access violation has been detected. 0 EST_1 No access violation has been detected. 0x1 EST_2 A single access violation has been detected. 0x2 EST_3 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. 0x3 DERR_W1_18 Domain Error Word1 Register 0x524 32 read-only n 0x0 0x0 EATR Error attributes 8 3 read-only EATR_0 Secure user mode, instruction fetch access. 0 EATR_1 Secure user mode, data access. 0x1 EATR_2 Secure privileged mode, instruction fetch access. 0x2 EATR_3 Secure privileged mode, data access. 0x3 EATR_4 Nonsecure user mode, instruction fetch access. 0x4 EATR_5 Nonsecure user mode, data access. 0x5 EATR_6 Nonsecure privileged mode, instruction fetch access. 0x6 EATR_7 Nonsecure privileged mode, data access. 0x7 EDID Error domain identifier 0 4 read-only EPORT Error port 24 3 read-only ERW Error read/write 11 1 read-only ERW_0 Read access 0 ERW_1 Write access 0x1 EST Error state 30 2 read-only EST_0 No access violation has been detected. 0 EST_1 No access violation has been detected. 0x1 EST_2 A single access violation has been detected. 0x2 EST_3 Multiple access violations for this domain have been detected by this submodule instance. Only the address and attribute information for the first error have been captured in DERR_W0_i and DERR_W1_i. 0x3 DERR_W3_0 Domain Error Word3 Register 0x40C 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_1 Domain Error Word3 Register 0x41C 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_16 Domain Error Word3 Register 0x50C 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_17 Domain Error Word3 Register 0x51C 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only DERR_W3_18 Domain Error Word3 Register 0x52C 32 read-write n 0x0 0x0 RECR Rearm Error Capture Registers 30 2 write-only FDID Fault Domain ID 0x1FC 32 read-write n 0x0 0x0 FDID Domain ID of Faulted Access 0 4 read-write HWCFG0 Hardware Configuration Register 0 0xF0 32 read-only n 0x0 0x0 MID Module ID 28 4 read-only NDID Number of domains 0 8 read-only NMRC Number of MRCs 16 8 read-only NMSTR Number of bus masters 8 8 read-only NPAC Number of PACs 24 4 read-only HWCFG1 Hardware Configuration Register 1 0xF4 32 read-only n 0x0 0x0 DID Domain identifier number 0 4 read-only HWCFG2 Hardware Configuration Register 2 0xF8 32 read-only n 0x0 0x0 PIDP0 Process identifier 0 1 read-only PIDP0_0 Bus master 0 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP0_1 Bus master 0 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP1 Process identifier 1 1 read-only PIDP1_0 Bus master 1 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP1_1 Bus master 1 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP10 Process identifier 10 1 read-only PIDP10_0 Bus master 10 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP10_1 Bus master 10 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP11 Process identifier 11 1 read-only PIDP11_0 Bus master 11 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP11_1 Bus master 11 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP12 Process identifier 12 1 read-only PIDP12_0 Bus master 12 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP12_1 Bus master 12 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP13 Process identifier 13 1 read-only PIDP13_0 Bus master 13 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP13_1 Bus master 13 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP14 Process identifier 14 1 read-only PIDP14_0 Bus master 14 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP14_1 Bus master 14 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP15 Process identifier 15 1 read-only PIDP15_0 Bus master 15 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP15_1 Bus master 15 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP16 Process identifier 16 1 read-only PIDP16_0 Bus master 16 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP16_1 Bus master 16 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP17 Process identifier 17 1 read-only PIDP17_0 Bus master 17 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP17_1 Bus master 17 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP18 Process identifier 18 1 read-only PIDP18_0 Bus master 18 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP18_1 Bus master 18 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP19 Process identifier 19 1 read-only PIDP19_0 Bus master 19 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP19_1 Bus master 19 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP2 Process identifier 2 1 read-only PIDP2_0 Bus master 2 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP2_1 Bus master 2 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP20 Process identifier 20 1 read-only PIDP20_0 Bus master 20 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP20_1 Bus master 20 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP21 Process identifier 21 1 read-only PIDP21_0 Bus master 21 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP21_1 Bus master 21 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP22 Process identifier 22 1 read-only PIDP22_0 Bus master 22 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP22_1 Bus master 22 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP23 Process identifier 23 1 read-only PIDP23_0 Bus master 23 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP23_1 Bus master 23 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP24 Process identifier 24 1 read-only PIDP24_0 Bus master 24 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP24_1 Bus master 24 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP25 Process identifier 25 1 read-only PIDP25_0 Bus master 25 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP25_1 Bus master 25 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP26 Process identifier 26 1 read-only PIDP26_0 Bus master 26 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP26_1 Bus master 26 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP27 Process identifier 27 1 read-only PIDP27_0 Bus master 27 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP27_1 Bus master 27 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP28 Process identifier 28 1 read-only PIDP28_0 Bus master 28 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP28_1 Bus master 28 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP29 Process identifier 29 1 read-only PIDP29_0 Bus master 29 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP29_1 Bus master 29 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP3 Process identifier 3 1 read-only PIDP3_0 Bus master 3 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP3_1 Bus master 3 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP30 Process identifier 30 1 read-only PIDP30_0 Bus master 30 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP30_1 Bus master 30 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP31 Process identifier 31 1 read-only PIDP31_0 Bus master 31 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP31_1 Bus master 31 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP4 Process identifier 4 1 read-only PIDP4_0 Bus master 4 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP4_1 Bus master 4 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP5 Process identifier 5 1 read-only PIDP5_0 Bus master 5 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP5_1 Bus master 5 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP6 Process identifier 6 1 read-only PIDP6_0 Bus master 6 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP6_1 Bus master 6 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP7 Process identifier 7 1 read-only PIDP7_0 Bus master 7 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP7_1 Bus master 7 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP8 Process identifier 8 1 read-only PIDP8_0 Bus master 8 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP8_1 Bus master 8 sources a process identifier register to the XRDC_MDAC logic. 0x1 PIDP9 Process identifier 9 1 read-only PIDP9_0 Bus master 9 does not source a process identifier register. The XRDC_MDAC logic provides the needed PID for processor cores. 0 PIDP9_1 Bus master 9 sources a process identifier register to the XRDC_MDAC logic. 0x1 HWCFG3 Hardware Configuration Register 3 0xFC 32 read-only n 0x0 0x0 PIDPn Process identifier 0 32 read-only MDACFG0 Master Domain Assignment Configuration Register 0x100 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only NCM_0 Bus master is a processor. 0 NCM_1 Bus master is a non-processor. 0x1 NMDAR Number of master domain assignment registers for bus master m 0 4 read-only MDACFG1 Master Domain Assignment Configuration Register 0x101 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only NCM_0 Bus master is a processor. 0 NCM_1 Bus master is a non-processor. 0x1 NMDAR Number of master domain assignment registers for bus master m 0 4 read-only MDACFG2 Master Domain Assignment Configuration Register 0x102 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only NCM_0 Bus master is a processor. 0 NCM_1 Bus master is a non-processor. 0x1 NMDAR Number of master domain assignment registers for bus master m 0 4 read-only MDACFG3 Master Domain Assignment Configuration Register 0x103 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only NCM_0 Bus master is a processor. 0 NCM_1 Bus master is a non-processor. 0x1 NMDAR Number of master domain assignment registers for bus master m 0 4 read-only MDACFG32 Master Domain Assignment Configuration Register 0x120 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only NCM_0 Bus master is a processor. 0 NCM_1 Bus master is a non-processor. 0x1 NMDAR Number of master domain assignment registers for bus master m 0 4 read-only MDACFG33 Master Domain Assignment Configuration Register 0x121 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only NCM_0 Bus master is a processor. 0 NCM_1 Bus master is a non-processor. 0x1 NMDAR Number of master domain assignment registers for bus master m 0 4 read-only MDACFG34 Master Domain Assignment Configuration Register 0x122 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only NCM_0 Bus master is a processor. 0 NCM_1 Bus master is a non-processor. 0x1 NMDAR Number of master domain assignment registers for bus master m 0 4 read-only MDACFG4 Master Domain Assignment Configuration Register 0x104 8 read-only n 0x0 0x0 NCM Non-CPU Master 7 1 read-only NCM_0 Bus master is a processor. 0 NCM_1 Bus master is a non-processor. 0x1 NMDAR Number of master domain assignment registers for bus master m 0 4 read-only MDA_W0_0_DFMT0 Master Domain Assignment 0x800 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DFMT_0 no description available 0 DFMT_1 no description available 0x1 DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write DIDS_0 Use MDAm[3:0] as the domain identifier. 0 DIDS_1 Use the input DID as the domain identifier. 0x1 DIDS_2 Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. 0x2 LK1 1-bit Lock 30 1 read-write LK1_0 Register can be written by any secure privileged write. 0 LK1_1 Register is locked (read-only) until the next reset. 0x1 PE Process identifier enable 6 2 read-write PE_0 No process identifier is included in the domain hit evaluation. 0 PE_1 No process identifier is included in the domain hit evaluation. 0x1 PE_2 no description available 0x2 PE_3 no description available 0x3 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write VLD_0 The Wr domain assignment is invalid. 0 VLD_1 The Wr domain assignment is valid. 0x1 MDA_W0_1_DFMT0 Master Domain Assignment 0x820 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DFMT_0 no description available 0 DFMT_1 no description available 0x1 DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write DIDS_0 Use MDAm[3:0] as the domain identifier. 0 DIDS_1 Use the input DID as the domain identifier. 0x1 DIDS_2 Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. 0x2 LK1 1-bit Lock 30 1 read-write LK1_0 Register can be written by any secure privileged write. 0 LK1_1 Register is locked (read-only) until the next reset. 0x1 PE Process identifier enable 6 2 read-write PE_0 No process identifier is included in the domain hit evaluation. 0 PE_1 No process identifier is included in the domain hit evaluation. 0x1 PE_2 no description available 0x2 PE_3 no description available 0x3 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write VLD_0 The Wr domain assignment is invalid. 0 VLD_1 The Wr domain assignment is valid. 0x1 MDA_W0_2_DFMT1 Master Domain Assignment 0x840 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DFMT_0 no description available 0 DFMT_1 no description available 0x1 DID Domain identifier 0 4 read-write DIDB DID Bypass 8 1 read-write DIDB_0 Use MDAn[3:0] as the domain identifier. 0 DIDB_1 Use the DID input as the domain identifier. 0x1 LK1 1-bit Lock 30 1 read-write LK1_0 Register can be written by any secure privileged write. 0 LK1_1 Register is locked (read-only) until the next reset. 0x1 PA Privileged attribute 4 2 read-write PA_0 Force the bus attribute for this master to user. 0 PA_1 Force the bus attribute for this master to privileged. 0x1 PA_2 Use the bus master's privileged/user attribute directly. 0x2 PA_3 Use the bus master's privileged/user attribute directly. 0x3 SA Secure attribute 6 2 read-write SA_0 Force the bus attribute for this master to secure. 0 SA_1 Force the bus attribute for this master to nonsecure. 0x1 SA_2 Use the bus master's secure/nonsecure attribute directly. 0x2 SA_3 Use the bus master's secure/nonsecure attribute directly. 0x3 VLD Valid 31 1 read-write VLD_0 The Wr domain assignment is invalid. 0 VLD_1 The Wr domain assignment is valid. 0x1 MDA_W0_32_DFMT0 Master Domain Assignment 0xC00 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DFMT_0 no description available 0 DFMT_1 no description available 0x1 DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write DIDS_0 Use MDAm[3:0] as the domain identifier. 0 DIDS_1 Use the input DID as the domain identifier. 0x1 DIDS_2 Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. 0x2 LK1 1-bit Lock 30 1 read-write LK1_0 Register can be written by any secure privileged write. 0 LK1_1 Register is locked (read-only) until the next reset. 0x1 PE Process identifier enable 6 2 read-write PE_0 No process identifier is included in the domain hit evaluation. 0 PE_1 No process identifier is included in the domain hit evaluation. 0x1 PE_2 no description available 0x2 PE_3 no description available 0x3 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write VLD_0 The Wr domain assignment is invalid. 0 VLD_1 The Wr domain assignment is valid. 0x1 MDA_W0_33_DFMT1 Master Domain Assignment 0xC20 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DFMT_0 no description available 0 DFMT_1 no description available 0x1 DID Domain identifier 0 4 read-write DIDB DID Bypass 8 1 read-write DIDB_0 Use MDAn[3:0] as the domain identifier. 0 DIDB_1 Use the DID input as the domain identifier. 0x1 LK1 1-bit Lock 30 1 read-write LK1_0 Register can be written by any secure privileged write. 0 LK1_1 Register is locked (read-only) until the next reset. 0x1 PA Privileged attribute 4 2 read-write PA_0 Force the bus attribute for this master to user. 0 PA_1 Force the bus attribute for this master to privileged. 0x1 PA_2 Use the bus master's privileged/user attribute directly. 0x2 PA_3 Use the bus master's privileged/user attribute directly. 0x3 SA Secure attribute 6 2 read-write SA_0 Force the bus attribute for this master to secure. 0 SA_1 Force the bus attribute for this master to nonsecure. 0x1 SA_2 Use the bus master's secure/nonsecure attribute directly. 0x2 SA_3 Use the bus master's secure/nonsecure attribute directly. 0x3 VLD Valid 31 1 read-write VLD_0 The Wr domain assignment is invalid. 0 VLD_1 The Wr domain assignment is valid. 0x1 MDA_W0_34_DFMT1 Master Domain Assignment 0xC40 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DFMT_0 no description available 0 DFMT_1 no description available 0x1 DID Domain identifier 0 4 read-write DIDB DID Bypass 8 1 read-write DIDB_0 Use MDAn[3:0] as the domain identifier. 0 DIDB_1 Use the DID input as the domain identifier. 0x1 LK1 1-bit Lock 30 1 read-write LK1_0 Register can be written by any secure privileged write. 0 LK1_1 Register is locked (read-only) until the next reset. 0x1 PA Privileged attribute 4 2 read-write PA_0 Force the bus attribute for this master to user. 0 PA_1 Force the bus attribute for this master to privileged. 0x1 PA_2 Use the bus master's privileged/user attribute directly. 0x2 PA_3 Use the bus master's privileged/user attribute directly. 0x3 SA Secure attribute 6 2 read-write SA_0 Force the bus attribute for this master to secure. 0 SA_1 Force the bus attribute for this master to nonsecure. 0x1 SA_2 Use the bus master's secure/nonsecure attribute directly. 0x2 SA_3 Use the bus master's secure/nonsecure attribute directly. 0x3 VLD Valid 31 1 read-write VLD_0 The Wr domain assignment is invalid. 0 VLD_1 The Wr domain assignment is valid. 0x1 MDA_W0_3_DFMT1 Master Domain Assignment 0x860 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DFMT_0 no description available 0 DFMT_1 no description available 0x1 DID Domain identifier 0 4 read-write DIDB DID Bypass 8 1 read-write DIDB_0 Use MDAn[3:0] as the domain identifier. 0 DIDB_1 Use the DID input as the domain identifier. 0x1 LK1 1-bit Lock 30 1 read-write LK1_0 Register can be written by any secure privileged write. 0 LK1_1 Register is locked (read-only) until the next reset. 0x1 PA Privileged attribute 4 2 read-write PA_0 Force the bus attribute for this master to user. 0 PA_1 Force the bus attribute for this master to privileged. 0x1 PA_2 Use the bus master's privileged/user attribute directly. 0x2 PA_3 Use the bus master's privileged/user attribute directly. 0x3 SA Secure attribute 6 2 read-write SA_0 Force the bus attribute for this master to secure. 0 SA_1 Force the bus attribute for this master to nonsecure. 0x1 SA_2 Use the bus master's secure/nonsecure attribute directly. 0x2 SA_3 Use the bus master's secure/nonsecure attribute directly. 0x3 VLD Valid 31 1 read-write VLD_0 The Wr domain assignment is invalid. 0 VLD_1 The Wr domain assignment is valid. 0x1 MDA_W0_4_DFMT1 Master Domain Assignment 0x880 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DFMT_0 no description available 0 DFMT_1 no description available 0x1 DID Domain identifier 0 4 read-write DIDB DID Bypass 8 1 read-write DIDB_0 Use MDAn[3:0] as the domain identifier. 0 DIDB_1 Use the DID input as the domain identifier. 0x1 LK1 1-bit Lock 30 1 read-write LK1_0 Register can be written by any secure privileged write. 0 LK1_1 Register is locked (read-only) until the next reset. 0x1 PA Privileged attribute 4 2 read-write PA_0 Force the bus attribute for this master to user. 0 PA_1 Force the bus attribute for this master to privileged. 0x1 PA_2 Use the bus master's privileged/user attribute directly. 0x2 PA_3 Use the bus master's privileged/user attribute directly. 0x3 SA Secure attribute 6 2 read-write SA_0 Force the bus attribute for this master to secure. 0 SA_1 Force the bus attribute for this master to nonsecure. 0x1 SA_2 Use the bus master's secure/nonsecure attribute directly. 0x2 SA_3 Use the bus master's secure/nonsecure attribute directly. 0x3 VLD Valid 31 1 read-write VLD_0 The Wr domain assignment is invalid. 0 VLD_1 The Wr domain assignment is valid. 0x1 MDA_W1_0_DFMT0 Master Domain Assignment 0x804 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DFMT_0 no description available 0 DFMT_1 no description available 0x1 DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write DIDS_0 Use MDAm[3:0] as the domain identifier. 0 DIDS_1 Use the input DID as the domain identifier. 0x1 DIDS_2 Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. 0x2 LK1 1-bit Lock 30 1 read-write LK1_0 Register can be written by any secure privileged write. 0 LK1_1 Register is locked (read-only) until the next reset. 0x1 PE Process identifier enable 6 2 read-write PE_0 No process identifier is included in the domain hit evaluation. 0 PE_1 No process identifier is included in the domain hit evaluation. 0x1 PE_2 no description available 0x2 PE_3 no description available 0x3 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write VLD_0 The Wr domain assignment is invalid. 0 VLD_1 The Wr domain assignment is valid. 0x1 MDA_W1_1_DFMT0 Master Domain Assignment 0x824 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DFMT_0 no description available 0 DFMT_1 no description available 0x1 DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write DIDS_0 Use MDAm[3:0] as the domain identifier. 0 DIDS_1 Use the input DID as the domain identifier. 0x1 DIDS_2 Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. 0x2 LK1 1-bit Lock 30 1 read-write LK1_0 Register can be written by any secure privileged write. 0 LK1_1 Register is locked (read-only) until the next reset. 0x1 PE Process identifier enable 6 2 read-write PE_0 No process identifier is included in the domain hit evaluation. 0 PE_1 No process identifier is included in the domain hit evaluation. 0x1 PE_2 no description available 0x2 PE_3 no description available 0x3 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write VLD_0 The Wr domain assignment is invalid. 0 VLD_1 The Wr domain assignment is valid. 0x1 MDA_W1_32_DFMT0 Master Domain Assignment 0xC04 32 read-write n 0x0 0x0 DFMT Domain format 29 1 read-only DFMT_0 no description available 0 DFMT_1 no description available 0x1 DID Domain identifier 0 4 read-write DIDS DID Select 4 2 read-write DIDS_0 Use MDAm[3:0] as the domain identifier. 0 DIDS_1 Use the input DID as the domain identifier. 0x1 DIDS_2 Use MDAm[3:2] concatenated with the low-order 2 bits of the input DID (DID_in[1:0]) as the domain identifier. 0x2 LK1 1-bit Lock 30 1 read-write LK1_0 Register can be written by any secure privileged write. 0 LK1_1 Register is locked (read-only) until the next reset. 0x1 PE Process identifier enable 6 2 read-write PE_0 No process identifier is included in the domain hit evaluation. 0 PE_1 No process identifier is included in the domain hit evaluation. 0x1 PE_2 no description available 0x2 PE_3 no description available 0x3 PID Process Identifier 16 6 read-write PIDM Process Identifier Mask 8 6 read-write VLD Valid 31 1 read-write VLD_0 The Wr domain assignment is invalid. 0 VLD_1 The Wr domain assignment is valid. 0x1 MRCFG0 Memory Region Configuration Register 0x140 8 read-only n 0x0 0x0 NMRGD Number of memory region descriptors for memory region controller n 0 5 read-only MRCFG1 Memory Region Configuration Register 0x141 8 read-only n 0x0 0x0 NMRGD Number of memory region descriptors for memory region controller n 0 5 read-only MRGD_W0_0_0 Memory Region Descriptor 0x2000 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write MRGD_W0_0_1 Memory Region Descriptor 0x2020 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write MRGD_W0_0_2 Memory Region Descriptor 0x2040 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write MRGD_W0_0_3 Memory Region Descriptor 0x2060 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write MRGD_W0_0_4 Memory Region Descriptor 0x2080 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write MRGD_W0_0_5 Memory Region Descriptor 0x20A0 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write MRGD_W0_0_6 Memory Region Descriptor 0x20C0 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write MRGD_W0_0_7 Memory Region Descriptor 0x20E0 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write MRGD_W0_1_0 Memory Region Descriptor 0x2200 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write MRGD_W0_1_1 Memory Region Descriptor 0x2220 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write MRGD_W0_1_2 Memory Region Descriptor 0x2240 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write MRGD_W0_1_3 Memory Region Descriptor 0x2260 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write MRGD_W0_1_4 Memory Region Descriptor 0x2280 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write MRGD_W0_1_5 Memory Region Descriptor 0x22A0 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write MRGD_W0_1_6 Memory Region Descriptor 0x22C0 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write MRGD_W0_1_7 Memory Region Descriptor 0x22E0 32 read-write n 0x0 0x0 SRTADDR Start Address 5 27 read-write MRGD_W1_0_0 Memory Region Descriptor 0x2004 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write MRGD_W1_0_1 Memory Region Descriptor 0x2024 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write MRGD_W1_0_2 Memory Region Descriptor 0x2044 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write MRGD_W1_0_3 Memory Region Descriptor 0x2064 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write MRGD_W1_0_4 Memory Region Descriptor 0x2084 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write MRGD_W1_0_5 Memory Region Descriptor 0x20A4 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write MRGD_W1_0_6 Memory Region Descriptor 0x20C4 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write MRGD_W1_0_7 Memory Region Descriptor 0x20E4 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write MRGD_W1_1_0 Memory Region Descriptor 0x2204 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write MRGD_W1_1_1 Memory Region Descriptor 0x2224 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write MRGD_W1_1_2 Memory Region Descriptor 0x2244 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write MRGD_W1_1_3 Memory Region Descriptor 0x2264 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write MRGD_W1_1_4 Memory Region Descriptor 0x2284 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write MRGD_W1_1_5 Memory Region Descriptor 0x22A4 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write MRGD_W1_1_6 Memory Region Descriptor 0x22C4 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write MRGD_W1_1_7 Memory Region Descriptor 0x22E4 32 read-write n 0x0 0x0 ENDADDR End Address 5 27 read-write MRGD_W2_0_0 Memory Region Descriptor 0x2008 32 read-write n 0x0 0x0 D0SEL Domain 0 select 0 3 read-write D1SEL Domain 1 select 3 3 read-write D2SEL Domain 2 select 6 3 read-write EALO Exclusive Access Lock Owner 24 4 read-only MRGD_W2_0_1 Memory Region Descriptor 0x2028 32 read-write n 0x0 0x0 D0SEL Domain 0 select 0 3 read-write D1SEL Domain 1 select 3 3 read-write D2SEL Domain 2 select 6 3 read-write EALO Exclusive Access Lock Owner 24 4 read-only MRGD_W2_0_2 Memory Region Descriptor 0x2048 32 read-write n 0x0 0x0 D0SEL Domain 0 select 0 3 read-write D1SEL Domain 1 select 3 3 read-write D2SEL Domain 2 select 6 3 read-write EALO Exclusive Access Lock Owner 24 4 read-only MRGD_W2_0_3 Memory Region Descriptor 0x2068 32 read-write n 0x0 0x0 D0SEL Domain 0 select 0 3 read-write D1SEL Domain 1 select 3 3 read-write D2SEL Domain 2 select 6 3 read-write EALO Exclusive Access Lock Owner 24 4 read-only MRGD_W2_0_4 Memory Region Descriptor 0x2088 32 read-write n 0x0 0x0 D0SEL Domain 0 select 0 3 read-write D1SEL Domain 1 select 3 3 read-write D2SEL Domain 2 select 6 3 read-write EALO Exclusive Access Lock Owner 24 4 read-only MRGD_W2_0_5 Memory Region Descriptor 0x20A8 32 read-write n 0x0 0x0 D0SEL Domain 0 select 0 3 read-write D1SEL Domain 1 select 3 3 read-write D2SEL Domain 2 select 6 3 read-write EALO Exclusive Access Lock Owner 24 4 read-only MRGD_W2_0_6 Memory Region Descriptor 0x20C8 32 read-write n 0x0 0x0 D0SEL Domain 0 select 0 3 read-write D1SEL Domain 1 select 3 3 read-write D2SEL Domain 2 select 6 3 read-write EALO Exclusive Access Lock Owner 24 4 read-only MRGD_W2_0_7 Memory Region Descriptor 0x20E8 32 read-write n 0x0 0x0 D0SEL Domain 0 select 0 3 read-write D1SEL Domain 1 select 3 3 read-write D2SEL Domain 2 select 6 3 read-write EALO Exclusive Access Lock Owner 24 4 read-only MRGD_W2_1_0 Memory Region Descriptor 0x2208 32 read-write n 0x0 0x0 D0SEL Domain 0 select 0 3 read-write D1SEL Domain 1 select 3 3 read-write D2SEL Domain 2 select 6 3 read-write EALO Exclusive Access Lock Owner 24 4 read-only MRGD_W2_1_1 Memory Region Descriptor 0x2228 32 read-write n 0x0 0x0 D0SEL Domain 0 select 0 3 read-write D1SEL Domain 1 select 3 3 read-write D2SEL Domain 2 select 6 3 read-write EALO Exclusive Access Lock Owner 24 4 read-only MRGD_W2_1_2 Memory Region Descriptor 0x2248 32 read-write n 0x0 0x0 D0SEL Domain 0 select 0 3 read-write D1SEL Domain 1 select 3 3 read-write D2SEL Domain 2 select 6 3 read-write EALO Exclusive Access Lock Owner 24 4 read-only MRGD_W2_1_3 Memory Region Descriptor 0x2268 32 read-write n 0x0 0x0 D0SEL Domain 0 select 0 3 read-write D1SEL Domain 1 select 3 3 read-write D2SEL Domain 2 select 6 3 read-write EALO Exclusive Access Lock Owner 24 4 read-only MRGD_W2_1_4 Memory Region Descriptor 0x2288 32 read-write n 0x0 0x0 D0SEL Domain 0 select 0 3 read-write D1SEL Domain 1 select 3 3 read-write D2SEL Domain 2 select 6 3 read-write EALO Exclusive Access Lock Owner 24 4 read-only MRGD_W2_1_5 Memory Region Descriptor 0x22A8 32 read-write n 0x0 0x0 D0SEL Domain 0 select 0 3 read-write D1SEL Domain 1 select 3 3 read-write D2SEL Domain 2 select 6 3 read-write EALO Exclusive Access Lock Owner 24 4 read-only MRGD_W2_1_6 Memory Region Descriptor 0x22C8 32 read-write n 0x0 0x0 D0SEL Domain 0 select 0 3 read-write D1SEL Domain 1 select 3 3 read-write D2SEL Domain 2 select 6 3 read-write EALO Exclusive Access Lock Owner 24 4 read-only MRGD_W2_1_7 Memory Region Descriptor 0x22E8 32 read-write n 0x0 0x0 D0SEL Domain 0 select 0 3 read-write D1SEL Domain 1 select 3 3 read-write D2SEL Domain 2 select 6 3 read-write EALO Exclusive Access Lock Owner 24 4 read-only MRGD_W3_0_0 Memory Region Descriptor 0x200C 32 read-write n 0x0 0x0 CR Code Region Indicator 31 1 read-write EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 MRGD_W3_0_1 Memory Region Descriptor 0x202C 32 read-write n 0x0 0x0 CR Code Region Indicator 31 1 read-write EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 MRGD_W3_0_2 Memory Region Descriptor 0x204C 32 read-write n 0x0 0x0 CR Code Region Indicator 31 1 read-write EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 MRGD_W3_0_3 Memory Region Descriptor 0x206C 32 read-write n 0x0 0x0 CR Code Region Indicator 31 1 read-write EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 MRGD_W3_0_4 Memory Region Descriptor 0x208C 32 read-write n 0x0 0x0 CR Code Region Indicator 31 1 read-write EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 MRGD_W3_0_5 Memory Region Descriptor 0x20AC 32 read-write n 0x0 0x0 CR Code Region Indicator 31 1 read-write EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 MRGD_W3_0_6 Memory Region Descriptor 0x20CC 32 read-write n 0x0 0x0 CR Code Region Indicator 31 1 read-write EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 MRGD_W3_0_7 Memory Region Descriptor 0x20EC 32 read-write n 0x0 0x0 CR Code Region Indicator 31 1 read-write EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 MRGD_W3_1_0 Memory Region Descriptor 0x220C 32 read-write n 0x0 0x0 CR Code Region Indicator 31 1 read-write EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 MRGD_W3_1_1 Memory Region Descriptor 0x222C 32 read-write n 0x0 0x0 CR Code Region Indicator 31 1 read-write EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 MRGD_W3_1_2 Memory Region Descriptor 0x224C 32 read-write n 0x0 0x0 CR Code Region Indicator 31 1 read-write EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 MRGD_W3_1_3 Memory Region Descriptor 0x226C 32 read-write n 0x0 0x0 CR Code Region Indicator 31 1 read-write EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 MRGD_W3_1_4 Memory Region Descriptor 0x228C 32 read-write n 0x0 0x0 CR Code Region Indicator 31 1 read-write EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 MRGD_W3_1_5 Memory Region Descriptor 0x22AC 32 read-write n 0x0 0x0 CR Code Region Indicator 31 1 read-write EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 MRGD_W3_1_6 Memory Region Descriptor 0x22CC 32 read-write n 0x0 0x0 CR Code Region Indicator 31 1 read-write EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 MRGD_W3_1_7 Memory Region Descriptor 0x22EC 32 read-write n 0x0 0x0 CR Code Region Indicator 31 1 read-write EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 MRGD_W4_0_0 Memory Region Descriptor 0x2010 32 read-write n 0x0 0x0 ACCSET1 SET 1 of Programmable access flags. 0 12 read-write ACCSET2 SET 2 of Programmable access flags. 16 12 read-write LK2 Lock 29 2 read-write LK2_0 no description available 0 LK2_1 no description available 0x1 LK2_2 no description available 0x2 LK2_3 no description available 0x3 LKAS1 Lock ACCSET1 12 1 read-write LKAS1_0 Writes to ACCSET1 affect lesser modes 0 LKAS1_1 ACCSET1 cannot be modified 0x1 LKAS2 Lock ACCSET2 28 1 read-write LKAS2_0 Writes to ACCSET2 affect lesser modes 0 LKAS2_1 ACCSET2 cannot be modified 0x1 VLD Valid 31 1 read-write VLD_0 no description available 0 VLD_1 no description available 0x1 MRGD_W4_0_1 Memory Region Descriptor 0x2030 32 read-write n 0x0 0x0 ACCSET1 SET 1 of Programmable access flags. 0 12 read-write ACCSET2 SET 2 of Programmable access flags. 16 12 read-write LK2 Lock 29 2 read-write LK2_0 no description available 0 LK2_1 no description available 0x1 LK2_2 no description available 0x2 LK2_3 no description available 0x3 LKAS1 Lock ACCSET1 12 1 read-write LKAS1_0 Writes to ACCSET1 affect lesser modes 0 LKAS1_1 ACCSET1 cannot be modified 0x1 LKAS2 Lock ACCSET2 28 1 read-write LKAS2_0 Writes to ACCSET2 affect lesser modes 0 LKAS2_1 ACCSET2 cannot be modified 0x1 VLD Valid 31 1 read-write VLD_0 no description available 0 VLD_1 no description available 0x1 MRGD_W4_0_2 Memory Region Descriptor 0x2050 32 read-write n 0x0 0x0 ACCSET1 SET 1 of Programmable access flags. 0 12 read-write ACCSET2 SET 2 of Programmable access flags. 16 12 read-write LK2 Lock 29 2 read-write LK2_0 no description available 0 LK2_1 no description available 0x1 LK2_2 no description available 0x2 LK2_3 no description available 0x3 LKAS1 Lock ACCSET1 12 1 read-write LKAS1_0 Writes to ACCSET1 affect lesser modes 0 LKAS1_1 ACCSET1 cannot be modified 0x1 LKAS2 Lock ACCSET2 28 1 read-write LKAS2_0 Writes to ACCSET2 affect lesser modes 0 LKAS2_1 ACCSET2 cannot be modified 0x1 VLD Valid 31 1 read-write VLD_0 no description available 0 VLD_1 no description available 0x1 MRGD_W4_0_3 Memory Region Descriptor 0x2070 32 read-write n 0x0 0x0 ACCSET1 SET 1 of Programmable access flags. 0 12 read-write ACCSET2 SET 2 of Programmable access flags. 16 12 read-write LK2 Lock 29 2 read-write LK2_0 no description available 0 LK2_1 no description available 0x1 LK2_2 no description available 0x2 LK2_3 no description available 0x3 LKAS1 Lock ACCSET1 12 1 read-write LKAS1_0 Writes to ACCSET1 affect lesser modes 0 LKAS1_1 ACCSET1 cannot be modified 0x1 LKAS2 Lock ACCSET2 28 1 read-write LKAS2_0 Writes to ACCSET2 affect lesser modes 0 LKAS2_1 ACCSET2 cannot be modified 0x1 VLD Valid 31 1 read-write VLD_0 no description available 0 VLD_1 no description available 0x1 MRGD_W4_0_4 Memory Region Descriptor 0x2090 32 read-write n 0x0 0x0 ACCSET1 SET 1 of Programmable access flags. 0 12 read-write ACCSET2 SET 2 of Programmable access flags. 16 12 read-write LK2 Lock 29 2 read-write LK2_0 no description available 0 LK2_1 no description available 0x1 LK2_2 no description available 0x2 LK2_3 no description available 0x3 LKAS1 Lock ACCSET1 12 1 read-write LKAS1_0 Writes to ACCSET1 affect lesser modes 0 LKAS1_1 ACCSET1 cannot be modified 0x1 LKAS2 Lock ACCSET2 28 1 read-write LKAS2_0 Writes to ACCSET2 affect lesser modes 0 LKAS2_1 ACCSET2 cannot be modified 0x1 VLD Valid 31 1 read-write VLD_0 no description available 0 VLD_1 no description available 0x1 MRGD_W4_0_5 Memory Region Descriptor 0x20B0 32 read-write n 0x0 0x0 ACCSET1 SET 1 of Programmable access flags. 0 12 read-write ACCSET2 SET 2 of Programmable access flags. 16 12 read-write LK2 Lock 29 2 read-write LK2_0 no description available 0 LK2_1 no description available 0x1 LK2_2 no description available 0x2 LK2_3 no description available 0x3 LKAS1 Lock ACCSET1 12 1 read-write LKAS1_0 Writes to ACCSET1 affect lesser modes 0 LKAS1_1 ACCSET1 cannot be modified 0x1 LKAS2 Lock ACCSET2 28 1 read-write LKAS2_0 Writes to ACCSET2 affect lesser modes 0 LKAS2_1 ACCSET2 cannot be modified 0x1 VLD Valid 31 1 read-write VLD_0 no description available 0 VLD_1 no description available 0x1 MRGD_W4_0_6 Memory Region Descriptor 0x20D0 32 read-write n 0x0 0x0 ACCSET1 SET 1 of Programmable access flags. 0 12 read-write ACCSET2 SET 2 of Programmable access flags. 16 12 read-write LK2 Lock 29 2 read-write LK2_0 no description available 0 LK2_1 no description available 0x1 LK2_2 no description available 0x2 LK2_3 no description available 0x3 LKAS1 Lock ACCSET1 12 1 read-write LKAS1_0 Writes to ACCSET1 affect lesser modes 0 LKAS1_1 ACCSET1 cannot be modified 0x1 LKAS2 Lock ACCSET2 28 1 read-write LKAS2_0 Writes to ACCSET2 affect lesser modes 0 LKAS2_1 ACCSET2 cannot be modified 0x1 VLD Valid 31 1 read-write VLD_0 no description available 0 VLD_1 no description available 0x1 MRGD_W4_0_7 Memory Region Descriptor 0x20F0 32 read-write n 0x0 0x0 ACCSET1 SET 1 of Programmable access flags. 0 12 read-write ACCSET2 SET 2 of Programmable access flags. 16 12 read-write LK2 Lock 29 2 read-write LK2_0 no description available 0 LK2_1 no description available 0x1 LK2_2 no description available 0x2 LK2_3 no description available 0x3 LKAS1 Lock ACCSET1 12 1 read-write LKAS1_0 Writes to ACCSET1 affect lesser modes 0 LKAS1_1 ACCSET1 cannot be modified 0x1 LKAS2 Lock ACCSET2 28 1 read-write LKAS2_0 Writes to ACCSET2 affect lesser modes 0 LKAS2_1 ACCSET2 cannot be modified 0x1 VLD Valid 31 1 read-write VLD_0 no description available 0 VLD_1 no description available 0x1 MRGD_W4_1_0 Memory Region Descriptor 0x2210 32 read-write n 0x0 0x0 ACCSET1 SET 1 of Programmable access flags. 0 12 read-write ACCSET2 SET 2 of Programmable access flags. 16 12 read-write LK2 Lock 29 2 read-write LK2_0 no description available 0 LK2_1 no description available 0x1 LK2_2 no description available 0x2 LK2_3 no description available 0x3 LKAS1 Lock ACCSET1 12 1 read-write LKAS1_0 Writes to ACCSET1 affect lesser modes 0 LKAS1_1 ACCSET1 cannot be modified 0x1 LKAS2 Lock ACCSET2 28 1 read-write LKAS2_0 Writes to ACCSET2 affect lesser modes 0 LKAS2_1 ACCSET2 cannot be modified 0x1 VLD Valid 31 1 read-write VLD_0 no description available 0 VLD_1 no description available 0x1 MRGD_W4_1_1 Memory Region Descriptor 0x2230 32 read-write n 0x0 0x0 ACCSET1 SET 1 of Programmable access flags. 0 12 read-write ACCSET2 SET 2 of Programmable access flags. 16 12 read-write LK2 Lock 29 2 read-write LK2_0 no description available 0 LK2_1 no description available 0x1 LK2_2 no description available 0x2 LK2_3 no description available 0x3 LKAS1 Lock ACCSET1 12 1 read-write LKAS1_0 Writes to ACCSET1 affect lesser modes 0 LKAS1_1 ACCSET1 cannot be modified 0x1 LKAS2 Lock ACCSET2 28 1 read-write LKAS2_0 Writes to ACCSET2 affect lesser modes 0 LKAS2_1 ACCSET2 cannot be modified 0x1 VLD Valid 31 1 read-write VLD_0 no description available 0 VLD_1 no description available 0x1 MRGD_W4_1_2 Memory Region Descriptor 0x2250 32 read-write n 0x0 0x0 ACCSET1 SET 1 of Programmable access flags. 0 12 read-write ACCSET2 SET 2 of Programmable access flags. 16 12 read-write LK2 Lock 29 2 read-write LK2_0 no description available 0 LK2_1 no description available 0x1 LK2_2 no description available 0x2 LK2_3 no description available 0x3 LKAS1 Lock ACCSET1 12 1 read-write LKAS1_0 Writes to ACCSET1 affect lesser modes 0 LKAS1_1 ACCSET1 cannot be modified 0x1 LKAS2 Lock ACCSET2 28 1 read-write LKAS2_0 Writes to ACCSET2 affect lesser modes 0 LKAS2_1 ACCSET2 cannot be modified 0x1 VLD Valid 31 1 read-write VLD_0 no description available 0 VLD_1 no description available 0x1 MRGD_W4_1_3 Memory Region Descriptor 0x2270 32 read-write n 0x0 0x0 ACCSET1 SET 1 of Programmable access flags. 0 12 read-write ACCSET2 SET 2 of Programmable access flags. 16 12 read-write LK2 Lock 29 2 read-write LK2_0 no description available 0 LK2_1 no description available 0x1 LK2_2 no description available 0x2 LK2_3 no description available 0x3 LKAS1 Lock ACCSET1 12 1 read-write LKAS1_0 Writes to ACCSET1 affect lesser modes 0 LKAS1_1 ACCSET1 cannot be modified 0x1 LKAS2 Lock ACCSET2 28 1 read-write LKAS2_0 Writes to ACCSET2 affect lesser modes 0 LKAS2_1 ACCSET2 cannot be modified 0x1 VLD Valid 31 1 read-write VLD_0 no description available 0 VLD_1 no description available 0x1 MRGD_W4_1_4 Memory Region Descriptor 0x2290 32 read-write n 0x0 0x0 ACCSET1 SET 1 of Programmable access flags. 0 12 read-write ACCSET2 SET 2 of Programmable access flags. 16 12 read-write LK2 Lock 29 2 read-write LK2_0 no description available 0 LK2_1 no description available 0x1 LK2_2 no description available 0x2 LK2_3 no description available 0x3 LKAS1 Lock ACCSET1 12 1 read-write LKAS1_0 Writes to ACCSET1 affect lesser modes 0 LKAS1_1 ACCSET1 cannot be modified 0x1 LKAS2 Lock ACCSET2 28 1 read-write LKAS2_0 Writes to ACCSET2 affect lesser modes 0 LKAS2_1 ACCSET2 cannot be modified 0x1 VLD Valid 31 1 read-write VLD_0 no description available 0 VLD_1 no description available 0x1 MRGD_W4_1_5 Memory Region Descriptor 0x22B0 32 read-write n 0x0 0x0 ACCSET1 SET 1 of Programmable access flags. 0 12 read-write ACCSET2 SET 2 of Programmable access flags. 16 12 read-write LK2 Lock 29 2 read-write LK2_0 no description available 0 LK2_1 no description available 0x1 LK2_2 no description available 0x2 LK2_3 no description available 0x3 LKAS1 Lock ACCSET1 12 1 read-write LKAS1_0 Writes to ACCSET1 affect lesser modes 0 LKAS1_1 ACCSET1 cannot be modified 0x1 LKAS2 Lock ACCSET2 28 1 read-write LKAS2_0 Writes to ACCSET2 affect lesser modes 0 LKAS2_1 ACCSET2 cannot be modified 0x1 VLD Valid 31 1 read-write VLD_0 no description available 0 VLD_1 no description available 0x1 MRGD_W4_1_6 Memory Region Descriptor 0x22D0 32 read-write n 0x0 0x0 ACCSET1 SET 1 of Programmable access flags. 0 12 read-write ACCSET2 SET 2 of Programmable access flags. 16 12 read-write LK2 Lock 29 2 read-write LK2_0 no description available 0 LK2_1 no description available 0x1 LK2_2 no description available 0x2 LK2_3 no description available 0x3 LKAS1 Lock ACCSET1 12 1 read-write LKAS1_0 Writes to ACCSET1 affect lesser modes 0 LKAS1_1 ACCSET1 cannot be modified 0x1 LKAS2 Lock ACCSET2 28 1 read-write LKAS2_0 Writes to ACCSET2 affect lesser modes 0 LKAS2_1 ACCSET2 cannot be modified 0x1 VLD Valid 31 1 read-write VLD_0 no description available 0 VLD_1 no description available 0x1 MRGD_W4_1_7 Memory Region Descriptor 0x22F0 32 read-write n 0x0 0x0 ACCSET1 SET 1 of Programmable access flags. 0 12 read-write ACCSET2 SET 2 of Programmable access flags. 16 12 read-write LK2 Lock 29 2 read-write LK2_0 no description available 0 LK2_1 no description available 0x1 LK2_2 no description available 0x2 LK2_3 no description available 0x3 LKAS1 Lock ACCSET1 12 1 read-write LKAS1_0 Writes to ACCSET1 affect lesser modes 0 LKAS1_1 ACCSET1 cannot be modified 0x1 LKAS2 Lock ACCSET2 28 1 read-write LKAS2_0 Writes to ACCSET2 affect lesser modes 0 LKAS2_1 ACCSET2 cannot be modified 0x1 VLD Valid 31 1 read-write VLD_0 no description available 0 VLD_1 no description available 0x1 PDAC_W0_0_1 Peripheral Domain Access Control 0x1008 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_12 Peripheral Domain Access Control 0x1060 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_125 Peripheral Domain Access Control 0x13E8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_126 Peripheral Domain Access Control 0x13F0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_127 Peripheral Domain Access Control 0x13F8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_15 Peripheral Domain Access Control 0x1078 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_20 Peripheral Domain Access Control 0x10A0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_21 Peripheral Domain Access Control 0x10A8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_22 Peripheral Domain Access Control 0x10B0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_23 Peripheral Domain Access Control 0x10B8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_27 Peripheral Domain Access Control 0x10D8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_3 Peripheral Domain Access Control 0x1018 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_32 Peripheral Domain Access Control 0x1100 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_33 Peripheral Domain Access Control 0x1108 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_34 Peripheral Domain Access Control 0x1110 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_35 Peripheral Domain Access Control 0x1118 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_36 Peripheral Domain Access Control 0x1120 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_37 Peripheral Domain Access Control 0x1128 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_38 Peripheral Domain Access Control 0x1130 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_39 Peripheral Domain Access Control 0x1138 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_4 Peripheral Domain Access Control 0x1020 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_40 Peripheral Domain Access Control 0x1140 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_41 Peripheral Domain Access Control 0x1148 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_42 Peripheral Domain Access Control 0x1150 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_43 Peripheral Domain Access Control 0x1158 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_44 Peripheral Domain Access Control 0x1160 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_45 Peripheral Domain Access Control 0x1168 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_46 Peripheral Domain Access Control 0x1170 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_47 Peripheral Domain Access Control 0x1178 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_48 Peripheral Domain Access Control 0x1180 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_49 Peripheral Domain Access Control 0x1188 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_50 Peripheral Domain Access Control 0x1190 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_51 Peripheral Domain Access Control 0x1198 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_52 Peripheral Domain Access Control 0x11A0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_53 Peripheral Domain Access Control 0x11A8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_54 Peripheral Domain Access Control 0x11B0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_55 Peripheral Domain Access Control 0x11B8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_56 Peripheral Domain Access Control 0x11C0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_57 Peripheral Domain Access Control 0x11C8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_58 Peripheral Domain Access Control 0x11D0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_59 Peripheral Domain Access Control 0x11D8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_60 Peripheral Domain Access Control 0x11E0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_61 Peripheral Domain Access Control 0x11E8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_62 Peripheral Domain Access Control 0x11F0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_63 Peripheral Domain Access Control 0x11F8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_64 Peripheral Domain Access Control 0x1200 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_65 Peripheral Domain Access Control 0x1208 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_66 Peripheral Domain Access Control 0x1210 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_67 Peripheral Domain Access Control 0x1218 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_68 Peripheral Domain Access Control 0x1220 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_69 Peripheral Domain Access Control 0x1228 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_70 Peripheral Domain Access Control 0x1230 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_71 Peripheral Domain Access Control 0x1238 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_72 Peripheral Domain Access Control 0x1240 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_73 Peripheral Domain Access Control 0x1248 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_74 Peripheral Domain Access Control 0x1250 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_75 Peripheral Domain Access Control 0x1258 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_76 Peripheral Domain Access Control 0x1260 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_77 Peripheral Domain Access Control 0x1268 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_78 Peripheral Domain Access Control 0x1270 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_8 Peripheral Domain Access Control 0x1040 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_0_9 Peripheral Domain Access Control 0x1048 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_15 Peripheral Domain Access Control 0x1478 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_27 Peripheral Domain Access Control 0x14D8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_32 Peripheral Domain Access Control 0x1500 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_33 Peripheral Domain Access Control 0x1508 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_34 Peripheral Domain Access Control 0x1510 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_35 Peripheral Domain Access Control 0x1518 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_36 Peripheral Domain Access Control 0x1520 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_37 Peripheral Domain Access Control 0x1528 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_38 Peripheral Domain Access Control 0x1530 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_39 Peripheral Domain Access Control 0x1538 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_40 Peripheral Domain Access Control 0x1540 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_41 Peripheral Domain Access Control 0x1548 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_42 Peripheral Domain Access Control 0x1550 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_43 Peripheral Domain Access Control 0x1558 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_44 Peripheral Domain Access Control 0x1560 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_45 Peripheral Domain Access Control 0x1568 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_46 Peripheral Domain Access Control 0x1570 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_47 Peripheral Domain Access Control 0x1578 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_48 Peripheral Domain Access Control 0x1580 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_49 Peripheral Domain Access Control 0x1588 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_50 Peripheral Domain Access Control 0x1590 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_51 Peripheral Domain Access Control 0x1598 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_52 Peripheral Domain Access Control 0x15A0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_53 Peripheral Domain Access Control 0x15A8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_54 Peripheral Domain Access Control 0x15B0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_55 Peripheral Domain Access Control 0x15B8 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_56 Peripheral Domain Access Control 0x15C0 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_8 Peripheral Domain Access Control 0x1440 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_1_9 Peripheral Domain Access Control 0x1448 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_2_16 Peripheral Domain Access Control 0x1880 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W0_2_32 Peripheral Domain Access Control 0x1900 32 read-write n 0x0 0x0 D0ACP Domain 0 access control policy 0 3 read-write D1ACP Domain 1 access control policy 3 3 read-write D2ACP Domain 2 access control policy 6 3 read-write EALO Excessive Access Lock Owner 24 4 read-only PDAC_W1_0_1 Peripheral Domain Access Control 0x100C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_12 Peripheral Domain Access Control 0x1064 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_125 Peripheral Domain Access Control 0x13EC 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_126 Peripheral Domain Access Control 0x13F4 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_127 Peripheral Domain Access Control 0x13FC 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_15 Peripheral Domain Access Control 0x107C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_20 Peripheral Domain Access Control 0x10A4 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_21 Peripheral Domain Access Control 0x10AC 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_22 Peripheral Domain Access Control 0x10B4 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_23 Peripheral Domain Access Control 0x10BC 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_27 Peripheral Domain Access Control 0x10DC 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_3 Peripheral Domain Access Control 0x101C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_32 Peripheral Domain Access Control 0x1104 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_33 Peripheral Domain Access Control 0x110C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_34 Peripheral Domain Access Control 0x1114 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_35 Peripheral Domain Access Control 0x111C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_36 Peripheral Domain Access Control 0x1124 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_37 Peripheral Domain Access Control 0x112C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_38 Peripheral Domain Access Control 0x1134 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_39 Peripheral Domain Access Control 0x113C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_4 Peripheral Domain Access Control 0x1024 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_40 Peripheral Domain Access Control 0x1144 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_41 Peripheral Domain Access Control 0x114C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_42 Peripheral Domain Access Control 0x1154 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_43 Peripheral Domain Access Control 0x115C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_44 Peripheral Domain Access Control 0x1164 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_45 Peripheral Domain Access Control 0x116C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_46 Peripheral Domain Access Control 0x1174 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_47 Peripheral Domain Access Control 0x117C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_48 Peripheral Domain Access Control 0x1184 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_49 Peripheral Domain Access Control 0x118C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_50 Peripheral Domain Access Control 0x1194 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_51 Peripheral Domain Access Control 0x119C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_52 Peripheral Domain Access Control 0x11A4 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_53 Peripheral Domain Access Control 0x11AC 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_54 Peripheral Domain Access Control 0x11B4 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_55 Peripheral Domain Access Control 0x11BC 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_56 Peripheral Domain Access Control 0x11C4 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_57 Peripheral Domain Access Control 0x11CC 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_58 Peripheral Domain Access Control 0x11D4 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_59 Peripheral Domain Access Control 0x11DC 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_60 Peripheral Domain Access Control 0x11E4 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_61 Peripheral Domain Access Control 0x11EC 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_62 Peripheral Domain Access Control 0x11F4 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_63 Peripheral Domain Access Control 0x11FC 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_64 Peripheral Domain Access Control 0x1204 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_65 Peripheral Domain Access Control 0x120C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_66 Peripheral Domain Access Control 0x1214 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_67 Peripheral Domain Access Control 0x121C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_68 Peripheral Domain Access Control 0x1224 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_69 Peripheral Domain Access Control 0x122C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_70 Peripheral Domain Access Control 0x1234 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_71 Peripheral Domain Access Control 0x123C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_72 Peripheral Domain Access Control 0x1244 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_73 Peripheral Domain Access Control 0x124C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_74 Peripheral Domain Access Control 0x1254 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_75 Peripheral Domain Access Control 0x125C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_76 Peripheral Domain Access Control 0x1264 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_77 Peripheral Domain Access Control 0x126C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_78 Peripheral Domain Access Control 0x1274 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_8 Peripheral Domain Access Control 0x1044 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_0_9 Peripheral Domain Access Control 0x104C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_15 Peripheral Domain Access Control 0x147C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_27 Peripheral Domain Access Control 0x14DC 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_32 Peripheral Domain Access Control 0x1504 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_33 Peripheral Domain Access Control 0x150C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_34 Peripheral Domain Access Control 0x1514 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_35 Peripheral Domain Access Control 0x151C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_36 Peripheral Domain Access Control 0x1524 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_37 Peripheral Domain Access Control 0x152C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_38 Peripheral Domain Access Control 0x1534 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_39 Peripheral Domain Access Control 0x153C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_40 Peripheral Domain Access Control 0x1544 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_41 Peripheral Domain Access Control 0x154C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_42 Peripheral Domain Access Control 0x1554 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_43 Peripheral Domain Access Control 0x155C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_44 Peripheral Domain Access Control 0x1564 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_45 Peripheral Domain Access Control 0x156C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_46 Peripheral Domain Access Control 0x1574 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_47 Peripheral Domain Access Control 0x157C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_48 Peripheral Domain Access Control 0x1584 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_49 Peripheral Domain Access Control 0x158C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_50 Peripheral Domain Access Control 0x1594 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_51 Peripheral Domain Access Control 0x159C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_52 Peripheral Domain Access Control 0x15A4 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_53 Peripheral Domain Access Control 0x15AC 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_54 Peripheral Domain Access Control 0x15B4 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_55 Peripheral Domain Access Control 0x15BC 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_56 Peripheral Domain Access Control 0x15C4 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_8 Peripheral Domain Access Control 0x1444 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_1_9 Peripheral Domain Access Control 0x144C 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_2_16 Peripheral Domain Access Control 0x1884 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PDAC_W1_2_32 Peripheral Domain Access Control 0x1904 32 read-write n 0x0 0x0 EAL Exclusive Access Lock 24 2 read-write EAL_0 Lock disabled 0 EAL_1 Lock disabled until next reset 0x1 EAL_2 Lock enabled, lock state = available 0x2 EAL_3 Lock enabled, lock state = not available 0x3 LK2 Lock 29 2 read-write LK2_0 Entire PDACs can be written. 0 LK2_1 Entire PDACs can be written. 0x1 LK2_2 Domain x can only update the DxACP field and the LK2 field no other PDACs fields can be written. 0x2 LK2_3 PDACs is locked (read-only) until the next reset. 0x3 VLD Valid 31 1 read-write VLD_0 The PDACs assignment is invalid. 0 VLD_1 The PDACs assignment is valid. 0x1 PID0 Process Identifier 0x700 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write LK2_0 Register can be written by any secure privileged write. 0 LK2_1 Register can be written by any secure privileged write. 0x1 LK2_2 Register can only be written by a secure privileged write from bus master m. 0x2 LK2_3 Register is locked (read-only) until the next reset. 0x3 PID Process identifier 0 6 read-write SP4SM Special 4-state model 27 1 read-write TSM Three-state model 28 1 read-write PID1 Process Identifier 0x704 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write LK2_0 Register can be written by any secure privileged write. 0 LK2_1 Register can be written by any secure privileged write. 0x1 LK2_2 Register can only be written by a secure privileged write from bus master m. 0x2 LK2_3 Register is locked (read-only) until the next reset. 0x3 PID Process identifier 0 6 read-write SP4SM Special 4-state model 27 1 read-write TSM Three-state model 28 1 read-write PID32 Process Identifier 0x780 32 read-write n 0x0 0x0 LK2 Lock 29 2 read-write LK2_0 Register can be written by any secure privileged write. 0 LK2_1 Register can be written by any secure privileged write. 0x1 LK2_2 Register can only be written by a secure privileged write from bus master m. 0x2 LK2_3 Register is locked (read-only) until the next reset. 0x3 PID Process identifier 0 6 read-write SP4SM Special 4-state model 27 1 read-write TSM Three-state model 28 1 read-write